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SiGe quantum wells
703
World abstracts on microelectronics and reliability using a single cascadable ASIC. With a minimum system configuration of four identical ASIC’s produced by using 1.0 p CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude. A hi-density C4/CBGA interconnect technology for a CMOS microprocessor. GARY B. KROMANN, R. DAVID GERKE and WAYNE WEI-XU HUANG. IEEE Transactions on Components, Packaging and Manufacturing Technology-Part B, 19 (1). 166 (1996). The application of a controlled-collapse chip connection (C4), ceramic-ball-grid array (CBGA) single-chip package to the Motorola 88110 RISC CMOS microprocessor is presented. Also presented are the zero-level to second-level interconnection technologies and the various design considerations: from the onchip redistribution metal to the printed-circuit board definition. In addition to an overview of the interconnect technology, we discuss the: (1) printedcircuit board design, (2) first-level and second-level assembly. (3) electrical modeling and characterization, (4) thermal management. and (5) controlled-collapse chip connection (C4) and ceramic-ball-grid array (CBGA) interconnection reliability and solder-fatigue life estimates. For this study four discipline-specific technology test vehicles were used to evaluate the assembly, electrical, thermal, and reliability aspects of this C4,‘CBGA interconnect technology. The design and use of each test vehicle is presented. In contrast to a 51 mm, wirebond pin-grid array package (PGA). the C4/CBGA package offers several technological improvements for high-performance RISC microprocessors, which are: (1) a much smaller use of printed-circuit board area, for example, the 361 I/O 25 mm package reduces the original package footprint by approximately 75”;, (2) a surface mountable package, (3) the package-to-board assembly is possible with industry-standard surface-mount equipment, (4) the use of C4 and CBGA technology reduces the electrical parasitics, (5) thejunction-to-cap thermal resistance was less than l.SC/W. and (6) the CBGA solder joints are predicted to exceed 3,500 on/off cycles. of 25 ‘C to 55 C cycling, with a failure rate of 100 parts per million (ppm) per package. Case study: the design of a mixed-signal global positioning system receiver using multichip module packaging. PATRICK J. ZABINSKI et al. IEEE Transactions on Components, Packaging and Manufacturing Technology---Part B. 19 (l), 215 (1996). In a collaborative project, the Mayo Foundation and Motorola have developed a fully functional miniaturized global positioning system (GPS) receiver using laminated multichip modules (MCM-L). This paper presents the system requirements, design constraints, substrate selection criteria and description, design approach, assembly, and test of a fully
operational mixed-signal development
GPS receiver to describe design techniques used cycle.
the generic during the
Design and evaluation of an epoxy three-dimensional multichip module. JON M. STERN et al. IEEE Transactions on Components, Packaging and Manufacturing Technology-Part B, 19 (l), 188 (1996). A low-cost, three-dimensional multichip module (MCM) technology provides greatly improved system density and reduced mass over planar packaging technologies. The technology offers a high degree of testability that negates the need for known good die (KGD) procurement Testing is achieved with very low cost overheads and with no increase in the volume of the module. The technology allows complete, heterogeneous systems to be packaged and interconnected in a single, ultra-dense module. The electrical characteristics of the technology are comparable to standard chip packages. However, the parasitics due to package-to-package interconnects are eliminated. This removes the dominant cause of parasitics. dramatically improving the electrical characteristics. A programmable integrated camera and image processing system has been developed which incorporates a grayscale camera, analog-to-digital conversion, four programmable processors and memory. Utilizing the three-dimensional multichip module technology, the system, which consists of nine chips and 36 discrete components, has an overall volume of 4.77 ml. This is approximately six times more dense than an advanced PCB implementation. The system forms the first stage in the design and manufacture of a portable video communications device. For such applications, low system volume and mass are key attributes. The system demonstrates the potential of the packaging technique for the integration of complete mixed-signal systems incorporating sensors and processing. Further developments to the technology will provide increased module density, improved routing capacity. and electrical performance.
7. SEMICONDUCTOR INTEGRATED CIRCUITS, DEVICES AND MATERIALS Intersubband lifetimes in Si/SiGe quantum wells. W. HEISS et al. So/id-State Electronics, 40 (1-8). 59 (1996). In the present work we report the first measurement of intersubband lifetimes in Si/Si, _,Ge, quantum well samples. We have determined T, by a time resolved pump and probe experiment using the far infrared picosecond free electron laser source FELIX at Rijnhuizen, the Netherlands. In a sample with a well width of 50 A and a sheet density of 2.1 x 10” cm- ’ we find a lifetime of 30 ps while 20 ps is observed for adensityofl.l x 10”cm-2andawellwidthof75,& We discuss acoustic phonon, as well as optical phonon intersubbard scattering as possible limiting processes for the observed lifetimes in Si/SiGe and GaAs/AlGaAs quantum wells.
World abstracts on microelectronics and reliability using a single cascadable ASIC. With a minimum system configuration of four identical ASIC’s produced by using 1.0 p CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude. A hi-density C4/CBGA interconnect technology for a CMOS microprocessor. GARY B. KROMANN, R. DAVID GERKE and WAYNE WEI-XU HUANG. IEEE Transactions on Components, Packaging and Manufacturing Technology-Part B, 19 (1). 166 (1996). The application of a controlled-collapse chip connection (C4), ceramic-ball-grid array (CBGA) single-chip package to the Motorola 88110 RISC CMOS microprocessor is presented. Also presented are the zero-level to second-level interconnection technologies and the various design considerations: from the onchip redistribution metal to the printed-circuit board definition. In addition to an overview of the interconnect technology, we discuss the: (1) printedcircuit board design, (2) first-level and second-level assembly. (3) electrical modeling and characterization, (4) thermal management. and (5) controlled-collapse chip connection (C4) and ceramic-ball-grid array (CBGA) interconnection reliability and solder-fatigue life estimates. For this study four discipline-specific technology test vehicles were used to evaluate the assembly, electrical, thermal, and reliability aspects of this C4,‘CBGA interconnect technology. The design and use of each test vehicle is presented. In contrast to a 51 mm, wirebond pin-grid array package (PGA). the C4/CBGA package offers several technological improvements for high-performance RISC microprocessors, which are: (1) a much smaller use of printed-circuit board area, for example, the 361 I/O 25 mm package reduces the original package footprint by approximately 75”;, (2) a surface mountable package, (3) the package-to-board assembly is possible with industry-standard surface-mount equipment, (4) the use of C4 and CBGA technology reduces the electrical parasitics, (5) thejunction-to-cap thermal resistance was less than l.SC/W. and (6) the CBGA solder joints are predicted to exceed 3,500 on/off cycles. of 25 ‘C to 55 C cycling, with a failure rate of 100 parts per million (ppm) per package. Case study: the design of a mixed-signal global positioning system receiver using multichip module packaging. PATRICK J. ZABINSKI et al. IEEE Transactions on Components, Packaging and Manufacturing Technology---Part B. 19 (l), 215 (1996). In a collaborative project, the Mayo Foundation and Motorola have developed a fully functional miniaturized global positioning system (GPS) receiver using laminated multichip modules (MCM-L). This paper presents the system requirements, design constraints, substrate selection criteria and description, design approach, assembly, and test of a fully
operational mixed-signal development
GPS receiver to describe design techniques used cycle.
the generic during the
Design and evaluation of an epoxy three-dimensional multichip module. JON M. STERN et al. IEEE Transactions on Components, Packaging and Manufacturing Technology-Part B, 19 (l), 188 (1996). A low-cost, three-dimensional multichip module (MCM) technology provides greatly improved system density and reduced mass over planar packaging technologies. The technology offers a high degree of testability that negates the need for known good die (KGD) procurement Testing is achieved with very low cost overheads and with no increase in the volume of the module. The technology allows complete, heterogeneous systems to be packaged and interconnected in a single, ultra-dense module. The electrical characteristics of the technology are comparable to standard chip packages. However, the parasitics due to package-to-package interconnects are eliminated. This removes the dominant cause of parasitics. dramatically improving the electrical characteristics. A programmable integrated camera and image processing system has been developed which incorporates a grayscale camera, analog-to-digital conversion, four programmable processors and memory. Utilizing the three-dimensional multichip module technology, the system, which consists of nine chips and 36 discrete components, has an overall volume of 4.77 ml. This is approximately six times more dense than an advanced PCB implementation. The system forms the first stage in the design and manufacture of a portable video communications device. For such applications, low system volume and mass are key attributes. The system demonstrates the potential of the packaging technique for the integration of complete mixed-signal systems incorporating sensors and processing. Further developments to the technology will provide increased module density, improved routing capacity. and electrical performance.
7. SEMICONDUCTOR INTEGRATED CIRCUITS, DEVICES AND MATERIALS Intersubband lifetimes in Si/SiGe quantum wells. W. HEISS et al. So/id-State Electronics, 40 (1-8). 59 (1996). In the present work we report the first measurement of intersubband lifetimes in Si/Si, _,Ge, quantum well samples. We have determined T, by a time resolved pump and probe experiment using the far infrared picosecond free electron laser source FELIX at Rijnhuizen, the Netherlands. In a sample with a well width of 50 A and a sheet density of 2.1 x 10” cm- ’ we find a lifetime of 30 ps while 20 ps is observed for adensityofl.l x 10”cm-2andawellwidthof75,& We discuss acoustic phonon, as well as optical phonon intersubbard scattering as possible limiting processes for the observed lifetimes in Si/SiGe and GaAs/AlGaAs quantum wells.