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A high efficient dual-output rectifier for piezoelectric energy harvesting
Int. J. Electron. Commun. (AEÜ) 111 (2019) 152922
Contents lists available at ScienceDirect
International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.com/locate/aeue
Regular paper
A high efficient dual-output rectifier for piezoelectric energy harvesting Peng Wah Yuen, Gabriel Chong, Harikrishnan Ramiah ⇑ Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia
a r t i c l e
i n f o
Article history: Received 26 June 2019 Accepted 16 September 2019
Keywords: Piezoelectric Energy Harvesting (PEH) Cross-Coupled Active NMOS Rectifier DC-DC combiner Voltage Conversion Efficiency (VCE) CMOS
a b s t r a c t In this paper, a high efficient active NMOS dual-output rectifier for piezoelectric energy harvesting (PEH) in CMOS technology is proposed. The rectifier adopts a cross-coupled active NMOS topology producing two output DC voltages. A DC-DC combiner at the rectifier’s output is employed to sum the output DC voltages which improves the effective Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE). Simulated on a standard 65-nm CMOS technology, the proposed rectifier achieves a VCE > 98% across a connected output load of Rrec > 9 kO and a peak PCE of 84% for Rrec = 12 kO. Compared to conventional piezoelectric rectifiers, the PCE of the proposed rectifier is significantly improved with comparative VCE performance. Ó 2019 Elsevier GmbH. All rights reserved.
1. Introduction The high demand for low-power wireless sensor nodes (WSNs) in the upcoming internet of things (IoT) are imperative in today’s modern world. Having a reliable power source is important to sustain the operation of the WSNs. With the presence of ambient energy sources, energy harvesting has become a conceivable solution for powering these low-power portable electronics. Various circuits in CMOS technology has been explored for harvesting ambient energy sources for powering these devices [1,2]. Piezoelectric energy harvesting (PEH) is a prominent solution because PEH systems are highly scalable in its output power, able to provide high output power density and capable of generating high output direct current (DC) voltage [3]. A piezoelectric (PE) transducer generates an alternative current (AC) from the harvesting of ambient mechanical energy. High peak voltage conversion efficiency (VCE) and power conversion efficiency (PCE) of the rectifier (AC-DC converter) is desirable for efficient rectification to power up a WSN. However, current PE rectifiers are limited by the device’s on-resistance which degrades the VCE [5]. The Full Bridge Rectifier (FBR) is commonly implemented for PEH which employs a bridge arrangement of 4 discrete diodes [6]. Yet, the bulky off-chip diodes make the FBR not suitable for System-on-Chip (SoC) solution. CMOS-based Full Bridge (CFB) rectifier has been realized in [7] which provides an alternative solution to the off-chip FBR. Though the physical form factor of
⇑ Corresponding author. E-mail addresses: [email protected] (G. Chong), [email protected]. my (H. Ramiah). https://doi.org/10.1016/j.aeue.2019.152922 1434-8411/Ó 2019 Elsevier GmbH. All rights reserved.
the rectifier is significantly reduced, the high reflux current introduced in a CFB rectifier significantly degrades the PCE performance. To overcome this issue, the work in [4] implements a CFB rectifier with an active PMOS diode to reduce the reflux current. However, the range of the input voltage amplitude is limited due to fluctuation in the ohmic state of the bypass active PMOS diode which degrades the VCE. A wide input voltage amplitude range of the rectifier is desirable to achieve the required performance in VCE without degrading the PCE of the rectifier. In this work, a new rectifier for PEH application is proposed. It adopts a cross-coupled active NMOS structure to achieve a wide input voltage amplitude range and reduce the reflux current of the CFB rectifier. In addition, the output of the rectifier is split to generate two DC voltages from the positive and negative input half cycles, respectively. The novelty of the proposed rectifier is in the adoption of a DC-DC combiner at the output of the rectifier which sums the two DC voltages to improve the PCE while maintaining a competitive VCE performance. Section 2 review prior works of conventional PE rectifiers and the proposed rectifier is presented. The results of the proposed rectifier along the CFB and CFB with active diode rectifiers are compared in Section 3. Section 4 conclude the findings.
2. Piezoelectric rectifier 2.1. Modeling of PE transducer A PE transducer can be modelled with the mechanical and electrical domains coupled together as shown in Fig. 1 [2,3,6,8]. The coupling of the mechanical and electrical domains is represented
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Fig. 1. Modeling of PE transducer.
by an electrical transformer, T. Cm in the mechanical domain represents the reciprocal mechanical stiffness, Rm is the mechanical damping and Lm is the effective mass of the PE transducer. In the electrical domain, the vibration excitation can be modelled by a current source in parallel with an internal capacitance (Cp) and resistance (Rp) as denoted in Fig. 1. The VCE of a rectifier can be calculated by [5],
VCE ¼
V rec V in
ð1Þ
where Vrec and VIN are the DC output voltage and input voltage amplitude, respectively. Besides that, the PCE can be calculated by [8],
PCE ¼
P rec V rec Irec ¼ Pin ðV OC V ds Þ2 C P f P
ð2Þ
Prec is the output power calculated through multiplication of the output voltage and output current. Alternatively, Pin is the extracted input power from the PE transducer where Cp is the internal capacitance of the PE transducer, fp is the frequency of the input current, Vds is the source-to-drain voltage of the rectifier and VOC is opencircuit voltage determined by,
V OC ¼
IP
xC P
¼
IP 2pC P f P
ð3Þ
2.2. Conventional full bridge rectifier The first notion in designing a rectifier for PEH is to use discrete diodes as a full bridge rectifier shown in Fig. 2 [7]. The four diodes
labelled D1, D2, D3 and D4 are arranged in ‘‘series pairs” with only two diodes conducting current during each half cycle of the input AC source from the PE transducer. Diodes D2 and D3 conducts in series during the positive half cycle when VIP > VIN. Alternatively, diodes D1 and D4 conducts in the negative half cycle when VIP < VIN. During the positive half cycle, diodes D1 and D4 are reverse-biased and vice versa. The first challenge in designing a highly efficient PE rectifier for low-voltage application is to overcome the forward voltage drop, VD across the diodes as this voltage drop attenuates the effective output voltage and consumes power. The forward voltage drop of a standard silicon PN-junction diode is 0.7 V. This amount of voltage drop is not desirable for low-voltage PEH application as the PCE and VCE performances of the rectifier drastically degrade. A CFB can provide a much lower forward voltage drop (0.35 V for low-Vth devices) which is less detrimental to the performance of the rectifier compared to the use of discrete diodes. 2.3. CMOS Full Bridge (CFB) rectifier To avoid using bulky discrete diodes with an inherent large forward voltage drop, a CFB rectifier can be adopted as shown in Fig. 3 [7]. When VIP is positive and VIN is negative, MP1 and MN2 conducts due to the negative and positive potential at their respective gates. MP2 and MN1 are forced to turn off as their gates are connected to VIN and VIP, respectively. Hence, VIN is grounded and a current path from VIP and Vrec through MP1 to the output load is established. Similarly when the potential at VIP and VIN inverts, MP2 and MN1 conducts while MP1 and MN2 turns off. Through this operation, the CFB rectifier only suffers minimal voltage drop. However, reflux current is introduced and the reflux current blocking capability of the CFB rectifier is weak when Vrec > VIP (VIN). This in effect reduces the PCE of the rectifier as it is not able to retain the charge at the output. 2.4. Active rectifier
Fig. 2. Conventional diode based full bridge rectifier.
To improve on the CFB rectifier, a cross-coupled rectifier with an active diode is introduced to reduce the reflux current [5]. This rectifier can be represented as a two stage rectifier illustrated in Fig. 4. The first stage consists of a cross-coupled rectifier and the second stage is realized with a PMOS device as a switch with a comparator modelled as an active diode. The comparator is adopted to control the on/off state of the PMOS transistor which depends on the voltage difference between the source and drain terminals of the transistor. Whenever VIN is larger than Vref (Vrec) at the input of the comparator, the comparator will turn off the PMOS device. This prevents reflux current to occur which improves
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Fig. 3. Conventional CMOS Cross-Coupled full bridge rectifier.
Fig. 4. Active rectifier.
the PCE. However, when the input voltages (VIP and VIN) are low, the forward voltage across the second stage limits the output voltage of the rectifier chain. Even though the active diode is able to improve the PCE, the VCE suffers due to the voltage drop across the active diode which is evident when the input voltage from the PE transducer is low. 2.5. Proposed rectifier To overcome the limitations of the aforementioned rectifiers, a new PE rectifier is proposed as shown in Fig. 5. The proposed topology consists of the PE transducer, an active NMOS cross-coupled PMOS rectifier, and a DC-DC combiner. An active dual-output NMOS cross-coupled rectifier is implemented as it provides a wide input voltage swing for rectification, achieves high VCE and consumes a small active chip area. In addition, a DC-DC combiner is employed by combining the two output DC voltages from the rectifier. This technique of combining the two output voltages of the
rectifier allows for higher PCE while retaining a comparable VCE performance. a. Dual Output Rectifier The proposed active dual-output NMOS cross-coupled PMOS rectifier is shown in Fig. 6. In the rectifier architecture shown in Fig. 6(a), the two NMOS transistors, MN1 and MN2 are implemented with comparator COM1 and COM2, respectively. Low Vth NMOS transistors are used to reduce the biasing complexity of the comparator. This decreases the internal body to drain (p-n junction) voltage drop of the NMOS switches by sensing the voltage difference of the drain and source terminals. Therefore, the rectifier operation will not be interrupted even if the input voltage amplitude from the PE transducer is low [10]. Both NMOS transistors will only be switched on to ensure forward conduction of the current when |Vac| > VDC1(2). In addition, the PMOS transistors, MP1 and MP2 are configured in a cross-coupled structure where the
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Fig. 5. Block schematic of proposed active NMOS dual-output rectifier.
output terminals are isolated from each other to produce two output DC voltages, VDC1 and VDC2. Unlike the conventional CFB-based rectifiers where the output terminals are summed, the dual-output configuration implemented in the proposed rectifier allow more current to flow to the output from the two half cycles of the PE transducer. MP1 and MP2 function as switches with small forward voltage drop when they are switched on. Large quantity of forward current is achieved and the active NMOS provides good blocking capability of the reflux current. MP1 and MP2 are driven as a cross-coupled connection which can adaptively turn on the transistors to retain its operation in triode region which reduces the drain-to-source voltage drop [5]. Ideally, the size of the transistors should be large to achieve zero on-resistance. However, parasitic capacitances of the MOSFET will drastically increase with a large transistor size which in turn degrades the PCE. An optimal size of the transistors is desirable as it will affect the PCE of the rectifier. Therefore, the size of the NMOS and PMOS transistors should be carefully chosen to ensure minimal PCE degradation of the rectifier. Fig. 7 shows the PCE plot against the aspect ratio (W/L) of
Fig. 6. Rectifier schematic: (a) dual-output rectifier. (b) Comparator.
Fig. 7. PCE plot versus transistor size.
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Fig. 8. Schematic of DC-DC combiner.
the PMOS and NMOS transistors for an output load of Rrec = 12 kO. The plot shows that the optimal aspect ratio for the PMOS and NMOS sizes are 16 mm/0.065 mm and 128 mm/0.065 mm, respectively. Comparators COM1 and COM2 are implemented to extend the input voltage range from the PE transducer which achieve active gate driving of the NMOS. The schematic of the comparator (COM1 and COM2) is shown in Fig. 6(b). The comparator consist of a biasing stage (MN3 and MN4), source-input stage (MN5, MN6, MP7 and MP8) and output stage (MN7, MN8, MP9 and MP10). The two diode-connected NMOS transistors, MN3 and MN4 in the biasing stage supplies a bias voltage, Vbias to the source-input and output stage. The source input stage compares VIN and Vref which are the terminals of the PMOS transistor, MP7 or MP8. The output stage (MP5, MP6, MN8 and MN9) is realized with a two stage inverter for generating a nearly digital output signal, Vg1(2) to control and drive the gate of MN1 or MN2 for reducing the reflux current. b. DC-DC Combiner The two DC output voltages generated from the rectifier are combined by implementing the DC-DC combiner illustrated in Fig. 8. It uses four PMOS transistors, MP11, MP12, MP13 and MP14 with two pulse signals, P1 and P2 to bias the gate of the transistors. The timing of the pulse are depended on the input cycle from the PE transducer where MP11 and MP13 are pulsed by P1 during the first half cycle while MP12 and MP14 are pulsed by P2 at the second half cycle. All the transistors can be represented as a switch and are biased in triode region when pulsed. The DCDC combiner operates by passing current from VDC1(2) to the output capacitor, Crec. Through the implementation of the DC-DC combiner, the PCE of the rectifier is improved and the output voltage ripple of the overall rectifier reduces. The size of the PMOS transistors are relatively sensitive with respect to the PCE, hence, the transistors are optimized to ensure optimal PCE performance is achieved.
3. Simulation results This proposed rectifier is designed and simulated on a standard 65-nm CMOS technology. The physical chip layout extraction of the PE rectifier is shown in Fig. 9. The parameters of the PE
Fig. 9. Chip layout of proposed rectifier.
transducer are given as Ip = 300 mA, Cp = 130 nF, fp = 120 Hz, and Rp = 1 MO to model the harvested vibration energy source from the PE transducer. The value of the output load resistor Rrec and capacitor Crec are 12 kO and 10 mF, respectively. Figs. 10 and 11 shows the transient response of the output current, Irec and output voltage, Vrec respectively. The results are compared with the conventional CFB and CFB with active diode rectifiers simulated with the same input parameters of the PE transducer and process technology. It can be seen from Fig. 10(a) that the leakage current phenomena is significant in the case of the CFB which is the reason for its lower VCE and PCE performance. The CFB with active diode and the proposed rectifier in Fig. 10(b) and (c) does not exhibit any reflux current that would degrade the PCE of the rectifier. A significant improvement in the output voltage, Vrec can be observed in Fig. 11 for the proposed rectifier compared to the CFB and CFB with active diode. The proposed rectifier achieves significantly higher Vrec as the integration of the DC-DC combiner allows more forward current to flow which consecutively generates a higher output voltage. The low voltage drop across the rectifier and DC-DC combiner stage also improves the VCE of the rectifier. This can be seen by the VCE comparison in Fig. 12 calculated with Eq. (1). The proposed rectifier achieves an average VCE > 98% for Rrec > 9 kO. As the leakage current phenomenon influences the PCE of the rectifier, the simulated PCE across the load is shown in Fig. 13. The highest PCE achieved is 84% for Rrec = 12 kO while delivering a Vrec of 1.21 V. This yields an output current of 101.12 mA which provides a deliverable output power of 120 mW for powering up a WSN. Table 1 tabulates the performance summary of the proposed rectifier in comparative to recently reported state-of-the-art PE rectifiers. Simulation of the proposed rectifier with respect to process corner and temperate are performed to validate the robustness of the rectifier. Fig. 14(a) shows the VCE while Fig. 14(b) shows the PCE simulation. It can be observed that the worst case VCE and PCE of the proposed rectifier are 97.4% and 77%, respectively which still achieves better performance in comparison to prior-art PE rectifiers.
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Fig. 11. Simulated output voltage, Vrec.
Fig. 12. Simulated VCE.
Fig. 10. Simulated output current for Rrec = 12 kO: (a) CFB. (b) CFB + active diode. (c) Proposed rectifier.
4. Conclusion This paper presents a high efficient dual-output piezoelectric rectifier in CMOS technology for piezoelectric energy harvesting. The limitations of conventional PE rectifiers are discussed and a new active NMOS dual-output rectifier is proposed. Simulated on standard 65-nm CMOS technology, the proposed rectifier covers an active chip area of 0.00372 mm2. The highest performances of the proposed rectifier achieved a VCE of >98% and peak PCE of 84% for an output load, Rrec = 12 kO. A Vrec of 1.21 V was achieved which delivers an Irec of 101.12 mA to provide 120 mW of output power suitable for low-power WSN devices.
Fig. 13. Simulated PCE.
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P.W. Yuen et al. / Int. J. Electron. Commun. (AEÜ) 111 (2019) 152922 Table 1 Performance Summary and Comparison of Piezoelectric Rectifiers. Author This work* [5] [7] [6] * # y
Technique Active NMOS + DC-DC Combiner CFB + active diode CFB Off-chip
Tech. (nm) 65 130 180 Discrete
Input Freq. (Hz) 120 200 200 225
VCE (%) #
98 98 85 76.9
Peak PCE (%) 84y 46 57 58
Simulation. Rrec > 12 kO. Rrec = 12 kO.
Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper Acknowledgement Funding: This work was supported by the International Grant [IF-009-2019]; and Partnership Grant [RK004-2019]. References [1] Elham K, Alireza H. An ultra-low power, low voltage DC-DC converter circuit for energy harvesting applications. AEU-Int J Electron Commun 2019;98:8–18. [2] Marzieh BA, Mohammad HZ. RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications. AEU-Int J Electron Commun 2014;68:1180–4. [3] Ramadass YK, Chandrakasan AP. An efficient piezoelectric energy harvesting interface circuit using a bias-flip rectifier and shared inductor. IEEE J SolidState Circuits 2010;45:189–204. [4] Wu L, Do XD, Lee SG, Ha DS. A self-powered and optimal SSHI circuit integrated with an active rectifier for piezoelectric energy harvesting. IEEE Trans Circuits Syst I Regul Pap 2017;64:537–49. [5] Peters C, Handwerker J, Maurath D, Manoli YA. sub-500 mV highly efficient active rectifier for energy harvesting applications. IEEE Trans Circuits Syst I Regul Pap 2011;58:1542–50. [6] Lu S, Boussaid F. A highly efficient P-SSHI rectifier for piezoelectric energy harvesting. IEEE Trans Power Electron 2015;30:5364–9. [7] Sun Y, Hieu NH, Jeong CJ, Lee SG. An integrated high-performance active rectifier for piezoelectric vibration energy harvesting systems. IEEE Trans Power Electron 2002;27:623–7. [8] Kim J, Kim J, Sim M, Kim S, Kim C. A single-input four-output (SIFO) AC–DC rectifying system for vibration energy harvesting. IEEE Trans Power Electron 2014;29(6):2629–33. [9] Do X, Nguyen H, Han S, Ha DS, Lee S. A self-powered high-efficiency rectifier with automatic resetting of transducer capacitance in piezoelectric energy harvesting systems. IEEE Trans Very Large Scale Integr VLSI Syst 2015;23 (3):444–53.
Fig. 14. Process corners simulation of proposed rectifier for Rrec = 12 kO: (a) VCE. (b) PCE.
Contents lists available at ScienceDirect
International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.com/locate/aeue
Regular paper
A high efficient dual-output rectifier for piezoelectric energy harvesting Peng Wah Yuen, Gabriel Chong, Harikrishnan Ramiah ⇑ Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia
a r t i c l e
i n f o
Article history: Received 26 June 2019 Accepted 16 September 2019
Keywords: Piezoelectric Energy Harvesting (PEH) Cross-Coupled Active NMOS Rectifier DC-DC combiner Voltage Conversion Efficiency (VCE) CMOS
a b s t r a c t In this paper, a high efficient active NMOS dual-output rectifier for piezoelectric energy harvesting (PEH) in CMOS technology is proposed. The rectifier adopts a cross-coupled active NMOS topology producing two output DC voltages. A DC-DC combiner at the rectifier’s output is employed to sum the output DC voltages which improves the effective Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE). Simulated on a standard 65-nm CMOS technology, the proposed rectifier achieves a VCE > 98% across a connected output load of Rrec > 9 kO and a peak PCE of 84% for Rrec = 12 kO. Compared to conventional piezoelectric rectifiers, the PCE of the proposed rectifier is significantly improved with comparative VCE performance. Ó 2019 Elsevier GmbH. All rights reserved.
1. Introduction The high demand for low-power wireless sensor nodes (WSNs) in the upcoming internet of things (IoT) are imperative in today’s modern world. Having a reliable power source is important to sustain the operation of the WSNs. With the presence of ambient energy sources, energy harvesting has become a conceivable solution for powering these low-power portable electronics. Various circuits in CMOS technology has been explored for harvesting ambient energy sources for powering these devices [1,2]. Piezoelectric energy harvesting (PEH) is a prominent solution because PEH systems are highly scalable in its output power, able to provide high output power density and capable of generating high output direct current (DC) voltage [3]. A piezoelectric (PE) transducer generates an alternative current (AC) from the harvesting of ambient mechanical energy. High peak voltage conversion efficiency (VCE) and power conversion efficiency (PCE) of the rectifier (AC-DC converter) is desirable for efficient rectification to power up a WSN. However, current PE rectifiers are limited by the device’s on-resistance which degrades the VCE [5]. The Full Bridge Rectifier (FBR) is commonly implemented for PEH which employs a bridge arrangement of 4 discrete diodes [6]. Yet, the bulky off-chip diodes make the FBR not suitable for System-on-Chip (SoC) solution. CMOS-based Full Bridge (CFB) rectifier has been realized in [7] which provides an alternative solution to the off-chip FBR. Though the physical form factor of
⇑ Corresponding author. E-mail addresses: [email protected] (G. Chong), [email protected]. my (H. Ramiah). https://doi.org/10.1016/j.aeue.2019.152922 1434-8411/Ó 2019 Elsevier GmbH. All rights reserved.
the rectifier is significantly reduced, the high reflux current introduced in a CFB rectifier significantly degrades the PCE performance. To overcome this issue, the work in [4] implements a CFB rectifier with an active PMOS diode to reduce the reflux current. However, the range of the input voltage amplitude is limited due to fluctuation in the ohmic state of the bypass active PMOS diode which degrades the VCE. A wide input voltage amplitude range of the rectifier is desirable to achieve the required performance in VCE without degrading the PCE of the rectifier. In this work, a new rectifier for PEH application is proposed. It adopts a cross-coupled active NMOS structure to achieve a wide input voltage amplitude range and reduce the reflux current of the CFB rectifier. In addition, the output of the rectifier is split to generate two DC voltages from the positive and negative input half cycles, respectively. The novelty of the proposed rectifier is in the adoption of a DC-DC combiner at the output of the rectifier which sums the two DC voltages to improve the PCE while maintaining a competitive VCE performance. Section 2 review prior works of conventional PE rectifiers and the proposed rectifier is presented. The results of the proposed rectifier along the CFB and CFB with active diode rectifiers are compared in Section 3. Section 4 conclude the findings.
2. Piezoelectric rectifier 2.1. Modeling of PE transducer A PE transducer can be modelled with the mechanical and electrical domains coupled together as shown in Fig. 1 [2,3,6,8]. The coupling of the mechanical and electrical domains is represented
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Fig. 1. Modeling of PE transducer.
by an electrical transformer, T. Cm in the mechanical domain represents the reciprocal mechanical stiffness, Rm is the mechanical damping and Lm is the effective mass of the PE transducer. In the electrical domain, the vibration excitation can be modelled by a current source in parallel with an internal capacitance (Cp) and resistance (Rp) as denoted in Fig. 1. The VCE of a rectifier can be calculated by [5],
VCE ¼
V rec V in
ð1Þ
where Vrec and VIN are the DC output voltage and input voltage amplitude, respectively. Besides that, the PCE can be calculated by [8],
PCE ¼
P rec V rec Irec ¼ Pin ðV OC V ds Þ2 C P f P
ð2Þ
Prec is the output power calculated through multiplication of the output voltage and output current. Alternatively, Pin is the extracted input power from the PE transducer where Cp is the internal capacitance of the PE transducer, fp is the frequency of the input current, Vds is the source-to-drain voltage of the rectifier and VOC is opencircuit voltage determined by,
V OC ¼
IP
xC P
¼
IP 2pC P f P
ð3Þ
2.2. Conventional full bridge rectifier The first notion in designing a rectifier for PEH is to use discrete diodes as a full bridge rectifier shown in Fig. 2 [7]. The four diodes
labelled D1, D2, D3 and D4 are arranged in ‘‘series pairs” with only two diodes conducting current during each half cycle of the input AC source from the PE transducer. Diodes D2 and D3 conducts in series during the positive half cycle when VIP > VIN. Alternatively, diodes D1 and D4 conducts in the negative half cycle when VIP < VIN. During the positive half cycle, diodes D1 and D4 are reverse-biased and vice versa. The first challenge in designing a highly efficient PE rectifier for low-voltage application is to overcome the forward voltage drop, VD across the diodes as this voltage drop attenuates the effective output voltage and consumes power. The forward voltage drop of a standard silicon PN-junction diode is 0.7 V. This amount of voltage drop is not desirable for low-voltage PEH application as the PCE and VCE performances of the rectifier drastically degrade. A CFB can provide a much lower forward voltage drop (0.35 V for low-Vth devices) which is less detrimental to the performance of the rectifier compared to the use of discrete diodes. 2.3. CMOS Full Bridge (CFB) rectifier To avoid using bulky discrete diodes with an inherent large forward voltage drop, a CFB rectifier can be adopted as shown in Fig. 3 [7]. When VIP is positive and VIN is negative, MP1 and MN2 conducts due to the negative and positive potential at their respective gates. MP2 and MN1 are forced to turn off as their gates are connected to VIN and VIP, respectively. Hence, VIN is grounded and a current path from VIP and Vrec through MP1 to the output load is established. Similarly when the potential at VIP and VIN inverts, MP2 and MN1 conducts while MP1 and MN2 turns off. Through this operation, the CFB rectifier only suffers minimal voltage drop. However, reflux current is introduced and the reflux current blocking capability of the CFB rectifier is weak when Vrec > VIP (VIN). This in effect reduces the PCE of the rectifier as it is not able to retain the charge at the output. 2.4. Active rectifier
Fig. 2. Conventional diode based full bridge rectifier.
To improve on the CFB rectifier, a cross-coupled rectifier with an active diode is introduced to reduce the reflux current [5]. This rectifier can be represented as a two stage rectifier illustrated in Fig. 4. The first stage consists of a cross-coupled rectifier and the second stage is realized with a PMOS device as a switch with a comparator modelled as an active diode. The comparator is adopted to control the on/off state of the PMOS transistor which depends on the voltage difference between the source and drain terminals of the transistor. Whenever VIN is larger than Vref (Vrec) at the input of the comparator, the comparator will turn off the PMOS device. This prevents reflux current to occur which improves
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Fig. 3. Conventional CMOS Cross-Coupled full bridge rectifier.
Fig. 4. Active rectifier.
the PCE. However, when the input voltages (VIP and VIN) are low, the forward voltage across the second stage limits the output voltage of the rectifier chain. Even though the active diode is able to improve the PCE, the VCE suffers due to the voltage drop across the active diode which is evident when the input voltage from the PE transducer is low. 2.5. Proposed rectifier To overcome the limitations of the aforementioned rectifiers, a new PE rectifier is proposed as shown in Fig. 5. The proposed topology consists of the PE transducer, an active NMOS cross-coupled PMOS rectifier, and a DC-DC combiner. An active dual-output NMOS cross-coupled rectifier is implemented as it provides a wide input voltage swing for rectification, achieves high VCE and consumes a small active chip area. In addition, a DC-DC combiner is employed by combining the two output DC voltages from the rectifier. This technique of combining the two output voltages of the
rectifier allows for higher PCE while retaining a comparable VCE performance. a. Dual Output Rectifier The proposed active dual-output NMOS cross-coupled PMOS rectifier is shown in Fig. 6. In the rectifier architecture shown in Fig. 6(a), the two NMOS transistors, MN1 and MN2 are implemented with comparator COM1 and COM2, respectively. Low Vth NMOS transistors are used to reduce the biasing complexity of the comparator. This decreases the internal body to drain (p-n junction) voltage drop of the NMOS switches by sensing the voltage difference of the drain and source terminals. Therefore, the rectifier operation will not be interrupted even if the input voltage amplitude from the PE transducer is low [10]. Both NMOS transistors will only be switched on to ensure forward conduction of the current when |Vac| > VDC1(2). In addition, the PMOS transistors, MP1 and MP2 are configured in a cross-coupled structure where the
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Fig. 5. Block schematic of proposed active NMOS dual-output rectifier.
output terminals are isolated from each other to produce two output DC voltages, VDC1 and VDC2. Unlike the conventional CFB-based rectifiers where the output terminals are summed, the dual-output configuration implemented in the proposed rectifier allow more current to flow to the output from the two half cycles of the PE transducer. MP1 and MP2 function as switches with small forward voltage drop when they are switched on. Large quantity of forward current is achieved and the active NMOS provides good blocking capability of the reflux current. MP1 and MP2 are driven as a cross-coupled connection which can adaptively turn on the transistors to retain its operation in triode region which reduces the drain-to-source voltage drop [5]. Ideally, the size of the transistors should be large to achieve zero on-resistance. However, parasitic capacitances of the MOSFET will drastically increase with a large transistor size which in turn degrades the PCE. An optimal size of the transistors is desirable as it will affect the PCE of the rectifier. Therefore, the size of the NMOS and PMOS transistors should be carefully chosen to ensure minimal PCE degradation of the rectifier. Fig. 7 shows the PCE plot against the aspect ratio (W/L) of
Fig. 6. Rectifier schematic: (a) dual-output rectifier. (b) Comparator.
Fig. 7. PCE plot versus transistor size.
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Fig. 8. Schematic of DC-DC combiner.
the PMOS and NMOS transistors for an output load of Rrec = 12 kO. The plot shows that the optimal aspect ratio for the PMOS and NMOS sizes are 16 mm/0.065 mm and 128 mm/0.065 mm, respectively. Comparators COM1 and COM2 are implemented to extend the input voltage range from the PE transducer which achieve active gate driving of the NMOS. The schematic of the comparator (COM1 and COM2) is shown in Fig. 6(b). The comparator consist of a biasing stage (MN3 and MN4), source-input stage (MN5, MN6, MP7 and MP8) and output stage (MN7, MN8, MP9 and MP10). The two diode-connected NMOS transistors, MN3 and MN4 in the biasing stage supplies a bias voltage, Vbias to the source-input and output stage. The source input stage compares VIN and Vref which are the terminals of the PMOS transistor, MP7 or MP8. The output stage (MP5, MP6, MN8 and MN9) is realized with a two stage inverter for generating a nearly digital output signal, Vg1(2) to control and drive the gate of MN1 or MN2 for reducing the reflux current. b. DC-DC Combiner The two DC output voltages generated from the rectifier are combined by implementing the DC-DC combiner illustrated in Fig. 8. It uses four PMOS transistors, MP11, MP12, MP13 and MP14 with two pulse signals, P1 and P2 to bias the gate of the transistors. The timing of the pulse are depended on the input cycle from the PE transducer where MP11 and MP13 are pulsed by P1 during the first half cycle while MP12 and MP14 are pulsed by P2 at the second half cycle. All the transistors can be represented as a switch and are biased in triode region when pulsed. The DCDC combiner operates by passing current from VDC1(2) to the output capacitor, Crec. Through the implementation of the DC-DC combiner, the PCE of the rectifier is improved and the output voltage ripple of the overall rectifier reduces. The size of the PMOS transistors are relatively sensitive with respect to the PCE, hence, the transistors are optimized to ensure optimal PCE performance is achieved.
3. Simulation results This proposed rectifier is designed and simulated on a standard 65-nm CMOS technology. The physical chip layout extraction of the PE rectifier is shown in Fig. 9. The parameters of the PE
Fig. 9. Chip layout of proposed rectifier.
transducer are given as Ip = 300 mA, Cp = 130 nF, fp = 120 Hz, and Rp = 1 MO to model the harvested vibration energy source from the PE transducer. The value of the output load resistor Rrec and capacitor Crec are 12 kO and 10 mF, respectively. Figs. 10 and 11 shows the transient response of the output current, Irec and output voltage, Vrec respectively. The results are compared with the conventional CFB and CFB with active diode rectifiers simulated with the same input parameters of the PE transducer and process technology. It can be seen from Fig. 10(a) that the leakage current phenomena is significant in the case of the CFB which is the reason for its lower VCE and PCE performance. The CFB with active diode and the proposed rectifier in Fig. 10(b) and (c) does not exhibit any reflux current that would degrade the PCE of the rectifier. A significant improvement in the output voltage, Vrec can be observed in Fig. 11 for the proposed rectifier compared to the CFB and CFB with active diode. The proposed rectifier achieves significantly higher Vrec as the integration of the DC-DC combiner allows more forward current to flow which consecutively generates a higher output voltage. The low voltage drop across the rectifier and DC-DC combiner stage also improves the VCE of the rectifier. This can be seen by the VCE comparison in Fig. 12 calculated with Eq. (1). The proposed rectifier achieves an average VCE > 98% for Rrec > 9 kO. As the leakage current phenomenon influences the PCE of the rectifier, the simulated PCE across the load is shown in Fig. 13. The highest PCE achieved is 84% for Rrec = 12 kO while delivering a Vrec of 1.21 V. This yields an output current of 101.12 mA which provides a deliverable output power of 120 mW for powering up a WSN. Table 1 tabulates the performance summary of the proposed rectifier in comparative to recently reported state-of-the-art PE rectifiers. Simulation of the proposed rectifier with respect to process corner and temperate are performed to validate the robustness of the rectifier. Fig. 14(a) shows the VCE while Fig. 14(b) shows the PCE simulation. It can be observed that the worst case VCE and PCE of the proposed rectifier are 97.4% and 77%, respectively which still achieves better performance in comparison to prior-art PE rectifiers.
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P.W. Yuen et al. / Int. J. Electron. Commun. (AEÜ) 111 (2019) 152922
Fig. 11. Simulated output voltage, Vrec.
Fig. 12. Simulated VCE.
Fig. 10. Simulated output current for Rrec = 12 kO: (a) CFB. (b) CFB + active diode. (c) Proposed rectifier.
4. Conclusion This paper presents a high efficient dual-output piezoelectric rectifier in CMOS technology for piezoelectric energy harvesting. The limitations of conventional PE rectifiers are discussed and a new active NMOS dual-output rectifier is proposed. Simulated on standard 65-nm CMOS technology, the proposed rectifier covers an active chip area of 0.00372 mm2. The highest performances of the proposed rectifier achieved a VCE of >98% and peak PCE of 84% for an output load, Rrec = 12 kO. A Vrec of 1.21 V was achieved which delivers an Irec of 101.12 mA to provide 120 mW of output power suitable for low-power WSN devices.
Fig. 13. Simulated PCE.
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P.W. Yuen et al. / Int. J. Electron. Commun. (AEÜ) 111 (2019) 152922 Table 1 Performance Summary and Comparison of Piezoelectric Rectifiers. Author This work* [5] [7] [6] * # y
Technique Active NMOS + DC-DC Combiner CFB + active diode CFB Off-chip
Tech. (nm) 65 130 180 Discrete
Input Freq. (Hz) 120 200 200 225
VCE (%) #
98 98 85 76.9
Peak PCE (%) 84y 46 57 58
Simulation. Rrec > 12 kO. Rrec = 12 kO.
Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper Acknowledgement Funding: This work was supported by the International Grant [IF-009-2019]; and Partnership Grant [RK004-2019]. References [1] Elham K, Alireza H. An ultra-low power, low voltage DC-DC converter circuit for energy harvesting applications. AEU-Int J Electron Commun 2019;98:8–18. [2] Marzieh BA, Mohammad HZ. RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications. AEU-Int J Electron Commun 2014;68:1180–4. [3] Ramadass YK, Chandrakasan AP. An efficient piezoelectric energy harvesting interface circuit using a bias-flip rectifier and shared inductor. IEEE J SolidState Circuits 2010;45:189–204. [4] Wu L, Do XD, Lee SG, Ha DS. A self-powered and optimal SSHI circuit integrated with an active rectifier for piezoelectric energy harvesting. IEEE Trans Circuits Syst I Regul Pap 2017;64:537–49. [5] Peters C, Handwerker J, Maurath D, Manoli YA. sub-500 mV highly efficient active rectifier for energy harvesting applications. IEEE Trans Circuits Syst I Regul Pap 2011;58:1542–50. [6] Lu S, Boussaid F. A highly efficient P-SSHI rectifier for piezoelectric energy harvesting. IEEE Trans Power Electron 2015;30:5364–9. [7] Sun Y, Hieu NH, Jeong CJ, Lee SG. An integrated high-performance active rectifier for piezoelectric vibration energy harvesting systems. IEEE Trans Power Electron 2002;27:623–7. [8] Kim J, Kim J, Sim M, Kim S, Kim C. A single-input four-output (SIFO) AC–DC rectifying system for vibration energy harvesting. IEEE Trans Power Electron 2014;29(6):2629–33. [9] Do X, Nguyen H, Han S, Ha DS, Lee S. A self-powered high-efficiency rectifier with automatic resetting of transducer capacitance in piezoelectric energy harvesting systems. IEEE Trans Very Large Scale Integr VLSI Syst 2015;23 (3):444–53.
Fig. 14. Process corners simulation of proposed rectifier for Rrec = 12 kO: (a) VCE. (b) PCE.