An Adaptive PID Regulator Based on Reconfigurable Logic Cell Arrays

Copyright © IFAC Low Cost Automation 1989 Milan, Italy, 1989

AN ADAPTIVE PID REGULATOR BASED ON RECONFIGURABLE LOGIC CELL ARRA YS E. Buffoli, N. Scarabottolo R. Scattolini + M. Tacchini 0

* + o

*

Department of Electronics, Faculty of Engineering, Polytechnic of Milano Piazzale Leonardo da Vinci 32, I 20133 Milano, Italy Department of Computer Science, University of Pavia Via Abbiategrasso 209, I 27100 Pavia, Italy Foster Wheeler Italia Via Vittor Pisani 25, I 20100 Milano, Italy

Abstract The paper deals with the implementation of a high performances auto-tuning PID regulator by means of the Logic Cell Arrays (LCA) devices. The auto-tuning method is based on a preliminary use of Relay control to bring the output of the closedloop system to a permanent oscillating condition. The prototype is composed by two printed circuit boards: the first one, dedicated to the auto-tuning algorithm, is based on a 280 microprocessor, while the second one, equipped with 7 LCAs, is charged with the control tasks, i.e. the PID and Relay actions. Keywords PID control; microprocessor control; instrumentation

adaptive systems;

INTRODUCTION it is necessary to move the control algori thms from the microprocessor down to wired logic. This can obviously be made with conventional gate arrays: in so doing however the fundamental advantage of flexibility is lost. To avoid this, two main alternatives can be exploited: the use of digital signal processor devices and the use of new programmable gate arrays called Logic Cell Arrays (LCAs). In our project the second solution has been considered. This is motivated by the fact that the LCAs technology, although still in its early stage, seems to be particularly promising for future developments. It looks then advisable to test its potentialities in a real-world problem and eventually to compare the obtained results with the ones relative to other approaches.

The falling price/performances ratio of digital devices is having a major impact on digital control systems. Among the advantages of dig i tal log ic for control are the flexibility, the accuracy and the high degree of fault-tolerance. In particular the use of programmable logic for control algorithms allows high flexibility, while wired logic implementations permit high performances. However the main drawback of programmable logic is its intrinsic slowness, due to the sequential execution of control programs. On the other hand, wired logic is very fast but rigid, due to the impossibility of dynamically changing its structure. Then wired logic implementation is to be preferred in all cases where high performances in terms of speed are required; otherwise programmable logic i mpleme ntation is to be used when modifications of parts of the control algorith m are necessary during run-time operations.

In the present paper, the innovative aspects of LCA devices have been used to implement an auto-tuning high performances PID regulator as described in Astrom and Hagglund (1984). In particular, the outl ine of the paper is as follows. The LCA devices are briefly described in the next section. Then the main ideas underlying the considered auto-tuning method are quickly summarized in the third section, while a detailed description of the prototype is given in the fourth section. Finally the paper ends with a presentation of the results obtained by applying the PID prototype regulator to a laboratory process.

The use of a microprocessor is a typical way to obtain highly flexible control systems at low cost. Microprocessors have to accomplish several tasks in a digital control system. These tasks can be classified in four classes: user interface tasks, external communication tasks, control algorithm tasks, operating system tasks. Each one of them needs different microprocessor answer times and has different code sizes. In most cases, the control algorithms are quite simple, i.e. they need a small code size, but they require fast microprocessor answer times. Hence, to spe ed up the controller,

.".7

THE LCA DEVICES The Logic Cell Array (LCA) is a high density CMOS integrated circuit. Its architecture is similar to the one of the gate array. The most significant difference from conventional gate arrays is that in Logic Cell Arrays the configurable elements of the device are defined by a configuration pattern stored in a RAM memory internal to the device itself. Thus the LCAs require no customization: each device is identical until con figured by the user. The configuration of the device can obviously be loaded at run-time and in-circuit, for example by using a microprocesso r. The resul t is a device as fast as a custom and as flexible as a microprocessor logic due to dynamic reconfigurability. The LCA user programmable array architecture is made up of three types of configurable elements: Input/Output Blocks, Logic Blocks and Interconnections. The designer can define individual Input/Output Blocks to provide an interface between the external package pins of the device and the internal logic. Each Input/Output Block includes a programmable input path and a programmable output buffer. The input path provides an edge-triggered D flipflop and the user can select either the direct input or the registered input. An array of Configurable Logic Blocks (CLBs), arranged in the center of the device, provides the functional elements usable to implement simple combinational or sequential networks. In the LCAs version we used there are 64 Configurable Logic Blocks arranged in a 8-row by 8column matrix. Each block has a 4 input combinational logic section, a storage D flip-flop, an internal routing and control section, and two outputs. The programmable Interconnection resources in the LCA provide routing paths to connect inputs and outputs of the Input/Output Blocks and the configurable Logic Blocks into desired networks. All Interconnections are composed of metal segments, with programmable switching points provided to implement the desired routing. THE AUTO-TUNING METHOD AUTOMATIC CHOICE OF THE PERIOD

AND THE SAMPLING

The auto-tuning method The classical Ziegler-Nichols tuning procedure for PID regulators is based on the identification of the amplitude and the frequency of one point of the openloop Nyquist diagram. Whenever possible, this is done by using a proportional regulator which brings the closed -loop system to the stability boundary . The drawbacks of this approach are evident: first it is not applicable to systems with phase-Iag less than IT, second undumped oscillations are not acceptable in many pratical circumstances. In order to circumvent the above obstacles, in Astrom and Hagglung (1984) some methods have been presented for the

automatic tuning of the PID in a wide class of control problems. In view of their simplicity, they appear to be particularly suited for an implementation with LCAs. The basic idea underlying the proposed tuning rules consists of observing that the majority of systems oscillates under Relay control. From the characteristics of this oscillation, namely its period and ampl i tude, and by resorting to the describing function approximation, it is then possible to get some information on one point of the open-loop Nyquist diagram. The position of this point in the complex plane can then be changed by a proper selection of the proportional, integral and derivative actions performed by the PID regulator. In so doing, it is possible to fulfill prescribed requirements on the desired amplitude or phase margins. The choice of the sampling period As is well known, a wise choice of the sampling period is crucial for the success of any digital control system, see e.g. Astrom and lVittenmark (1984). Apart from ideal cases, the selection of the sampling period is usually made on the basis of few rules of thumb which take into account 3 particular frequencies: wc

The required bandwidth of the closed loop system. The frequency of the low-pass anti-aliasing filter. The sampling frequency.

wf ws

The relations usually considered between these frequencies are summarized in Fig. 1. Idbl

20 - 100

'- - - - - -1i ,.'0

I

4-10

I

Log w

Fig. 1 Typical relations among fundamental frequencies wc, wf , ws.

the

Now note that when the auto-tuning method previously described is used, the bandwidth of the closed-loop system is known since it is equal to the frequency of the limit cycle oscillation obtained with the Relay. Therefore we allowed the user to have an automatic selection of the sampling period h according to this simple rule of thumb: wf

=

10wc

\·is

=

100wc

Which, whenever applied, uniquely defines the value of h used in the implementation of the digital PID regulator. THE PROTOTYPE The structure necessary to implement the auto-tuning algorithm discussed above

AN ADAPTIVE PID REGULATOR requires the two functional blocks shown in Fig. 2 the PlO logic block and the Relay logic one. In a ddition , a more complex logic is neede d to manage the switching beet wen Rel ay and PlO behaviors in order to a c hiev e the autotuning capability.

equipped with 7 LCAs con nec t e d to the microprocessor a s a c o mm on peripheral device.

}(a ni lude I

$ ,I

Period

V

)

( - Pl O f u nctio n \

t Rel", funCtiOn) (

-ComtaQ,uc .lJolI ",tb t he hfH't

Il

-PlO a nd Rei .. ,

cO ll'lp"' ~ r

Fig. 2 The feedback PlO control

loop with Relay or

In our prototype, bo th th e PlO and the Relay algorithms have b ee n i mpleme nted in a LCA structure, while the auto-tuning algorithm ha s been ass igned to a simple micropro c es so r (Zilog Z80). A schematic diagra m of the s tructure of our prototype is synthetised in Fig . 3. where a very fast Primary Control action (PlO, Relay) is performed on the basis of a simple algorithm while a Secondary Control action (auto-tuning method) is implemented by a much slower and much more complex algorithm. Pr im a ry contro l

Conlrolled varia ble

Second ary co n tr o l

Secondary controll er

Fig. 3 The Prima r y a nd Seconda ry control loops The Secondary Control i s required to decide whether to cha n ge s ome of the parameters of the Primary Co ntrol or to change the whole primary algorithm (PlO versus Relay) by repr og ra mm ing the LCAs with a different configuration pattern. The resulting structure is shown in Fig. 4.

The prototype consists o f t wo printed circuit boards: the fir s t one, dedicated to the auto-tuning a lgorith m, contains the Z80 microproces s or connected to a personal computer (hos t compute r) through a RS232-C serial int e rf a ce . The second board, charged with c ontrol tasks, is

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pn .amet er ,,:l UP !

- LeA prOCflmrnioc - CompuUn, of peri od an d t. mphh,d, oKI II. lIon

1

J

Fig. 4 Structure of th e p rototype The 7 LCAs are configu r e d in parallel by the microprocessor in o rder to operate as a PlO regulator or a s a Re la y . The two LCAs configuration p a tt e rn s ha v e been stored into the EPROM memo r y of the Z80 . In this way the 7 LCAs c a n operate as a programmable hardwa re s tructure . The auto-tuning algorithm is implemented partly in the mi c ropr ocesso r logic and partly in the host comp ut e r logic. This last one is al s o d e di ca t ed to monitor and graphically displ ay t he va lues of the control and the controll ed va riables. The PlO and th e Rel a y a lg o r i thms Both the PlO and th e Rela y algorithms have been i mple me nt ed in the LCAs according to a fl oH ch a rt structure diagram. The PlO b lock di ag r a m is shown in Fig. 5. Bo th th e AOC an d the OAC Converters h ave 1 2 b it s of r e solution . Internal nu mb e r re p rese nt a t io n is in two's complement wi th 16 bits of resolution. Oue to s p ace cons tra ints, the adopted arith me tic i s se ri a l, fi x ed point.

~I-~ dJl~El~____________L-_____~

Fig. 5 The PlO b lock d i agram An incremental f orm of the di sc r e te PlO regulator has been i mplemen t e d according to the folloHing rul es : u(h(k+1»

u(hk)+ K(I ( h (k+ 1 ) )+ O(h(k+1») +

where

c5 (h(k+l»

(1.1)

')11

E. Huffoli. 'J. SClr;iI)llttolo. R. SClttolini. \1. 'LIL"L'hini

(Td/h)*(2F(h(k))-F(h(k+1)) +

D(h(k+1) )

- F(h(k-l))) (l+h/Ti)

I(h(k+1)) F(h(k))

=

(1. 2) e(h(k+l))

e(h(k) ) (1. 3)

0.5 (F(h(k-l) + y(h(k))

(1.4)

In eqns. (1) h is the sampling period, k is the discrete-time index, u and e represent the sampled control and error variables respectively. The variable y is the controlled signal passed through an analog second order lovl-pass filter and subsequently sampled. The analog filter is inserted into the feedback loop to reduce the effects of the aliasing phenomenon as well as the ones of measurement noises. A further digital filter can also be used according to eqn. (1.4) to remove the influence of high frequency disturbances on the derivative action. This digital filter can either be used or not according to the operator's commands. Finally the signal {, is a disturbance which can be inserted by the user to test the performances of the control system. Particular attention has also been given to the implementation aspects so as to avoid some problems frequently encountered in practice, such as integral windup or manual-auto bumpless transfer. The PID structure is composed by three main logic elements: control units (Central Control unit, Filter Control Unit and PID Control Unit), arithmethic blocks (multipliers, adders and subtractors), registers (16 bits wide), as shown in Fig. 6.

'--,........J . ~ F(tk)

~

~.

-

I(tk)

O(tk)

Filter Block (composed of an adder and two shift registers) that computes the new value of F(h(k)). (see eqn. (1.4)). When the new value of F(h(k)) is ready (after 17 clock pulses), the Filter Control unit communi cates the end of its operations to the Central Control Unit. The second phase is the execution of the operations of both the Integral and the Derivative blocks (see again Fig. 6). The Integral block is composed by a multiplier, 2 adders and 3 16-bit registers; the Derivative block is composed of a mul t ipl ier, 1 adder, 2 subtractors and 3 16-bit registers. After receiving the signal from the Filter Control Unit, the Central Control unit starts the operations of the prD Control unit for the first time. The PID Control unit generates the timing signals both to the Integral and to the Derivative blocks, in order to obtain the new values of r (h (k)) and of D (h (k) ) respectively (see eqns. (1.2) and (1.3)). When the Integral and the Derivative blocks end their operations, the Central Control Unit activat es the prD Control unit for the second time. The third step of the algorithm starts when the PID Control unit generates the timing signals to the Proportional Block which computes the new value of u(h(k) according to eqn. (1.1). At the end, the Central Control Unit stops its operations and awaits the starting signal of a new computation step of the algorithm. Each arithmetic block has a network controlling the overflow errors. Therefore, if a positive overflow error occurs during an operation, the result is set to the maximum positive value (7FFFH), whereas if the overflow error is negative the result is set to the the maximum negative value (8000H). The overall procedure may take from 84 up to 140 clock pulses depending on the number of overflow errors arising during computation. since all the operations of the algorithm are synchronized with the system-clock running at 4MHz, the time needed to complete the whole algorithm is from 21 microseconds up to 35 microseconds. In an implementation of the same algorithm with the second generation of the LCAs devices, the resulting speed may be increased by more than one order of magnitude. The

Fig. 6 The PID configuration pattern The execution of the \'Ihole algorithm takes place in 3 different phases. In the first one, when th e Central Control Unit (composed of a 4-states synchronous sequential network) receives the command to start a new step of the algorithm, the operations of the Filter Control unit (composed mainly of a 5-bit syncronous binary counter) start. The Filter Control Unit generates the timing signals for the

addition

and

the

multiplication

As already discussed, relations (1) have been implemented by means of wired logic. In particular we used the serial fixed point - two's complement arithmetic with 16-bit words. Each word has been divided into 8 bits of integer part and 8 bits of fractional part: therefore our range is from 80,00H (-128) up to 7F,FFH (+127,996). Both addition and multiplication operators are protected against overflow (underflow) errors by forcing maximum (minimum) values in the case of these errors.

AN ADAPTIVE PlO REGULATOR

One of the advantages \-le got using this technique is th a t we auto~atica lly solved the problem of the int eg r a l or reset windup, since the setting of the value of the Integr a l action to a maximum positive or neg a ti ve value corresponds to automatically i~pl e~ent an antireset windup. The integral term A problem connected \-I i th the use of the fixed point t wo ' s comple~ent arithmetic is that even when th e complete PlO algorithm is used, the controlled variable never rea ches exac tly the desired set p o int value : the process variable always r emains under the set point causing a positive erro r eve n when the system has reached it s s t eady state.

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the first conta ins the comma nds to be sent by the microprocessor to the host computer, the second co nta ins the commands sent by the host computer to the microprocessor, the th i r d contains the values of both th e con trol and the controlled variables t o be displayed by the host computer . The ~ain tasks of the microprocessor are th e ma nagement of these 3 circular buffer s , the computation of the amplitude and the per iod of the oscillation forc ed by th e Relay, the programming phase of the LCAs structure with the PlO configur ation pattern or with the Relay one.

7

LCA XC2064

The value of this error increases with the ratio (Ti / h) . This i s due both to the round off in th e Integral term and to the two's complement representa tion. As an example, let us consider the integral t erm (1.3): h

e(h(k+1) )+e(h(k+ 1))-e(kh)

I(h(k+1))= Ti

As usually Ti >h, if both th e ratio h / Ti and the error e (h (k+ 1) ) are small, the mult iplication result of th e (h/Ti)*e(h(k+1) may be zero. Let us consider now t wo examples : -1) e(h(k+1)) = OOOFH h/Ti = 0010H Then (h/ Ti )*e(h(k+1))=00 0000FOH that, after th e cutting off , becomes: OOOOH -2)

e(h(k+1)) - OOOFH FFF1H h/ Ti = 0010H Then (h/ Ti)* e(h(k+1)) FFFFFF10H that, after th e cutti ng off , becomes: FFFFH th a t is different from zero (= -1 /256) . Therefore, we can say that the implemented PlO algorithm has an high sensitivity to negative errors , while it is much less sensiti ve to pos itive ones. The printed boards The hardwa re of the printed boards is shown schematic a ll y in Fig. 7. The SIO device manages t he serial async hronous communication beetwen th e boa rds and the host computer . The first CTC device has to be programmed t o provide the SIO the right communicati on clock (the baud rate can be from 120 0 up to 9600) . The second CTC dev ice i s used t o supply to the LCAs structure a periodi c signal , whose period is equal to th e desired s a mpling period. The rising edge of this signal allows the PlO (or Rela y) Central Contro l u nit to run a ne w comput ation step of the algorithm. The 32 KB of EPRor·~ ::-.e ::-.c ry con tain the mic roprocessor progra~ (abou t 4KB) and the configurati on patt e rn s of bo th the PlO and th e Relay a l go rithms ( ab out 24KB). The 32KB of the RN! a re ma inly d evo ted to i mplenent 3 circular b uffers:

Fig. 7 The printed b oa rd s EXPERIMENT The prototype has been used for control of a coupled-tanks proc ess . The control variable is the number of r ev olutions per minute of the volumetri c pump , while the controlled variable is the l eve l of the second tank. In th e experiment reported below, a Relay wi t hout hys t e resis has first been used to tun e a PlO regulator so as to obtain a closed-l oop sys tem with a gain margin equ a l t o 6. As shown in Fig. 8, a regime corresponding to a reference signal equal to 4 (0 and 10 corr espond to empty and full tank respectively) has first been reached by using a PlO ~ith the following parameters: Kp=1 6, Ti =J2s ;Td=Os. Then, at time t=100 0s , it has b e en i ns e rted a Relay without hysteresis and with amplitude 1 (0 means no pUP.'.p revolution and 10 means th e maximum number of revolutions). The pr esence of the Relay has forced an oscill ation \-li th amplitude 0.049 and period 58s. Correspo ndingly, the auto-tuning alg o rith m has computed the follo wing parameters : Kp=4.4, Ti=18.5s, Td=4. 6s. At ticce 1200s the so obtained PlO has been i nse rted. Finally, at time 260 0s (after 56 0 0s from the beginning of th e exp e ri~e nt), the reference signal ha s be e n chang ed from 4 to 6. With reference t o t he tr ansie nts of Fig. 8, it is worth noti ng th a t : 1)

the auto-tun ed P lO performs better than the manually tuneJ one (see in

E . Buffoli. N. Scarahottolo. R. Scattolini. i'vl. Tacchini

particular th e overshoots) ;

amplit ude

of

the

2) when changing th e \·lorking point, the performances of the con trol system deteriorate sensibly d ue to the nonlinearities of the process. However, in Vie\·l of both the simplicity of th e tuning procedure and the available hardVl a re , the tuning phase can be repeated a t any time with no effort. PIOSII'tGl.GRF

Se .. J.. 1 : 7

-V(t) -U(U -V'

10.00

8.00

' . 00

2.00

O . oo~__~~~~~~~~~~~~~~~~~~__H_.~-+O 355

704

1053

1403

1752

2101

2451

Z800

31,.,

Fig. 8 The experimental resu lt

REFERENCES Astrom, K.J. and T. Hagglund , (1984). "Automatic Tuning of Simp le Regulators with Specificati on on Phase and Amplitude Margin s ", Automa t ic a, vol. 20,

645-651.

Astrom, K.J. and B. lVittenmark, (1984). Computer-Controll ed Systems-TheorY and Design, Prentice-Hall.

ACKNOWLEDGMENTS Paper partially supported by Ministero della Pubblica Istruzione.