@iie,'IZ,zgor~:pl
A bstract: The paper presents the new etlective version of heuristic algorithm for state assignment of concurrent finite state machines. The algorithm is devoted for effective, rapid local state encoding, during an implementation of logic controller programs, specilied in Structured Text (ST) - taken !rom international standard IEC 1131-3. It is considered that textual specification in ST is closely related with an equivalent Sequential Function Chart SFC. For the sake of simplicity the slightly restricted sound SFC is treated as a standardised version of control interpreted Petri Net. The obtained state encoding is especially suited and useful for a compact representation of binary control algorithms. Copyriglll © 2006IFAC Keywords: Sequential Function Chart, Petri-Nets, FPGA, logic controllers
I. INTRODUCTION
To de scribe digital system designers need tools, which support formal analysis methods. Such tools are Petri Nets, as a good example (David and Alia 1992). Petri Net is not enough wcll accepted in industry, so it can be related with Sequential Function Chart fonnalism . The SFC is delined as a part of international standard lEC 1131-3 and its restricted " sound" form can be considered as a control interpreted Petri Net. The main aim of this paper is to demonstrate a heuristic algorithm for an effective SFC encoding, which allows reducing the length of infonnation about the internal state of digital reconfigurable controller. The simplest technique for state assignment for FPGAs is the using of one flip-flop per place - so called concurrent " one-hot" method can be used. Thi s method results in a simple combinational logic for realisation of transitions, but a long state register of size, which Icngth cquals to the numbcr of placcs. Such cxhausti vc realisation causes a great waste of cells. Today FPGAs arc vcry largc, and this limit is usually not a problem from the area point of view. The problem of necessary "Iifling" occurs, when the design becomes too big to fit into alrcady uscd FPGA.
236
An optimised design is necessary, when a new functionality had to bc addcd to thc microsystem, which has already nearly reached the maximum capacity of the FPOA . If the realisation area becomes too large, also the heat and clocking problems can be the main drawbacks of the system. Heuristic encoding allows reducing the number of flipflops and the realisation area to reasonable minimum, without any major drawbacks (Adamski 1991 ; Adamski, et al., 2005). The advantage of the compact code of Petri Net places is a reasonable sma ll representation of a state space of concurrent state machine by means of Ordered Binary Control Diagrams OBDD. OBDD may be treated as an intermediate fonn that is cspccially constructcd for a vcrification of logic controller behaviour and a rapid hardware synthesis of binary control programs (Yakovlev, et al. , 2000; Adamski , et a/. , 2(05). Hcuristic mcthod for statc cncoding, which has bccn applied previously for Petri Net (Adamski , 1987; Adamski 1991), givcs a significant reduction in flipflops . The classical approach was improved by several authors, mainly form lJniverstity of Rristol and Technical Universtity of Zielona Gora (Amroun and llolton 1990; Pardey, et of.. 1992; llilinski. et al. , 1994;
Kozlowski, et aI., 1995). Slightly different ideas where developed independently by A.Zakrevsky, II.Kubatova and others - see chapters in (Adamski, e/ al. , 2005).
fires the steps preceding the transition are deactivated and her succeeding steps are activated. An SFC can contain alternative or parallel paths. shown in Fig.!.
Since SFC can be easily converted to Petri Net, those methods can be also used for effective encoding of SFC steps. There are several different semantic interpretations of SFC but only Petri Net view into SFC is straight oriented into FPGA or CPLD implementations and enough rigorous from formal point of view. Improved and simplified classical encoding methodology of coneurrcnt statc assignment, supportcd by a modern software technology (.NET) is a reasonable compromise between concurrent one-hot encoding and time and computer memory consuming optimal concurrent state assignments.
f81 T
i
Fig. I. SFC example or alternative and parallel path. Fig. 2 shows as an example action blocks, action qualifiers and actions.
2. SEQUENTIAL FUNCTION CHART Sequential Function Chart (SFC) is a special high-level language to describe control sequences in graphical schedules. SFC also before known as Grafcet was proposed in France in 1977 as a formal specification method for logical controller programs. SFC is well accepted by industry as standard, TEC I 131-3 and used in many applications for control process dcscription. SFC can be viewed as an industrial specialization of Petri Nets. Thus, the existing formal methods lor analysing Petri Nets may be applied (David and Alia , 1992). The mathematical model of Sequential Function Chart has been derived from well-known theory o[Petri-nets. A Sequential Function Chart is a directed graph defined as quadruple (ITalang, 1989): (S.T,L,I) whcre: S=(s" .. ,s",) a finite, non-empty set of steps, T=(t, .. t.) a finite. non-empty set of transitions, L=(I, . .I.) a finite , non-empty set of links between a step and a transitions or a transition and a step, I c S set of initial steps, usually only one initial step The sets Sand T represent the nodes of the graph . The initial steps are set at the beginning of the process and determine the initial state. Steps can be active or inactive. An active step is marked with one token, placed in step. Active steps define state of the system. It is possible to associate actions with steps. Actions will be executed when the step, to which the action is assoeiatcd, becomes active. The action is associated with one or more action blocks. The action block uses an action qualifier to control the action (David and Alia, 1992).
Directed links and transitions are used to connect steps. Each transition is controlled be Doolean expression. When all stcps preceding arc active and condition becomcs true thc transition is fircablc. A tircablc transition will be fired immediately. When a transition
237
Fig. 2. SFC example of action blocks. action qualifiers and actions.
3. HEURISTIC METHOD FOR STATE ENCODING Heuristic method was originally proposed in (Adamski 19R7). The method was developed and use with Petri Nets hardware implcmcntation (Yakovlev 2000; Adamski ell/I. , 2005). Since Sequential Function Chart can be easily converted into Petri Net, most of applications and algorithms used by Petri Nets cncoding methodology can be applied directly or indirectly for SFC. The intemal representation of data structures for control interpreted Petri Net and SFC skeletons arc the same. The automatic translation Irom src graphical or textual to the internal Petri Net representation can be performed by software.
3.1 111trodllctiolllo algorilhm Places (local internal states) encoding is an important problem in the structured reali7.ation of a Petri Net. The most important features of the structural method of the safc interpreted Petri Net arc as lollows: 1. Direct interpretation of each transition in the form of a scparatc fragmcnt of a combinational part of a sequential circuit. 2. Direct interpretation of each place reflected as the state of a limited part of the sequential circuit memory register with nearly minimal length. 3. Direct interpretation of global state of the net as a Doolean vector stored in memory register. The lact that the Petri Net structure is fully rcHected in its matrix based realization, the analysis, synthesis,
testing and all necessary modifications of a circuit are relatively simple. The encoding is performed according to the following rules : of simultaneously marked places I. Codes (independent places, concurrent places) are non orthogonal. 2. Codes of non - simultaneously marked places (dependent places, non - concurrent places) are orthogonal. 3. Total length orthe code is nearly mini mal. Usually the codes of particular places are represented by cncoding conjunctions. The result of logical multiplication of compatible conjunctions for concurrent places is different from logical "false". Nonconcurrent places are represented by conjunctions, for which thc logical multiplication givcs thc valuc "falsc". Heuristic algorithm of the structured encoding consists of two main parts. First part it is an aggregation of the net. As a result, macronet is obtained and its encoding is applied after that. In the second part of procedure, internal places from macroplaces are encoded. taking into account the relation of concurrcncy among them.
3.2 Global encoding
As an example thc SFC takcn from paper (Halang, 1989) has been selected . The SFC diagram is shown in Fig. 3.
Following steps describe the first part of the algorithmglobal encoding of Petri Net which represents the SFC macrostcps.
Petri-Net theory is well documented and researched. so for farther investigation the method will be demonstrated be means of PN semantic of Sequential Function Chart. The developed s~' stem reads an ST-liIc and makes necessarily conversions automatically. The system can read Structurcd Tc).1 (ST) tilc . so dcvelopcr provides only text description of SFC. An equivalent Pctri Nct structurc is shown in Fig. 4.
Step 1: Alake a macronet that represents the Petri net. The obtained macronet of Petri Net from Fig. 4 is presented in Fig 5. Macroplace Ml contains places: PI , P3, P4, PS , PG. P18, P19. P20, P21. Macroplace M2 contains places: P7. P8. P9. Macroplace M3 contains places: PlO, PIl. Macroplace M4 contains places: PI4.PlS.PI6.PI7.
~Ml
L~-
Q~~M~M4 ........ no / O P1~/
~.:: ._ T15
L.-..._ _
Fig. 5. Macronet obtained form Fig. 4.
Step 2: Determine the reachability graph of the macrollet. Reachability graph can be computed using algorithm presented in several books including (David and Alia. 1992) - Fig 6. The cost of implementation calculated as number of flip-flops is given. Implementation Cost
4
2+1+2-5
Fig. 6. Reachability graph.
Fig. 3. Typical SFC example (Halaog. 19!!9).
238
TlS
Step 3. Determille cOllcurrellcy (R) and 11011concllrrcllcy (N) matrices alld graphs for macronet. Vertices of concurrency graph represents places in macronet, and its edges show, which macroplaces are concurrent. Non-concurrency graph is a complementary to concurrency graph. Tn Fig 7 the concurrency and non-concurrency adjacency matrices of graphs are presented The order of macroplaces in matrices is: P13 , Ml. M2. M3 and M4. P13 Ml M2 M3
R=
P13 Ml M2 M3
M4
()
()
()
Pl~M101=O 2 01=1
0
01=1
M2 M3 M4
M4
Q1=1
M3
Q1=1
The reduced size adjacency matrix with removed rows and columns is shown in Fig 10.
N=
1
Ml
Fig. 9. Partial code QI and adjacent matrix alier first stcp of the algorithm
M4
li l Hi] [i i ~ ~ l] 1 0
Ql P13
()
P13 M3 M4
N=r: ~ ~]
Fig. 7. Concurrency (R) and non-concurrency (N) matrices. Entry "I " in matrices means that macroplaces (i,j) are adjacent (concurrent in R , non-concurrent in N). The graphs are shown in Fig. 8 1
During the second pass of algorithm vertex P13 with degree d(P13)=2 is removed from the matrix in Fig.9. Thc procedurc is finishcd bccausc dcgrcc of incidcncc for all vertices are equal to O.
2
R
Fig. 10. Non-concurrcncy (N) matrix after first step of the algorithm
QI
N PI3
Fig. 8. Concurrency (R) and non-concurrency (N) graphs.
MI M2
For futher investigation the matrix N will be used. Degree of incidence for a vertex is the number of connected vertices (or edges) to it. In non-concurrency matrix N (Fig. 7) the "I " represents that considered vertex is a neighbour to another (Fig. !\).
Q2 0
0
[~r[J~l
Q2':~ I,
M3
(lJ
M4
M4
Q2='
M3
Q2=1
Fig. I!. Partial code QI. Q2 and adjacent matrix after second step of the algorithm
Step 4: Macroplace encoding 4.1. Till matrix is not an empty matrix: Select a graph vertex N, which have the highest degree of incidence. Eliminate the edges connecting the selected vertex (vertices) with the vertices adjacent to it. It means that the proper row and column in matrix N is removed . (Fig. 9) 4.2 Assign code Q: ~O to the selected vertex code Q: ~ l to the rest of the remaining adjacent vertices and Q: ~- to the parallel vertices (relation R). The dash "-" designate that the variable Q neither can be used for the encoding of an appropriate macroplace. nor for the local encoding of places. which arc represented by considered maeroplacc. Before the first pass of the algorithm the degrees of incidence are as follow: d(P13)=3. d(MI )=4 , d(M2) ~2. d(M3)=2. d(M4) ~ I. Vertex Ml is selected, because its degree of incidence is 4. Vertex MI is partially encoded by QI ~O , and its all neighbours (Pl3. M2. M3. M4) get partial codes QI = 1. Hecause vertex MI has been alreadv encoded it is removed from the list of macroplaces. Codes after the first stcp of thc algorithm and graph N with encoded places is shown in Fig. 9.
239
The obtained matrix is now empty matrix (only with 0), so the algorithm goes to next step. 4.3 The correction of the algorithm. Till thcrc arc unchcckcd macroplaccs having a code containing "-" : • Compare the code of a macroplace with the eooes of all macroplaces parallel to it. • Leave the dash symbol unchanged only when the relevant variablc from a parallcl maeroplacc is equal to ,,-,. or "*". [n other case, the dash "-" should be replaced by "*" . Stop the comparison, when all the macroplaces parallel to the considered one have been checked. Designate the considered macroplace as a checked one. In the presented partiCUlar example, after correction step. the coding is not changed.
Step 5: F:flcode the places inside respective macroplllces (local encoding). Gcncral rulcs of local state assignment are the same as for classical pure sequential state encoding.
Tab'" 2 Macropl"ce MJ ~ne()dcd. after M2
3.3 Local ellcodil/g Till all the places are not encoded: Step J.' DeTermine the maximal sel of cn17~\·isleIlT vl!rlices (clique ) having Ih" highesT implemelltalio" cosl (Fig. G. Fig. ll). The formula for determination of muxim!!1 set is presented ill Equation I.
I]log,h)[ ,,,, I
( 1)
where : numb"r ofrnacropla\:es which belongs to cliqlle in R-groph , n, - number of places rcprescnted by the i-th maeroplace which belong to the clique , }/[' the nearest integer number larger or equal to a.
111
•
Implementation cost determine number of variables needed for encoding a clique and thereto,,: how many llip·11ops mllst be used lilf internal "neoding the plac"s which b~long to it. REMARKS: 1) Macroplaces having n- l (cost equals 0) cun be prdiminary excludcd from calculation . 2) Cliques in R-graph correspond to Illacroplaces. which arc assigned to the same vertcx of reachability graph. In considered example. the implementation costs of each macroplace equals to: k(P13)=O . kCMl)=4. kCM2)=2. k(M3)= 1. k(M4 )=2 The configuration with the greatest cost 5 will be M2 , M3 and M4. so the five variablcs must be add to 01 and Q2.
Ql 02 Q3 04 Q5 Q6 Q7 I'Ll
o
P7
I
1'8
o
0 1
1'9
1
0
PlO
*. •
•
0
*
*
•
M4
QI Q2 Q3 Q4 05 Q6 Q7
PI3 Ml
P7 1'8
0 0
o o
1'7
M3
*
M4
*
240
•
•
• •
()
•
•
•
1
•
*
• 0
(I
o
0
1'9
1
()
PlO
•
•
I'll PI4
•
*
* •
1'15 1'16
•
•
•
0
I
*.
*
•
]
()
1'17
••••
1
Table 4 Macroplacc Ml encod.:d. aner M2. M3 and M4 (/ocal encoding)
QI 02 Q3 04 Q5 Q(; Q7 ()
0 0
0
0
o o
0 0
o o
0
()
P20
o () o 0 o 0 o 0
P::!1
()
PIS
(J
1'5
1'19 1"'4
1'6
*
•
• *
•
()
0 I
()
0
o 1
()
()
1 (J
0
(J
o o
0
*
1")
o •
*
1'10
*
•
*
*
* 0
•
0
•
•
•
•
0
1'15
*
*
•
0
1'16
* *
•
•
* *
*
*
*
PI7
*
••
o
PS
1'14 ()
•
I'll
0
P9
0
108
Q1 Q2 QJ Q4 Q5 Q6 Q7
MI
I 0
1'7
Taille 1 Macroplacc M2 encodcd
PI)
•
Table :3 Macroplacc M4 encoded. after M2 and M3
1'3 Slep 3: Assign vllllles /0 the locall'(Jrillbles. Variahles used for .:neoding the places. belonging to the considt,red selected clique should be assigll.:d "ith: a) the value ,.•... when thc seJccted macroplacc is parallel 10 the macroplace in the clique. b) the vari a ble ". " when the selected m3croplace is not parallel to thl' macroplacl' in the clique. The local encoding for considered example is presented step by step in Tables 1·4.
0
I'll
PI3 1'1
Step 2: Lncode the plll"es imide n/(/croplllces Th.: typi"ul statc assignment lechniques arc applied.
()
Ml
()
1
Now all places in the net have been encoded. The codes for each place can be rewritten as conjunctions: PI = IQI · /Q2 ' /Q3' IQ4· IQ5 P3 ~ IQI . IQ2 . IQ3 ' /04 . Q5 P4 = IQI . IQ2' Q3 ' /04' IQ5 P5 = IQ I . IQ2 . IQ3 . 04 . IQ5 P6 = IQI . 1Q2 . Q3 . 1Q4 . Q5 P7 = Q I . Q2 . IQ3 . 104 P8 = QI . Q2 ·/Q3· 04 P9 = QI . Q2 ' Q3 · /Q4 PlO ~ QI . Q2 . IQ5 PI I = QI . Q2 . Q5 P13 = QI . IQ2 . 1'14 ~ QI . IQ6 . IQ7 PIS = QI . IQ6· Q7 PI6 = QI . Q6 . IQ7 PI7 = QI·Q6·Q7 1'18 = IQI . Q2 ' IQ3 . IQ4 . IQ5 PI9 = IQI· IQ2' IQ3' 04' Q5 P20 = IQI · /Q2· Q3' 04 · /Q5 P21 = IQI . IQ2' Q3· Q4. Q5
5. CONCLUSIONS Presented algorithm can be used for coding of Sequential Function Charts steps in hardware implementations. The experimental solution is already tested for effectiveness and some minor changes are ready to be applied. All calculation have been done automatically by the program, which is written in Cf, . The program takes a speciiication written in Structured Text and gives as an output the state assignment for SFC steps. The idea of research it is including several coding tactics in the cxpcrimental program, sclccting thc best result for considered Sequential Function Chart. As the next version, the program will also display and save SFC diagrams in graphical format. It will use two related files: onc SI file with textual description of the SFC closely linked with another XML based format for graphical representation.
Acknowledgement The re search was supported by the Polish State Committee for Scientific Research (Komitet Badan Naukowych) grant4TIIC 00624
4. TEST OF SOLUTION The first test of the solution is checking the uniqueness of thc calculatcd codes. The codes gcneratcd by algorithm are unique for each global macro state or statc. Thc second test is the satisliability of rules presented in chapter 3 .1. Codes for concurrent places must be non-orthogonal what means that the conjunction of the codes for those places must not be equal to O. Codes for non-concurrent places has to be orthogonal what means, that conj unction of the codes for that places must be equal to O. Examples of concurrent places , torming one global state ofPclri Net (SFC global statc): 1'7, 1'10, 1'14 => QI·Q2· /Q3 ·/Q4-iQ5 -1Q6· /Q7 0 P13 , PI7 => QI· /Q2 ·Q6·Q7 Examples of non-concurrent places: 1'7,1'8 => QI'Q2'/Q3' /Q4'QI 'Q2 '/Q3'Q4 0 1'14,1'17 - :>QUQ6·/Q7·QI ·Q6 ·Q7 · 0
*
The third check is for the elleetiveness of the algorithm. Minimal number of variables for the Petri Net theoretically cannot be less then MIN ]log 2 NSG[ where NSG is the number of global states of the net. The NSG is equals to the number of vertices of reachability graph . In the example: NSG - jMl[ - jM2[' jM3['jM4l + I· jM4l~ 5 , 3·2·3, 3 ~ 26 so: MlN ']log 2 NSG[ 5 Usually the number of coding variables is not equal to theoretical minimum limit. The maximal number of variables in "onc-hot" mcthod equals to 19. In other coding method, based on decomposition into three state machines it is necessary to use 9 variables. The solution is accepted , as a compromise achieved between onc-hot and absolutely minimal. but not practically useful encoding, based on transformation of Pctri Net into classical single, equivalent state machine.
241
REFERENCES Ad amski , M. (1987). Directed imr.lementation of Petri Net specifications In: Proc. 1'Inl Conf on Control Systems alld Computer Science: Vol 3, pp 86-95 AdamskL M. (1991). Parallel controller implementation using standard PLD software In: FPGAs Internatiollal Workshop Oil Field Programmable Logic and Applicatiulls; Abingdon EE&CS Books, pp. 296-304, England Adamski , M" A .Karatkevich, M.wegrzyn (cds .) (2005). Design a/embedded cOlltrol ,ystems, Springcr Amroun, A. , M.I3olton (1990) . Synthesis of controllers from Petri Net description and application of ELLA In: Formal VLSI ::'pecification alld synthesis. Design Methods I: pp. 291-308, Elscvicr, Holland Rilinski , K" M .Adamski , lM.Saul , E.L.Dagless, (1994). apetri net based algorithms tor parallel controller synthesis", In: lEE Proc. - Computers and Digital Techniques , Vo1.l41 , pp.405-412 David , R , H.AlIa (1992). Petri Nets alld Grafcet, Prentice IIall 1nl.. USA Halang, W.A . (1989) Languagcs and Tools for the Graphical and Textual System Independent Programming of Programmable Logic Controllers, A1icroprocessing and A4icroprogramming 27, pp.583 - 590 Kozlowski , T. , E.L.Dagless, lM.Saul , M.Adamski , J.Szajna (1995), "Parallel controller synthesis using Petri nets", In: lEE Proceedings - E. Computers alld Digital Techniques, VoL142, pp.263-271 Pardey, J. , T.Kozlowski , J.Saul, M.I3olton (J 992) State assignment algorithms for parallel controller synthesis In: IEEE Proc. - Computer Design; VLSI ill Computers alld Processors. pp. 316-319 Yakovlcv A ., L. Gomes, L. Lavagno (cds .) (2000) Hardware Desigll alld Petri Nets Kluwer Academic Publisher, Boston