Microprocessor survey

Microprocessor survey David Russell presents a survey of commercially available chips The past year has seen the introduction o f new microprocessor products in all appfication categories. The single-chip 8-bit devices, with their associated development chips, are aimed at inexpensive, highvolume products while the 8-bit general purpose umts have been 'rounded out' to produce faster and easier-touse microprocessor systems. In the 16-bit ranges, enhancedperformance devices have been introduced, and at the top end o f the market, bit-slice families are expanding to include specialized functions as well as many higher speed selections. This paper wdl discuss in outline the techmcal characteristics of these and other products and wdl also prowde information on broad price trends for various types of microprocessors. MARKET AREAS Some of the application areas for microprocessor systems are shown in Table 1, which is an adaptation of similar tables produced by Intel and ERA 1'2. It shows that available 8- and 16-bit microprocessors fit into most categories. Whdst it is still true that it will be some time before many 8-bit microcomputers approach the price of 4-bit single-chip microcomputers and that the performance of the F100-L/F101-L 16-bit system on shifts and multiplication/division will be hard to beat by the 8-bit units, a lot of the ground in between these extremes has been filled in. One should therefore think in terms of devices designed for specific applications, rather than in terms of word size. For example, 8-bit and 16-bit microcomputers for inexpensive applications are now available and, m the general-purpose market, the supposed performance disadvantages of 8-bit systems for some 16-bit applications can be overcome by programming techniques 3. SINGLE-CHIP

MICROCOMPUTE

RS

The 4-bit devices still represent the cheapest solution for such low-performance requirements as are found in consumer applications. Existing major PMOS families have been expanded by introducing variants in memory capacity and I/O facilities (Table 2). In addition, devices of compatible or similar architecture are becoming available in other technologies, such as NMOS, CMOS and lowpower PMOS, to cater for applications requiring improved performance or lower power. These families are not generally economically viable for small quantities, but prices for high volume are extremely low, for example theTMS 1000 in typical applications is priced at about £.2 for I00 000. The total cost of the electronics will be more than this, as there are usually other semiconductor devices involved in any application. Computer Technology Limited, Eaton Road, Hemel Hempstead, Herts, UK. This is an updated version of the paper presented at the SERT conference 'Microprocessor systemsand software' 26-29 September 1977, University of Kent at Canterbury, UK.

vol 2 no I february 78

Many 8- and 16-bit slngle-chtp m=crocomputers have been announced this year, some are ah~ady available and most of the rest should come onto the market during the coming year. It is feasible to purchase small quantities, as versions with EPROM are available. However, it is expected that these will be considerably more expenswe than versions with mask-programmed ROM (Figure 1). Most of the microcomputers in Table 3 are intended for stand-a%ne applications, but some of them have bus connections to allow efficJent communication wtth other microprocessors. This type is relerred to as a peripheral controller. In time, there will probably be enough of them to warrant a separate tabulation. The dewces currently announced have the following general charactertst~cs • • • • • •

,

Package ROM/EPROM RAM I/O Interrupts Timer facilities

28-52 pins 1 - 2 kbytes 64--128 bytes 18-32 bits 1 - 4 levels

Memory and I/O capacity can usually be increased at the expense of some of the original I/O bits.

COMBINATION SYSTEMS FOR TWO-CHIP MICROCOMPUTERS

Many manufacturers have announced families of devices that allow a microcomputer to be made out of two chips connected to a common bus (Table 4). This bus allows the system to be easily expanded, particularly m cases where it is compatible with more powerful general-purpose microprocessors. The CPU, RAM, ROM, I/O and timer functions are partitioned between the two chips; some manufacturers put the RAM with the CPU, others put Jt with the ROM, I/O and timer. EPROM-based systems can be built using devices from the Intel range, which allows various combinations of memoryand I/O. Using a general-purpose bus restricts the number of I/O bits available in some systems, but they can be expanded by adding cheap PIA-type devices. Figure 2 shows the approximate prices for two and three-chip NMOS combinations. (Table 5). The systems announced have characteristics very similar to the 8-bit microcomputers with the exception of •

Packages

• •

I/O Readily expandible memory I/O

CPU 2 8 - 4 0 pins, memory combination 40 pins 8 - 40 bits 8 - 64 kbytes 13

150

• Predicted durmg 1977

125 E

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tO0 L I ~75 F !

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1981

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1979

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Figure 1. Price trends I000+ (a) Inte18748 8-bit EPROM microcomputer, (b) Fairchild 1=8 first generation 8-bit chip set, (c) Inte18048 8-bit microcomputer, 8021 Iow
&, 12- AND 16-BIT GENERAL-PURPOSE MICROPROCESSORS e~ E

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The major trends this year have been systems of higher performance and/or lower cost. For example, a large number of types require only + 5V supply, so that in many systems, power supply costs can be reduced (Figure 3, Tables 6 and 7). Where tmproved performance is the result of speeding up an existing microprocessor, the memory access ttme generally has to be reducedpro rata. Fortunately, memory technology has advanced sufficiently that these access times can be readily achieved, although the number of sources of the very-high-speed devices is more limited

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1979

1981

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Figure 2. Price trends 1000+: bus-oriented 2-chip set

microprocessors

Table 2. 4-bit single-chip microcomputers

Device

Originator/secondsource

$2000 S2000A

AMI

COPS series 5781 5799 5782 57140

Technology

Comments Microcomputers for display/ keyboard and control systems. 1 kbyte ROM expandable externally. 64 x 4-bit RAM. Direct drive to LEDs or vacuum fluorescent displays

National semiconductor

Calculator-oriented processors of various capacittes up to 2kbytes

PMOS

Scientific calculator chip compattble with microprocessor bus

57109

PPS411 series MM75 MM76D MM76 MM76E MM76C MM76L

Rockwell

PMOS

Mtcrocomputers with various capacities up to 2 kbytes. Some with special features such as A/D converter. 2 8 - 5 2 pin package

TMS I000 series

Texas Instruments (I)

PMOS, NMOS, CMOS, low-power PMOS

Microcomputers with capacities up to 1 kbyte. Instruction set can be modified to user requirements 2 8 - 4 0 pin package

1000 1018 1100 1117 1200

Table 3.8-and 16-bit microcomputers Devtce/ Ortgina- Technologylnstruction No of Internal Address I/O Interrupt WorkingSubroutine Power Clock avatlability tor/ Time, mstruc- memory, modes facilities levels/ registersnesting* supplies/ secondps ttons bytes efficiency package source (ma×) 3859 Fairchild (samples now)

NMOS isoplanar

1.5-9.75

70

1 k ROM D,I,IMM 4x81/O counter 3(2 ,n 5 bytes/ 64kRAM IMP, t=mer +1 in RAM) level 11.6ps- (fair) 2.96ms

2 k ROM

3860

64 RAM

8048

Intel(3)

2.5-5

8748)t (now)

96(inc. l k ROM R,IMM, 3x81/O all (EPROM) IND 2 flags/ address 64 RAM timer/ modes (4 k max)

8041 (8741) (now)

2x81/O 2 flags timer/ counter

Z8 (mid 1978)

3870 (samples now) 6801

15-3.75

Mostek (2)

NMOS

ion

2-13

96

70

implanted

Motorola

(Mid 1978)

72+ 8x8

2k ROM 96RA M (64k ROM 64k RAM max.)

16 in 1+2 2 flags RAM counter (V.good)

2.67MHz F8 internal S/W

+SV +12V 40 pin 8 levels +SV 6MHz 40 pin internal

2 flags counter

2 kROM D,I, 4x81/O 1+count- 4(3 in 64 RAMIMM, ttmer/ er (fair) RAM) (4 k IMP, counter/ soon) IDX width

Standalone system Intelligent Peripheral Controller 8080 bus

4x81/O 2xtimer/ counter

2 k ROM 6800+ 30 I/O 128RAM timer/ (8 k m a x ) counter/ width

+SV 40 pin

Notes

+5V

5 bytes /level

+SV 40 pin

4MHz internal (Ref.7)

1-4 F8 MHz S/W internal 680O

bus S/W

(Ref.7)

continued overleaf vol 2 no I february 78

15

Table 3.8- and 16-bit microcomputers (continued) Device/ Origina- Technologylnstruction No of Internal Address I/O Interrupt WorkmgSubroutine Power Clock availability tor/ Time, mstruc- memory, modes facilities levels/ registersnesting* supphes/ secondhts tlons bytes efficiency package source (max) 8050

NationalNMOS Sem,conductfor

1610~ (now)

General instrument(1 )

Notes

165g{Now) General instrument 6500 Rockwell (mid 1978) 9940// Texas N M O S (samples Instrunow) ments

53 1.6-17.6 32 (x) 45(+)

58

2 k ROM 34 I/O 64 RAM 2k D,IND,R,32 blts EPROM IDX I/O 128 RAM IMM 256bits C RU, ext logic Timer/ counter

+SV 2+ 16m counter RAM

32 bytes /level

(Ref.7)

+5V 5MHz 9900 40 pm internal S/W

(excellent)

Standby facility

Address modes: R register, D direct, I indirect, IMM immediate, IDX indexed, IMP implied, INC increment while performing other op'eration, ABS absolute * Shows bytes of RAM used for context switch. For many applications, fewer bytes/level can be used f Variantsavadable. 8049 has 2 k ROM, 128 RAM, 8021 28 pin package with reduced facilities -~ Very low cost 16 bit device for games systems // Variant with 1 k ROM/EPROM J'J" Peripheral processor

Table 4. 4-bit and first-generation 8-bit chip sets for controller applications Instruction time, ~zs

package with separate data and address; 40-pin package with limited address-range bus and separate multiplexed data bus (Table 8). The basic characteristic of the general-purpose system is that they offer up to about twice the performance of the two-chip sets, as a result of the extra power of the CPU achieved by a higher clock rate or enhanced architecture.

Device

Originator /secondsource

Technology

4004 (MCS-4) 4040

Intel (2)

PMOS

10.8-21.6

Intel (1)

PMOS

10.8-21.6

PPS-4

Rockwell (2)

PMOS

5-I 0

SAB4080

SIemens

PMOS

5-10

PPS-4/2

Rockwell

PMOS

5 10

5O

F8

Fairchild(2)

NMOS

2-13

40

4o

LP8000

General I nstru ment(2)

PMOS

5-20

30

30

CDP1801 (2-chip mpu)

RCA

CMOS

5.3

16-BIT HIGH-PERFORMANCE MICROPROCESSORS The 16-bit microprocessor seems tc be the area of greatest experimentation with new technologies. The established

TMS 9980 20

2O

I0

IO I

at the moment. Many of the high-speed memories are compatible with existing umts, allowing development of prototype systems with reduced performance. For 16-bit microprocessors, the problems of pin-out limitations make ~t impossible to accommodate separate 16-bit address and data buses on a 40-pin package. Hence the various arrangements used for 16-bit microprocessors' 40-pro package with multiplexed data and address; 64-pin

16

a 1977

1979

J

1981b 1977

1979

1981

Figure 3. Price trends 1000+ for a general-purpose system (a) Texas Instruments TMS 9900 or TMS 9980, 1 hbit PROM, 256-bit RAM, 32 I/0, (b) Z80, 2PIO, 2 hbit ROM, I kbit RAM

microprocessors

Table 5. Bus oriented chip sets for inexpensive controller applications CPU + Orlginacombination/ tot/ availability secondsource PPS 8/2 system (now)

TechnoIogy

Rockwell PMOS

8035 8355 (8755) 8048 (8748)

Intel

Instruc- No of Memory, Address I/O Interrupt tion instruc-bytes modes facilities levels/ times tions (max) efficiency /~ s 5

99

2-5

2 k ROM (EPROM) 64 RAM 1 k ROM

28 I/O 2 test 2 timer/ counter 40 I/o 2 test 2 timer/ counter

320 RAM

National PMOS 10-45 46 Semiconductor(l)

SC/MP 2 MCS 6503 MCS 6530 (now)

2x8 I/O 1 serial counter/ timer

(EPROM)

8155

SC/MP, 8356

2k ROM D.I IDX 64 RAM IM IMM (32k)

MOS Technology (2)

NMOS depletion load 2--7

2k ROM R,IDX, 128 RAM (64k)

3 Flags

l k ROM D,R, 64 RAM IMP,

(4k)

-17V 42 pln 52 pin

3 (fair)

+5V

1 4

6 bytes

ABS, etc.

MCS 6503A (now) MCS 6530At

3.5795 2-phase MHz clock (TV) O/P internal PPS 8 bus S/W Two examples, others possible

+5V -7V 40 pin 40 pin

2x8 I/O 1 Timer (v. good)

IDX,

Notes

+SV

8 I/O

R,I,IDX IMM 56

Power Clock Working Subregisters routine supplies/ nesting* package

DC 1MHz TTL I/P

+ 5V 40 pin

4 MHz

+5V 28 pin 40 pin

1 MHz TTLI/P

1-3.5

6800 bus

2MHz TTLI/P

XC 6802 Moto(samples now) rola (1) 6846(mid 78)

NMOS 2 - 8 depletion load

72

2k ROM 128RAM (64k)

D,R, IMM, IDX,I, IMP

10 I/O 1 Timer/ (v.good) counter

4

7 bytes/ +5V level 40 pin 40 pin

4MHz internal

6800 bus S/W

2650+ 2656 (now)

NMOS 4.8double 9.6 ion implanted

75

2kROM 128RAM (32k)

8 I/O 1 1 serial (good) I/O

7

8

+SV 40pin 40 pin

DL 1.1MHz TTL

2650A-I

2.49.6

75

R,I, IMM IDX, IMP, Timer

Static handshake memory access

265A-I

1.8-7.2 9 levels +SV --12V 40 pin

2MHz 2 phase

16-bit

PACE

Signetics(l)

National PMOS 8 . 5 Semi18 conductor

9980 9972

Texas Instruments

45

3.3-22 20.6(x) 45.3(-)

(64k)

D,I R,IDX

1920 ROM 128 RAM

4

10 I/O

+5V -5V -12V

Ref.7 9972

* Shows bytes of RAM used for full context switch. For many applications, few bytes/level can be used. Jf Other variants available with 8k addressing, 24) clock output, 2~b clock inputs or changes to Interrupt and Ready signals.

Table 6. First and second generation 8-bit general-purpose processor systems.

Device/availability

Originator/second-source

Technology

Instruction time/a s

8008 (MCS-8) PPS-8

Intel Rockwell (2)

PMOS PMOS

20-60 4-12

AM9080A--4 8080A MC6800 CDP1802

AMD Intel (5) Motorola (3) RCA(2)

NMOS NMOS MNOS ion implanted CMOS

1-4.5 2 - 9 (I . 3 - 5 . 9 for - I ) 2-8 2.5-3.7

vo/ 2 no 1 february 78

17

Table 7. 8- and 12-bit general-purpose microprocessors using + 5 V supply (All using 40-pin package)

Device

Originator/Techno- InstrsecondIogy uction source time,

8085A

Intel (3)

NMOS

8085A-2 MCS 6502

68A00

80

Memory Address I/O Range, modes range bytes

Interrupt Working Sublevels/ registers routine efficiency nesting

64k

8 H/W (good)

D,I, IMM IDX

No limit

7

MOS TechnoIogy (2)

NMOS 2 - 7 depletion load

320

56

64k

D,R, No IMM, limit IMP, IDX, INC, ABS,etc.

1 H/W 40 st.ptr (good)

4

40*

1-3.5 Motorola (4)

(2)

NMOS 2-8 ion ~mplanted

72

64k

D,R, IMM, IDX, INC, IMP

No limit

80 (inc 8x8) 64k

CDP1802

RCA(2)

C~/1OS C°L

2650 =#

Slgnetlcs

NMOS

91

64k

575

I MHz TTL

285

2 MHz

No limit 540

1 MHz 2 phase

"

360

1.5MHz 2 phase

250

2 MHz 2 phase

1-4

6809 (late 1978) Motorola

11

No limit

2H/W

D,I, IMM

7x80/P 7x8 I/P

1H/W (good)

Inc. 16- bit registers No limit

16x16

nolim,t

2650A

2.4--9.6

620

2650A-1

1.8-7.2

465

Z80

STTL Zilog (1)

NMOS 1.6--9 ton implanted depletion load

Z80A IM1600A

0.25

8k 158

64k

8 D,I, IMM

256x8 I/O ports

8

CMOS

2.5-5.5

17

No limit 590

355 4kx12 D,I,R expandable to 32kxl 2

64x12

1 (poor)

2

bus S/W

6800 bus

10 MHz

1--5.6 Intersd (1)

8080

3--15V supply 620

8X300

Notes

6800 bus

4.8-9.6

(1)

3.125 MHz internal 5MHz mternal

1 H/W 4 no limit stack pointer (v good)

NMOS 1.3-6 depletion load

68B00

Memory Clock access, ns

No limit 575

0.8--3.6

MCS 6502Af 6800

1.3-5.8

No. of instructions

No limit

2.5MHz TTL

4MHz TTL DC 8MHz

12 bits

Assumes the author has understood the operatfon of a 650 x 8-bit stack pointer correctly. Also assumesthat full context switch for each level; Jt wtll be possible m most casesto use fewer bytes per level 6512, 6512A are versions requiring 2-phase clock input See chip set section Table 8. 16-bit MOS general-purpose processor systems Device/availability PACE Super Pace 8900 mN601 CP1600 TMS9900

18

Originator/second-source National semi-conductor NMOS Data-General General Instrument (1) Texas Instruments

Technology

Instruction t i m e / J s

No o f Instructions

PMOS

8.5-18

45

NMOS

2.8-7.7 41 (x) 59(+) 1.6-72 2.7-14 17.33(x) 41.33(+)

87

NMOS ion implant NMOS

87 69

microprocessors

Table 9. 16-bit high-performance microprocessors Device/ availability

Originator

TechnoIogy

Instruction time,//s

No of

9440 (samples)

Fairchild

13 L

1.12-3.04

180

64

8 modes

63 devices

4

F100-L Ferranti (samples)

CDI

1.19-5.19

122

64

4 modes

No limit

2

instructions

Address I/0 modes r a n g e

<0.5

> 8085 set

2.7-14 17.3341.33

69

Includes x,÷

ZS000 Zilog (mid 1978)

Table 10. MOS and 12 L Microprogrammable processor components Originator/ Bits second source

TechnoIogy

Macrologic 4700

Fairchild

CMOS

IMP 16

National

4-16

PMOS

SBP 0400

Texas I nstruments

4

12L

MCP1600

Western Digital

8-16

NMOS

4

Microinstruction time, p.s

1 Mbyte

>10

64

+5V, injection current 40pin +SV

4096 bits

DMA

DMA Multi-

+5V 16 500 mA (in mem- injection ory) current

Has

lowpower

mode Many

40 pin 48 pin

Highlevel language oriented

Table 11.2-and 4-bit bipolar microprogrammable processor slice components.

Device

Originator/ Function secondsource

AMD(4)

1 2910+ 2922 2905,6,7 0.3

2930 9404+ 9405A

Fairchild (1)

9408

PROCESSOR

No hmit

64 8 Mbytes

2901A

SYSTEMS

9407 9406

3002

Intel(1)

3001 3212

TechnoIogy

16-bit m icro-

instruction time, ns*

During the past year, the various bipolar families have become established and enhanced-performance (A)

4-bit ALU +RAM

Low140+ power Schottky

12-bit MCU system 4-bit bus interface PCU 4-bit ALU 210+ +RAM 10-bit 13L 4-bit Lowmemory power interface Schottky 4-bit program stack 2-bit ALU Low+RAM power Schottky 9-bit MCU 8-bit bus interface

6701

6710 10800+

Mono4-bit ALU lithic +RAM Memories

Motorola

(1)

vol 2 no 1 february 78

Notes

0.5

PMOS and NMOS types have been joined by recently announced 12 L, I a L, CDI and CMOS-on-sapphire devices (Table 9); (although the author is not sure if the CMOSon-sapphire device will be marketed). VMOS and DMOS are other contenders, but recently the industry trend to the HMOS approach 6 has been noticeable. A number of high-performance 16-bit systems will become available in small quantities mid-1978. At present, very little information is released, the data in Table 9 being the best availabe the best available. Manufacturers are also tending to use a multiplexed bus system to keep within 40-pin package limitations, and it is to be expected that 'interface sets' will become available from more of them. BIT-SLICE

Working Power regtsters supplies/ package

ply/ divide chip

8086 Intel HMOS (mid 1978) SBP Texas 12L 9900 Instruments (now)

Device

Address range, kbytes

10801

4-bit MCU 4-bit ALU

Single 210+ layer Schottky LSI ECL LSI < 100

4-bit MCU continued overleaf

19

Device

Originator/ secondsource

10803

Motorola

74S481

Texas Instruments

74S482

Function

4-bit memory interfacing 4-bit ALU 4 - b i t MCU

TechnoIogy

16-b~t microinstruction tlme, ns*

"

STTL LSI "

* Approxlmat~ons for 32-b~t shift/add for 16-b~t

multiply micromstructmn

versions are coming out for some (Table 11). Applications information and support equipment is available from some manufacturers. In mmmcomputer replacement apphcatlons, multiplication/divlmon functions are likely to be required, and some bit-slice systems are more suited to this than others. Also, the performance of bit-slice systems can be considerably enhanced by adding extra MSI logic functions s . For future developments, one can predict that 8-b~t shces wdl become available, and that another ECL family is under development.

REFERENCES 1 Russell, D 'A survey of the available chips' Microprocessors at work SERT, London (September 1976) 2 Microprocessors - their development and application

ERA, Leatherhead, UK (April 1976) 3 Lee, M D 'The applicability of eight-bit microprocessors to a s~xteen-bit environment' 4 Capell, et al. 'Process refinements bring C-MOS on sapphire into commercial use' Electronics (26 May 1977) pp 99--105 5 Muething, G F, Jr 'Designing the maximum performance into b~t shce minicomputers' Electronics (30th September 1976) pp 91-96 6 Altman, L 'New MOS processes set speed, density records' Electronics (27 October 1977) pp 90-94 7 Airman, L 'Microcomputer families exand, part 1 : the new chips' Electronics (8 December 1977) pp 89-99

BIBLIOGRAPHY Bzersky and Barnes 'Choosing a microprocessor by its capabilities is a family affair' Electron. Des. Vol 14 (July 1977) pp 26-38 Chapple, K 'How to choose a microcomputer vendor' Intel '77 Fair

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