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MICROPROCESSOR SYSTEMS DWIGHT H. SAWIN I I I Center f o r T a c t i c a l Computer Sciences Communicotlons/Automatlc Data Processing Laboratory U.S. Army Electronics Command Fort Monmouth, Now 3ereey U.S.A.
Abstract- While slot of literature Is available describing indivlduml microprocessor (g-p) chips or chlp m o t e t this Informmtion only exposes the tip of mn iceberg. The remainder of t h e iceberg concerns t h e impact of ~-p8 on system design and development. This paper a t t e m p t s to focus on the c o n s i d e r a t i o n s mnd avenues o? approach to be used when d e s i g n i n g w i t h ~-ps. LSI c i r c u i t s o t h e r than ~-ps are d i s cuesed~ along w i t h p r o t o t y p i n g u n i t s and design t o o l s f o r both hmrdware and s o f t w a r e . F i n a l l y e look s t o v s l l o b l o components above the chip o r basi c design l e v e l 18 taken. The i n t e n t o f the d i s cussion 18 to f a m i l i a r i z e the reader with the many rmclts or , - p system design which are not r e f l e c t ed i n dlecumslng o n l y the processors themselves. R a t h e t j many o f the s u p p o r t elements, r e q u i r e d t o make ~-ps useful computers, o r e considered. INTRODUCTION Microprocessors (~-p8) are causing • g r e e t d e a l o f e x c i t e m e n t throughout the computer w o r l d . Reali z a t i o n s of promises for cheap, powerful processors at extremely low cost and size ere setting off 8 revolution in s y s t e m design. While none of the b-ps available or announced i s ideal for every a p p l i cation, a imrge amount of engineering hoe been done for the system deelgner who chooses to go the ~-p route. Unfortunately, to dote, s l o t has been said about the processors themselves end little about 811 the support elements and tools which are needed to produce usable ~-p based systems. This paper concentrmtee on describing these " o t h e r elements". DiscOo81ons about o t h e r LSI c i r c u i t s to s u p p o r t ~-ps, design tools, software support and some of the con81dormtlons i n s e l e c t i n g • ~-p are i n c l u d e d . Throughout • system design i t Is important to keep 8 perspective on different system ports. A terrifically powerful ~-p le nice but its effects on the more expensive components of the system may be more Important. Things llke memory, p e r i p h e r a l s end s o f t w a r e , l i k e l y oostlng many tlme8 more than the b-p, should be considered in d e t a i l . For i n stance, choosing 8 ~-p which requires large amounts o f memory end flnishes tasks in blinding speed i~ The o p i n i o n 8 presented hero are s o l e l y those o f the author and should n o t be i n t e r p r e t e d ms o f f i c i a l p o l i c i e s o f the U.S. A ~ y E l e c t r o n i c s Commend o r the U.S. Government, Furthermore~ the ment i o n o f px'oducte o r monufocturors does n o t c o n s t i t u t e i n endorsement by e i t h e r the author o r the p r e v i o u s l y mentioned agencies.
senseless i n on a p p l i c a t i o n which has very 8low r e 8pones times. Equally polntlee8 18 the often preconceived notion that e l g h t - b i t (byte) dots must be handled by en e l g h t - b l t ~-p. Nothing could be more misleading; rather the amount of time to accomplish tasks must be oonsldored. I t i s oleo interesting to note that no manufacturer of ~-p8 seems able to survive solely on the p r o f i t s of ~-p select but'more often have 8 vested i n t e r e s t in memories, perlpherels or systems design by which they prosper° This has led to " k i t pricing" where 8 single price i s quoted for both the ~-p and i t s related parts. Usually the k i t or bundled price w i l l be less than the sum of the unit prices at the same quantity level, implying that the ;>p is cheeper or even free in return for the rest of your b u d nose. Hopefully the emphasis on the aspects which make up total systems, rather than single chlps, is s t r e s s e d here, Systems containing ~-p8 are different from those designed wlth random logic in that they tend to be more complicated because the price for adding extra features has been lowered significantly. Likewise they are often more flexible due to the "programmable" c a p a b i l i t y of this sort of logic design. An emphasis on the "programmable" logic is important for this i s the heart of the ;~-p technology. Programmability should be emphasized in a l l types of logic design, whether i t be 8 ~-p based system or any other microprogrammed design. Use of ~-Pe dictates that the system designer attempt to complete the entire task using only the ~=-p end as little peripheral logic as possible. The problem of when to odd external hardware is a difficult one end often is almost impossible to answer. Use of standards, in system design, fat buses and intsrfecin 9 will help ease the burden when system hardwore must be changed. A v a i l a b i l i t y end newness of parts are key p r o b lems in system definition. While newer ~-pe hove been designed by computer archltect8, rather th~n semlcon~uctor circuit deslgner8 t benefitting from past e x p e r i e n c e , many of tho8e products never g e t off the drawing boards. At 8 time when second sources ate extremely limited it may be wise to go with an available product. As time goes on more multiple sourced devices will appear 81ong with larger ports fmmilles, oompetlble peripheral devices end design tools. ~ t o n l y a t e !L-ps changing the design o f systems, they are o l e o changing the demands on the de81gner8 who use them. The question of selection of designers can best be charocterlzed by both hardware end soft-
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were understanding, not Just one of the two. ~-ps require "system people" who can comprehend hardware and s o f t w a r e i n t e r a c t i o n . T h i s I s i m p o r t a n t because the d e s i g n e r oust f i r s t t r y to s o l v e the ent i r e problem i n s o f t w a r e , f a l l i n g beck on hardware solutions only after all avenues of attack through software hove failed. Throughout the remainder of the paper some familiarity with p a r t i c u l a r ~-ps i s a s s u m e d . D e t a i l s on those may be found In 3 a r t y Ogdtn's " R l c r o p r o csssor Scorecard" ( p r e v i o u s l y p u b l i s h e d i n EURORICRO Newsletter), As an update of s o r t s , the d e s c r i p t i o n s below concern more r e c e n t ~-ps o r g i v e • few more d e t a i l s which were not p r e v i o u s l y a v a i l a b l e on announced o r rumored p r o d u c t s . These new ~-ps show the trends toward lower prices (but not as quickly me f i r s t t h o u g h t ) , l a r g e r word l e n g t h s ( 8 , 12 and 1 6 - b i t s ) , more o v e r a l l s o p h i s t i c a t i o n end f a s t e r speeds. General Instruments CP-1600- A s i n g l e , 40 p i n c h i p emulstln9 the D i g i t a l Equipment Company (DEC) POP-
11, the 1800 has 88 fixed Instructlons which are executed i n 1.8 to 4.8 microseconds. 1 6 - b i t words are used, w i t h double p r e c i s i o n add, s u b t r a c t and l o g l c s l s being a v a i l a b l e , along w i t h 8 working r e g isters. P r i o r i t y i n t e r r u p t s ere included with d i rect addressing for the first 1K of external memory. Input/output ( I / 0 ) devices are treated like memory. N a t i o n a l Semiconductor PAC~- The "programmable a r i t h metic and c o n t r o l element" c o n t a i n s go~ o f the capa b i l i t y or the 1 6 - b i t IRP-16 i n a s i n g l e 40 p i n peckage. The f i x e d i n s t r u c t i o n s e t i n c l u d e s 43 b a s i c IRP-18 commands end handles data on a f u l l 1 8 - b i t wide b a s t e , o r i n s i n g l e b y t e s . I n s t r u c t i o n execut i o n times are i n the 10 mioroescond r e g i o n . Remo r y d a t e and address l i n e s are common and • 10 deep stack i s i n c l u d e d t o l i n k s u b r o u t i n e s end i n t e r r u p t r o u t i n e s from the s i x l e v e l v e c t o r i n t e r r u p t scheme. S c ~ l n t i f i c R l c r o Systems- A f a s t b i t / b y t e o r i e n t e d c o n t r o l l e r p t i t h e r than an a r i t h m e t i c p r o c e s s o r , the SRS m l c r o c o n t r o l l e r c o n s i s t s or s e v e r a l p r o p r i e t a r y s c h o t t k y TTL LSI c h i p s mounted on a m u l t i - l a y e r c e r amic s u b s t r a t a . I t s i n s t r u c t i o n set contains only add, end, and e x c l u s i v e - o r coamanda along w i t h sophi s t i c a t e d s h i f t i n g , b i t t a s t i n g and d a t a moving capabilities. 4K o f e x t e r n a l memory i s d i r e c t l y a d d r e s s a b l e w i t h 1 B - b i t I n s t r u c t i o n s e x e c u t i n g i n 300 nanoseconds. I n t e r r u p t s must be handled by s o f t , m r s polling. Texas I n s t r u a e n t l SAP0400- The SBPO400 i s • f o u r b i t s l i c e , p a r a l l e l expandable ~-p i n • 40 p i n package. I t i s TTL c o m p a t i b l e , asynchronous l . a . needs no c l o c k s , w i t h a f u l l y p a r a l l e l a r c h i t e c t u r e a l l o w i n g o v e r l a p p i n g of fitch and e x e c u t i o n c y c l e s with a f o u r - b i t add time o f 500 nanoseconds, and 1 8 - b i t add and m u l t i p l y times o f 850 nanoseconds and 20 microseconds. E i t h e r I PROR (programmable r e a d only-memory) or a PLA (programmable l o g i c a r r a y ) can ba used to insert • fully mloroprogrammible i n s t r u c t i o n eat. Western O l g l t a l RPS-1600- T h r o e c h i p s c o n s i s t i n g or d a t a , c o n t r o l end microROR, destqned t o emulate the POP-11, the RPS-1BO0 f e a t u r e s a 300 nanosecond m i c r o i n s t r u c t i o n access time. I t contains m 1 8 - b l t memo r y access p o r t and 28 8 - b i t r i l e r e g i s t e r s In an B-bit internal organization with capabilities for b y t e and 1 6 - b i t d a t a word o p e r a t i o n s . The 2 2 - b i t m l c r o l n e t r u o t l o n a i n c l u d e dacle,al ss w a l l as b i n a r y a r i t h a e t l c and f o u r p r o g r m e b l e e x t e r n a l l i n e s f o r use as c e n t = e l f u n c t i o n s .
In addition to these new processors two new ~-ps from Europe have been announced. One is an 8bit system conslstlng or 15 ROS LSI circuits cooperatively produced by AEG-Telerunken, General I n s t r u ments and SGS-Atas with Olympia Works s e l l i n g a t o t -
a l ~-p system.
The other, also 8 - b l t s t Is produced
by Nlxdor? Computer AG.
RERORIES FOR RICROPROCES50RS Programmable l o g i c design r e q u i r e s e x t e n s i v e use or e l l s o r t s o f memory elements. While the concepts being used r e d l y i n l o g i c design have bean around f o r q u i t e sometime, the a v a i l a b i l i t y o r r e a sonably priced memory elements has made the , - p r e v o l u t i o n possible. The choice of p r o p e r memories f o r • ~-p system i s i m p o r t a n t s i n c e the cost o f memory w i l l p r o b a b l y be over ½ o f the chip c o s t end 25-30~ o f system c o s t . For i n s t a n c e 16K o f s t a t i c randomaccess-memory (RAM) f o r an Intel 8080 costs around $1K w h i l e the c o s t o f the processor i s $350. The types and uses o f a v a i l a b l e memory are d i s cussed below, brnlle c o s t and f l e x i b i l i t y decrease going down the l i s t , e v e i l s b l l l t y i n c r e a s e s , making the l o w e s t c o s t , l e a s t f l e x i b l e memory, the most readily available. Figure 1 shows • summary o f f e a t u r e s and costa f o r p o p u l a r ~-p memory elements ( 1 ) . Access Time cent/blt Remory S~aps (~ssq) Technolooy ~@100) RAR 1024xl 1. NROS 1.5 256x4 .8 NROS 1.6 4096x1 1.* NROS .4 256xl ,0? Schottky 5.1 ROR 2048x8 1.2 NROS .2 256x8 1, PROS 1.2 I024x8 .45 NROS 1.8 512x8 ,07 Schottky 3.0 PROR 256x8 1. NMOS * * 1.5 512x8 ,5 NHOS * * 2.4 512x8 .1 Schottky 3.8 256x4 .07 Schottky 2.0 * dynamic * * uv e r a s a b l e Figure 1, Summaryo f Features end C o s t s . Electrically A l t e r a b l e RA~ (EARARS)-Those m e m o r i e s ere r e a d / w r i t e semiconductor RARe which are n o n - v o l a t i l e and have r e s t read times~ b u t slow w r i t e times. They o f f e r the advantage o f being v i r t u a l l y changeble ROR~ i . e . they can be used I n m o s t l y the reed mode but occasionally rewritten, C u r r e n t l y EARARi a r e almost n o n - a v a i l a b l e and are e x t r e m e l y e x p e n s i v e . For the time being they w i l l p r o b a b l y be l i m i t e d t o e x o t i c , s p e c i a l requirement a p p l i c a t i o n s , perhaps becoming more l i k e o f f - t h e - s h e l f items w i t h i n • year o r two. RARe. There are two basic types o f RARI a v a i l a b l e : core and semiconductor. Rest ~-p s y s t e m s use the semiconductor type r o t the s i z e end speed advantages, along w i t h p o l a r and c o s t s a v i r ~ e i n s m a l l s i z e memories. Two types o f semiconductor RA~ being manuf a c t u r e d are s t a t i c s and dyne=Ice. States RARe are composed o f an a r r a y o f d i r e c t l y s d d r e a l i b l e b i s t a b l e s t o r a g e elements. They a r e n o ~ e l l y 1K o r l e s s i n b i t s and consume around 500 m i c r o w a t t s per b i t i n the a c t i v e and standby modes. (CROS RARe use l s l e power but hays slower c y c l e t i m e s . ) The c y c l e times o f these RA~ range f t o ~ 70 nanoseconds on u p w a r d . The most p o p u l a r c o n f i g u r a t i o n s I r e 1Kxl such as the I n t e l 2102 which i s w i d e l y second sourced w l t h v a r i o u s
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256x4 and 128xB d e v i c e 8 r a p i d l y g a i n i n g p o p u l a r i t y . Dynamic RARe s t o r e I n f o r m a t i o n I n t h e c a p a c i tance o f a s i n g l e t r a n s i s t o r which p e r m i t s f a b r i c a t i o n o f more memory c e l l s p e r u n i t a r e s than s t a t i c s . The c a p a c i t o r s a r e somewhat l e a k y and charge8 on them must be p e r i o d i c a l l y refreshed. Refreshing 18 u s u a l l y e o c o m p l l s h e d by c y c l i n g t h r o u g h 32 a d d r e s s 08 I n two m i l l i s e c o n d s . These r e f r e s h c y c l e s e r e i n t e r l e a v e d between memory accesses d u r i n g t h e two millisecond interval. T h i s doe8 r e q u l r e more o v e r heed c i r c u i t r y then • s t a t i c RAM, b u t t h e c i r c u i t r y t 8 f a i r l y s i m p l e and c o n s t a n t i n s i z e f o r l a r g e o r 8m811 memory c o n f i g u r a t i o n s . Dynamic RAR8 draw a b o u t the same amount c? power o r perhaps 8 l i t t l e more, than s t a t i c s I n t h e a c t i v e mode, b u t draw l o s s than 1 mlcrowatt p e r b l t in standby. Popular conf i g u r a t i o n s f o r t h e dynamics a t e 1Kxl and 4Kx1. The I n , e l 1103 w a s t h e f i r s t and p r o b a b l y most w i d e l y u s e d o f the 1K8. I t i s a v a i l a b l e In • wide range o f speeds v a r y i n g from 250 nanosecond8 t o around 1 m i c r o s e c o n d , end 18 w i d e l y second s o u r c e d . In 4K dynamics the Rostek 4096P and the I n , e l 2107 e r e characteristic o r whet 18 a v a i l a b l e . The meet s i g n i f i c a n t d i f f e r e n c e i s i n package p i n c o u n t . The 2107 uses 22 p i n 8 w h i l e the 4095P uses o n l y 16 p i n s by m u l t i p l e x i n g l i n e s to a c c e p t the a d d r e s s e s I n two bytes. While t h i s c o m p l i c a t e s the a d d r e s s i n g l o g i c it increases the density or chips significantly. Typical 4K cycle times run from 200 nanoseconds to I microsecond. U n t i l recently many 4Ks also e x h i b i t ed pattern sensitive f a i l u r e s . These data dropping problems have been cleared up in many products but designers should be wary or such problems. RORs- Read-only-memories are used for unchanging s t o r e d d a t a such a s i n s t r u c t i o n s e t s end t a b l e s . They o r e not generalized memories in that they a r e not readily alterable, but rather 8 hard-wired storage mechanism that is laid down on the chip to de?Ins the data pattern. One o f the standard uses f o r ROMe i s t h e c o l d s t a r t program .or l o a d e r I n e system. Three commonly used t y p e s of ROMe a r e ultra-vlolst (uv) light erasable, Fuse link, and masked. The uv e r a s a b l e and ruse llnk ROMe a r e often designated as PROMs. due to t h e i r f i e l d programmable c a p e b i l l t i a 8 . With uv e r a s a b l e PROMs d a t a can be erased by e x p o sure to on u l t r a - v i o l e t l i g h t source and then the same d e v i c e may be reprogrammed. Thls p r o c e s s is markedly different from EARAMs because the whole dsv i c e must be reprogrammed, n o t s e l e c t e d l o c a t i o n s , and it may tequlrs removing the device from the memory system. The most popular uv PROM is the In,el 1702A which i s o r g a n i z e d 255xB and has access times around I microsecond, else i t s programming tlms i s less than two minutes. This is s i g n i f i c a n t because some uv PROMs r e q u i r e o v e r 30 minutes t o r e l i a b l y program. A new I n , e l uv PROM i s the 5704 which is a r r a n g e d 512xB with a n access time o f 500 nanoseconds, making i t the f i r s t or i t s type which i s f u l l y speed compatible with second generation u-p8 such 8e the BOBO. Fuse l i n k PROMs a t e p e r m a n e n t l y programmed by b l o w i n g o u t i n t e r n a l fusee t o d e f i n e one8 o r z e r o e s . Once the ruses are blown they cannot be reprogrammed. T y p i c a l PROM s i z e s a r e 1K a r r a n g e d 256x4, 2K a r r a n g e d 512x4 end 4K a r r a n g e d 512xB. These d e v i c e s a r e w i d e l y m u l t i p l e sourced and e x h i b i t access times down t o around 50 nanoseconds. Masked ROR8 a r e c u s tom made, when t h e d e v i c e t o c o n s t r u c t e d , by m l t e ~ l n g t h e masking p r o c e s s . They c a n n o t be changed once f a b r i c a t e d , and vendors u s u a l l y s t i p u l a t e s mask charge o r s i z a b l e volume g u a r a n t e e s to b e g i n p r o d u c -
tlon.
D m l i v o r y t i m e s a t e 8~8o l o n g e r than o t h e r m e m due to mask t i m e s . S i z e s range from IK to 16K i n many c o n f i g u r e , l e n s e i n c l u d i n g mlmoet e l l o f t h e p o p u l a r RAM and PROM c o n f l g u r a t l o n 8 . Access t i m e s v a r y w i t h s i z e b u t m o s t ROMe e r e speed c o m p a t i b l e w i t h o t h e r t y p e s o f memories. The 16Ks e x h i b i t met e s s t i m e s o r .5 t o 1 m i c r o s e c o n d . Power d i e e a p e t i o n , ~ e t b i t , goes down m a r k e d l y from the uv &@'~eeked ROR8 p r o v i d i n g access t i m e s a r e c o m p a r a b l e . Pro|rammable L o g i c A r r a y s (PLAsh- In a ROR a ? I x s d d e c o d e r t r a n s l a t e s an i n p u t a d d r e s s t o a memory oo11. T h i s t y p e o f decoder r e q u i r e s t h e ROR to c o n t a i n 811 p o s s i b l e memory 00118 even though many c e l l s may c o n t a i n t h e same d a t a . Raking t h e decoder programmable a l l o w s t h e mapping o f s e v e r a l i n p u t a d d r e s s e s o n t o one memory oo11, thus making mote e f f i c i e n t use o f storage. Thru t h e use o f such a d e c o d e r t h e PLA can r e a l i z e s l a r g e r number o r l o g i c a l ? u n c t i o n s / c h i p . P r e s e n t l y PLA8 e r e mode by I masking process l i k e masked RORs. An o f t e n o v e r l o o k e d memory e l e m e n t 18 the s h i r t register. Those d e v l o e s a r e r e l a t i v e l y 81ow by n o r m81 TTL standards, but often work w e l l with ~-p8. They make quite nice sequential access r i l e s and ors low In cost, small i n 81ze and low in power coneumptlon. A ~-p eye,am often proceeds thru many types of memory In d e s i g n s t a g e s . D i s r e g a r d i n g EARAR8 because of lock of availability, systems u s u a l l y b e g l n w l t h RAM or uv PROMs t o e n a b l e changes t o o c c u r i n t h e early stages of design. L a t e r on a change t o PROM before fielding the system often occurs and then to masked ROR for production. At the same time random l o g i c may o l e o be c o l l e c t e d i n t o 8 PLA. A good p r a c t i c e Is that of f i e l d i n g the system wlth other then masked RORe and PLA8, a t l e a s t f o r t h e f i r s t t i m e so that user deelrad changse'm8~ be included before flnal masks a r e made. T h l 8 e v o l u t i o n may i n v o l v e v o l t age l e v e l changes from.TTL to MO5. d i f f e r e n t power s u p p l i e s , o r changes i n p h y s i c a l s i z e o r p i n c o u n t . F a i l u r e to c o n s i d e r these changes i n the p r e l i m i n a r y s t a g e s o r system l a y o u t con r e s u l t i n • m a j o r r e d e sign. Memory organization i s another important system consideration. I f an eppllcetlon c a l l s for 256 bytes or memory, i t may be less costly to use two s t a t i c devices organized in 8 12Bx8 or 255x4 configuration even though those devices cost more individually than IK dynamics. Eight IK dynamics would be required to do the job and three-fourths of it would not be used, along with power consumption end s i z e i n c r e a s e s , rano u t problems con a l s o be a v o i d e d by p r o p e r c o n f i g u r a t i o n cholce. Configuration problems often can be av o i d e d i n changing from RAM to PROM o r masked ROR by adopting Interface standards within • system or company, which are timing independent. A key to the development of programmable logic i s compatible memory with 4 - b i t processors requiring 1 t o 5 microsecond c y c l e t i m e s , and B - b i t p r o c e s s o r s r e q u i r i n g 500 nanosecond t o 2 microsecond c y c l e t i m e s . New, b i p o l a r p r o c e s s o r s r e q u i r e access t i m e s o f 70 to 300 nanoseconds for PROMs s t o r i n g the mio~ocode. These p r o c e s s o r s e~s t o o f a s t for uv PROMs and e x h i b i t some problems i n h a n d l i n g RARs. Thus memory d e v e l o p m e n t s must keep pace w i t h these new d e v i c e s i n order that they may be easy to use. Trends in memory d e v i c e s a r e toward l o w e r power, f a s t c y c l e t i m e s , more e e s i b l y u s a b l e c o n f i g u r a t i o n s , and l a r g e r memory s i z e s I n a l l t y p e s o? d e v i c e s d i s c u s s e d . Examples o? these e r a p r o m i s e s o f f i e l d programmable PLAs f o r around J50 and r e o r g a n i z a t i o n s o r 4K RAMS i n t o 512x8 s i z e s . ories
29
HARDWARE Ei E~ENT5 Since l~-ps are not stand-alone computers they are essentially useless until interfaced with other logic~ peripheral devices and a memory to hold instructions and date. Interfaclng a ~-p is not always an easy task and can be a considerable impediment to its appllcstlon. The electrical spaclfications of a ~-p and its associated parts Family will tell the designer as much about potential interfacing problems as an instruction set tells a programmer about the nature of potential software problems. Unfortunately these specifications are normally the last piece of information released by the manufactbrers end are usually subject to change. The words "TTL compatible" are often misleading and can result in many ~ystam problems if output levels and drive cepabllltles are not checked carefully. MOS and other LSI circuJt techniques often force the use of pull-up or pul]-do~n reslstore on outputs end limited Fan-out st normal ITL levels. For ease in development t~-p circuitry shu,Jld interface directly with any support logic required for a system, especially memories. Several other points should also be considered in looking st the electrical specifications. An important consideration is the number of power supplies and voltage levels required. The voltages should be compatible with those required by the memories, support logic and the remainder of the system. For instance, if the system under deelgn has analog components, several different voltages may already be available and pose no problems. But if the system is all digital and to be battery powered, limiting the number of voltages, supplies and total power consumption is very important. Non-compatlble voltages may also indicate that level shifting is neeasd between chips. The ability of a ~-p to drive buses and the availability of electrically compatible components simplifies things greatly. Most ~-ps hays low drive capability due tc power dissapation oonstrairts on the chip. A good rule of thumb to remember is that a chip can usually dlssapate around one watt. Circuit response times and clocking requirements should also be thoroughly studied, avoiding typical times which dlplct d e v i c e s to o p e r a t e fastsr than they can reliably, and looking for minimum and maximum delays. Again these should be system compatible, i.e. wlth all parts used in the design. Clocking almost always requires outside support and the a v a i l a b i l i t y of devices to do the job d i r e c t l y Is convenient. Some manufacturers such as Intsl and Rockwell, supply apsclel clock generating chips. Others, llke Fairchild, have ~-ps which require only • crystal or aeries R-C network. Many a-p systems use OlP-ahapsd crystal clocks such ms those offered by Motorola and V a o t t o n . While system buses should be compatible and timing independent, s good, s t r o n g clocking scheme for each of the subsystems attached to these buses is important. This type of design yields faster operating, omelet to debug, more reliable and maintainable systems than many other approaches-
Packaging of ~-P systems is a problem o f conaldmrabla concern, Just as in large, computer systmma. An exmmpla o f thle Is the fact that the actual c i r c u i t r y i n a computer system r e q u i r e s t h r e e t o f i v e magnitudes l e s s volume than t h e o v e r a l l p h y s i c a l volume o f the system. This - e x t r a " volume
is taken up by connectors, heat sinks, fans, lamps, switches, and all the other physical packaging aspects of s system. Due to the size of the chips (up to 42 pins), logic board size and heat dissapation can also cause problems in ~-p systems. Sparsely populated boards result if the ratio of board space to output pins is not considered. While ~-ps consume less power than comparably powerful MSI designs, they tend to localize heat and create "hot spots". Large boards containing both the ~-p and memory may require fans or heat sinks. Fortunately present ~-ps are fairly noise immune due to the lower speeds of the chips as compared to support logic. However, bipolar chip sets may exhibit noise problems if layout rules are not carefully followed. One answer to the a-p packaging problem is to use hybrid technology. This involves laying dice on a hybrid substrata and then packaging the hybrids as functional units. The industry leader in the a r e a seams to be Teledyne Systems Company. Among their products are the TDY-52A, which employs an Intel 4004, and the TOY-52B, which employs a National IMP, along with promises of developing a fast multiply module, an analog to digital converter end a control module for operating multiple processors with a common memory. Overall this type of technology seems to provide s good alternative to specialized system designers who are not interested in manufacturing devices, The t y p e o f i~-p s e l e c t e d w i l l n o r m a l l y i n d i c a t e how much direct interfacing is required. Systems requirements will dictate the remainder of the problem. The Four-bit ~-ps often share address and data lines, requiring external latches to separate out and assemble t h i s information. The I n t s l 4004 has the 400B and 400g chips to supply an interface to "standard" memory and I/0 t while the In,el 4040 employs a single chip, the 4289, to do the job. Regardless of which chips are used, the point is that external logic is required to support the p-p. Rest eight-bit machines have a central bidirectional bus, over which internal status data is received, I/O ports are derived, interrupt data is entered and memory accesses are conducted. In first generation eights the memory address is also on this bus and must be assembled from the two bytes delivered. Sharing of data and address lines is also ue6d in several 12 and 16-bit tL-ps, due to pin limitations. One method of handling the "universal" bus is vie s bus interface latch/drlver which is electrically compatible and has the proper control signals to communicate with the ~-p. The In,el 8212, an elght-bit I/O port, and the 8228, a system controller, which are used with the 8080, are such devices. Another solution to managing the bus is a complete family of parts to f a c i l i t a t e system design. The Rockwell PPS-4 system e x e m p l i f i e s t h i s c o n c e p t . Bipolar slice architectures are actually extended register, arithmetic logic units (ALUs) with perhaps soma aid in solving the address generation problems which develop. The Monolithic Memories 6701 is such an extended ALU end requires the addition of mircoprogram memory, registers, addressing logic and other items to make it s complete processor. The Intel 3002 is the same type of thing except that it is two bits wide, rather than four, and has the 3001 to aid in address generation for the mlcroprogram. Both of these blpolars require • significant amount of design to make them functional. In the non-bipolare, the National GPC/P has a full family of parts to
30
s u p p o r t its ALUs. More importmntly~ National o f f e r s a standard Inatzuotlon set for those who do not wish to attempt mlcroprogr•mming. Single chip b-pa •re much more r e l i a b l e and easi e r to m•intaln than multiple chip processors. There are alas several other desirable features, from the systems standpoint, that the mL-p should contain. A reset signal i s important to i n i t i a l i z e the system. Likewise a hold or stop function which places the ~-p in • wait status i s important in multiple processor, memory sharing or direct-memory-access (DRA) app l i c a t i o n s . In such cases the i~-p should be atoppsble during an Inetructlon fetch cycle, not Just at the completion o f instruction execution. Forcing e wait state by halting the clock is both cumbersome and dangerous, especlslly if the ~-p is • dynamic device, • s it may not be able to complete its refresh cycle. S i g n a l s d e n o t i n g the i n t e r n a l s t a t u s o f the ~-p end the state of the central buses are also Important. These signals should alas acknowledge acceptance end recognition of externally applied signals. An interrupt llne and interrupt •cknowledga signal, along with the ability of the ~-p to lock out or dlsable interrupts, are extremely important in many reel-time control epplicatlons. Rest ~L-pa have only a single llne interrupt and some sort of poll~ Ing o r searching sequence must be performed to identify the cause of the interrupt. The use of interrupts in u-ps almost always requires external herdwere support. This external hardware may be available as one or more LSI circuits in the t,.-p#s ports ?emily, or as is often the case, it must be designed by the user. An exmmple of such an interrupt support circuit is the Intal 8214, a priority interrupt control unit which handles B interrupt request lines via a programmable priority end then vectors them to the processor. U-p response to an interrupt is else important to note. Of the two most common actions, vectored and trapping to e specific location in memory, v e c t o r i n g r e q u i r e s l e s s s o f t w a r e overhead and has fester response times, but normally requires more hardware support. To successfully interface a u-p the user must understand its basic operational cycle. This includes when end how the ~V-p does • memory cycle, how the memory address is generated end what control signals era used. Such questions as st what point in the machine cycle does the ~-p examine hold, reset, end interrupt lines, end whet actions it takes upon a c c e p t i n g these s i g n a l s must be answered. Methods of doing I/0 and determining the internal stqtus of the processor must also be available. Such Information is every bit as important to the user as a complete description of the instruction met, and should clearly be outlined in the documentation supplied by the manufacturer. This section concludes with a brief overview of the parts families end system cepsbillties of three tJr--pa. Outlined are the Rockwell PPS-4, the Motorola 6BOO and the Toshiba TLSC-12 systems. These systems ere available end characteristic of what good parts families contain. While no IL-p family is perfect for ell applications these examples yield many of the elements that should be considered in selecting a t~-p family for systems application. Rockwell Pp,S~4- This system, shown in Figure 2, p r o v i d e s e f o u r - b i t processor which handles e l g h t - b l t instructions. I t employs e four-phase clock, operates dynamically, can address up to 16 I/0 devices and has e 294,g12 bit memory capacity. The individual parts of the family ere described below.
address
Clock Ggn- Generates the b a s i c f o u r phase c l o c k revq u l r e d by the CPU. ROM- A v a i l a b l e c o n f i g u r a t i o n s i n c l u d e 1KxB and 2Kx8 masked RORa. Also a v a i l a b l e i s • b l o c k e r a s a b l e EAROR i n a 256x8 a r r a n g e m e n t . RAM- A 256x4 RAM end • 256x4 NVRAR (EARAR) p r o v i d i n g word e r a s a b l e , n o n - v o l a t i l e d • t • s t o r a g e . ROR/RAR- T h i l unique d e v i c e o f f e r s both RAM and ROR c a p a b i l i t y in • slngle package. Two configurations 704xB ROR end 76x4 RAM o r 1024xS/116x4 •re • v a i l able. GPI/O- General purpose i n p u t - o u t p u t p r o v i d i n g 12 d i s c r e t e i n p u t s and 12 s t a t i c o u t p u t s from the PPS4 d • t • bus l i n e s t o e x t e r n a l MOS o r TTL c i r c u i t s . GPKD- General purpose keyboard and d i s p l a y c o n t r o l p r o v i d e s 64-kay s t r o b i n g t kay dabounce, 2-key r o l l o v e r p r o t e c t i o n , g - k e y b u f f e r i n g and two 16 ( 4 - b i t ) character display buffers. PC- Printer control providing 21 4 - b i t character p r i n t buffers end automatic timing end control For the Selko 101, 102, and 103 p r i n t e r s . Tom- The telecommunications data interface is a Bell 202 compatible d l g i t a l modem with universal asynchronous r e c e i v e r / t r a n s m i t t e r (UART) c a p a b i l i t i e s of 8 to 64 b i t ch•racters, KPC- K • y b o • r d / p r i n t e r c o n t r o l l e r p r o v i d i n g the capa b i l i t y o f r e a d i n g e 64-key keyboard and c o n t r o l l i n g the Ssiko 320 p r i n t e r . DC- Display controller ualng i n t e r n a l buffering, decode logic end output strobes to control m 16-dlglt display.
B / I - Bus i n t e r f a c e element from TTL l e v e l s to the PPS-4 data bus. SDC- S e r i a l d a t e c o n t r o l l e r which i s RS-232-C comp a t i b l e and capable o f asynchronous d a t a t r a n s m i s s i o n with odd/even p a r i t y and one or two stop b i t s . M o t o r o l a 6800- B i d d i n g to a c h i e v e s t a t u e as the f i r s t " i n d u s t r y s t a n d a r d " , t h i s system, shown i n F i g u r e 3, p r o v i d e s •n e i g h t - b i t p r o c e s s o r (RPU) capable o f add r e s s i n g 65K bytes, complete with i n t e r r u p t c a p s b i l l t ym power on r e s t a r t and a r i c h fmmlly o f p a r t s . The add r e s s i n g problem between the parts family has been solved in • very flexible manner by offering both p o s i t i v e and n e g a t i v e enable c i r c u i t s on most c h i p s o r making the c h o i c e s p e c i f i a b l e by the u s e r . All p a r t s •re, or w i l l be, second sourced t h r u American Micro Systems v i a •n "official license". Other companies such •s ROS Technology and posalbly Rostek mrs fabricating parts compatible with the 6BOO bus. RAM- Compatible s t a t i c RAMs i n 12BxB and 1024xl conflgur•tlon8 along with • 4Kxl dynamic RAM ere available. RDM- Masked ROMs i n 1Kx8 mnd 2Kx8 c o n f i g u r e , l e n a . PIA- Peripheral interface adapter allowing the RPU
31
to control transfers of data mnd status Informetlon to end from perlpheral devices v l s b i d i r e c t i o n a l l i n e s . PI~ looks l l k e m smell number o? adjacent etormge bytes and normal LOAD mnd STORE Inetructlons are used to communicate between the MPU accumulators and I t s s i x r e g i s t e r s . D a t t t r a n s f e r c o m p l e t i o n s ere e i g r m l l a d v i e an i n t e r r u p t l i n e on the PIA which i s r e l a y e d t o the nPU.
Figure 3. 6800 System. ACIA.,- Aeynohronoua communications interface adapter, which i s e e e e n t i e l l y a 8800 c o m p a t i b l e UART w i t h p r o g r m l n g c h a r a c t e r i s t i c s which ere comparable to those o f the PIA. LSR- Low mpeed modem p ~ o v i d l n g the necessary modul a t i o n , demodulation end s u p e r v i s o r y c o n t r o l f u n c t i o n s to implement a e e r l e l data communlcmtlons l l n k . Toshiba TLC~-~2- Shown i n Figure 4, t h i s system p r o r i d e s m 1 2 - b i t p a r a l l e l p r o c e s s o r which i s m i c r o p r o grmmeble~ Namean i n t e r n a l l y generated c l o c k and a p o w e r f u l i n t e r r u p t structure. The system else feer u r a l m s t r o n g f a m i l y of p a r t s and reasonably s o p h i s t i c a t e d c o n t r o l schemes For s i n g l e s t e p , debug and e x a m i n a t i o n o r memory l o c a t i o n s .
.
,~
~
davic~
Figure 4. TLSC-12 System. RAM- A 128x4 s t a t i c RAM i s 8 y e l l a b l e . BOM- A 512x8 meoked ROR end a uv PROM which are pin compatible ere a v a i l a b l e . MCU- Memory c o n t r o l u n i t i n t e r p r e t s end responds to the bus c o n t r o l eigneZe from the CPU end c o n t r o l s up t o 41( verde o f memory. OCU- I/O c o n t r o l u n i t responds to CPU bum s i g n a l s and c o n t r o l s I/O d e v i c e s . 80U- A 1 2 - b i t b i d i r e c t i o n a l bus d r i v e r . GIOR- G e n e r a l p u r p o a e r e g i s t e r t w i t h one word each f o r o u t p u t and i n p u t t 8 o r v i n 9 88 an interface between e x t e r n a l d e v i c e s and the common bus under the CPUes control. INTU- I n t e r ~ p t 1etch u n i t which generates p e r s i s t e n t IntAmrmpt r o q u l e t 8 from the transient i n t e r r u p t requests 8 u p p l i e d by I/O d e v i c e s o r o t h e r e x t e r n a l e venf41. SOFTWARE ELERENTS F o l l o w i n g the path of m i n i end m i x l - C o a p u t e r a , i t w o n l t be l o n g b e f o r e ~ e o f t w m r e ' c o e t e dwarf h e , d mira c o m t e . . Since ~-pe ere in m t r e n e l t o t y hardware s t a g e , the h i ? d e a r s and s o f t w a r e c o a t i ere p r o b a b l y me n e a r l y equal amw~be they ever w111 be. C o n c e n t r a t Ing on p o t e n t i a l s o f t w a r e problems I n the b e g i n n i n g o f B-P usage w i l l n o t m l i a i n a t e a l l o f them, but can
result in s severe curtailment of their effects downstream In the design cycle. Reny software problems can be elimlnated by managing software well t without any reel technical advances. Proper management requires recognition of potentlal problems end usa of organized programming methods such as structured progrsmmingt top-down design, good documsntatlon, modular interface standards, and program compatibility considerations. The cholce of a ~-p which executes tlme-tasted software will probably result in a substantial cost savings over a series of applications. Examples of such ~-ps are the Western Digital RP51600 which emulates the OEC POP-11 and the Intersil 5100 which emulates the OEC POP-Be Another alternatlve if a bipolar slice machlna is selected, is to emulate e known processor or st least a subset of a known procsssorts instruction set. Often times a good cholce for the known processor Is the minl-computer that is currently being used in house. The type of memory employed in a ~-p also has substantlel effects on software and the type of Inetructlons which are required. The selsction of ROM end RAM is going to effect the location of date and instructions. Whether the ~-p is a Harvard or Princeton type is not going to really matter, as RAM data must physically be located in • different place than ROM instructions. Raking usa of direct addrasslng f e a t u r e s , ss i n the Motorola 6800 s e r i e s , may r e quire the low order 256 words of memory to be RAM e~ that frequently accessed date can be placed here. This Is especially true If local store is limited or If many two oparend instructions, using e storage register and s memory word or Just two memory words, to hold the opsranda, ere available. ROM also does not allow instruction modlrlcetlon at execution time, thus requiring inatructlona to load the program location counter with date in order to avoid long searches in determining responses to control words. Subroutining is also memory dependent. A convenient approach to subroutines is to place routines basic to the application i n fuse PROMs or masked ROMe. The remaining code which governs the flow of control end decision meklng, along with program or ¢un-tlme dependent routines, can be placed in uv PROMs or RARe A subatantlel number of headaches can be avoided In a l l ROR end PROR systems I? s u b r o u t i n e s are always c a l l e d i n d i r e c t l y v i e a Jump table. This table, along with other location sensitive r o u t i n e s such ms i n t e r r u p t s e r v i c e packages, can be stored In a small separate ROR or preferably PROM. Then if an error is Found only the smell ROM need be changed. Replacement routines For faulty ones can also be in this ROR or another "patch m ROM. The result Is that the meJorlty (gs~ or more) of the larger ROR which contalna the error, can be saved. Perhaps the overall kay words in software for ~-pe are simplicity and creetlvlty. Simplicity from the standpoint of the number of accumulators ( n o r m a l l y one), limited arithmetic capability and the large number of steps required to perform teaks which are often standard members of • mlnl-computerea Inetructlon met. Creativity ie r e q u i r e d in epplylng often non-oleeslcal Instructlon sate to perform the complete system eppllcetlont including such t r i v l m l tasks ms switch debounclng end teletype I/O routlnee. Also aiealngt From meet ~-p software, la m store houmm of "canned" or prewritten routinem. Inetructlon emk comperleone can be broken down i n t o areas concerning e d d ~ e e i n g t d e c l o i o n and cont r o l t I / 0 end d a t a m a n i p u l a t i o n s . The d a l i g n a r must be careful to look For exactly the instructions that
32
his task requires and remember that actual benchmark programs will probably have to be coded for valid comparisons. The addressing complexity often dictates whether or not an assembler is a must end how difficult debug may be. Some sort of indexing capability is a must with an index register being preferable for many tasks. The availability of internal status bits such as overflow, carries, etc~ along with the flexibility of the program counter influences the efficiency of the decision end control instructions. These points are extremely important in using interrupt and I/O capabilities.
With I/O c a p a b i l i t y varying greatly in tL-ps, i t s use, along with the I/O load of an application, must be considered. Hardware support thru the parts fami l y can greatly enhance I/O c a p a b i l i t i e s and also eimplify system addressing problems for ROM, RAM, I/O devices and the like. A cumbersome addressing scheme, system wide, will greatly complicate ebftwere. The accumulator instructions, the number of accumulators, the number of secondary registers and the functions they perform are indicative of data manipulation capabilities. The availability of logical functions and multiple precision capabilities for the accumulators are quite important. Most ~-pe feature some sort of stack capability. It is important to note that these stacks are not used as local store and do not have accumulator capabilities, but rather are used for linkage and nesting of subroutines and interrupt routines. They ere push-down stacks used to store the current state of the machine i.e. program counter, internal status bits and local register contents, etc. when an interrupt strikes or a subroutine call is executed. The stacks are pushed or loaded with parameters at the beginning of a subroutine or interrupt routine, and popped, or unloaded, upon completion of the routine, thus returning the ~-p to its previous state. These stacks may be "hard", i.e. contained in the l~-p chip itself, or "soft", i.s. contained in the system memory, in which case some ~AM is required. Herd stacks ere also limited in depth, and either way, hard or soft, stack depth and overflow conditions must often be accounted for in software and require a varying amount of overhead. Interrupts are currently fairly undeveloped in ~-ps and usable at a substantially high cost in time, hardware end overall complexity. Generally no machine internal interrupts are available and masking of individual interrupts, or in some cases all interrupts, may not be possible. Microprogramming in ~-pe is e powerful but high risk technology. It is powerful due to the capability to "tune" instruction sets for a particular application, thus realizing increased efficiency over the use of general instruction sets. It is dangerous due to the lack of software support and the development time associated with coding and producing the often required masked ROMs. The debugging tools such as s microessembler and temporary RAM must be available. This is often not the case. Also any software available for the ~-p, probably will not run on the tuned version in a reliable fashion. The failure of manufacturers, especially in the bipolar slice architectures, to support a standard or "fall back" instruction set leaves the user on his own to design e new machine with little or no software or hardware support. These problems may be overcome but their solution requires indepth planning and a complete design cycle, rather than purchasing a supported, ready-to-use ~-p. Software support in the form of assemblers,
l o a d e r e p debug e d i t o r s , s i m u l a t o r s and h i g h l e v e l languages are a v a i l a b l e i n v a r i e d ? o ~ s f o r ~ - p s . Any lL-p which l e to be used i n a l i m i t e d q u a n t i t y should be u s a b l e with as little support as possible. For a four-bit ~-p this implies use without an assembler or formal loader. For most elght-blt or larger ~-ps some form of a loader along with an assembler and debug monitor ere usually needed. Assemblers of three types are normally available for ~-ps. The first is a self assembler which rune on the ~-p system itself. This type of assembler works well for slght-bit or larger machines, but is usually not too well suited to a four-biffs more llmited capability. Either way a self assembler will require a minimum memory configuration which may or may not match the system configuration and some type of I/O devices which again may not match the system. Self assemblers are also normally limited in capsbility with regards to documentstlon, sophisticated pseudo-ope, and other programming aids. More powerful assemblers ere cross assemblers, meaning that they assemble code for the ~-p on a larger host machine. This usually requires the availability of a mini-computer or larger machine capable of running e high level language, normally fortran IV, or the use of a timesharing service. Text editors, extensive comment, and documentation facilities are normally incorporated into such systems. An important capability of a cross assembler is the production of a compatible output form for the ~-p system. A magnetic tape, for instance, may not be of much use for loading s ~t-p system. Macro capabilities are also easily incorporated into e cross assembler. A good system macro library end the availability of a user macro library allows the programmer to build up a store of "tools n to use in software development. Sophisticated macro assemblers often begin to approximate high level languages and may have as much capability as is needed for the majority of ~-p software development ~fforts. Loaders, debug editors, or monitors and peripheral driver routines are also needed in ~-p software development. The loader may be s standard start-up program in firmware or s software routine used exclusively for loading programs. Either way they must both be compatible with the media used to transcribe programs into memory end should support some type of error control such as a check sum on a paper tape. Oebug editors or monitors should field interrupts~ communicate with some peripherals t provide break point capabilities and supply data on what the ~-p is doing. Without such e tool the ~-p may wander aimlessly due to errors or execute e program correctly, unknown to the designer, because no I/O was completed due to another error. Peripheral driver routines ere of obvious value in communicating with the ~-p while getting s system online. Simulators for ~ p s end high level languages ere also available and useful at times. A simulator facilitates at least a gross debugging of program code before it is placed on the ~-p system. While simulation will usually not show up problems related to timing end device interfaces, it will help eliminate slot of general problems end bookkeeping type errors in an environment which has much better software support end more debugging aids than the actual system. The only high level language currently available is Intel's PL/M which is much like PL/I in its constructs and nomenclature. PL/M clearly facilitates documentation and ease of program unde~standing while speeding up general problem coding.
33
While PL/R he• •eme c a p a b i l i t i e s i n h a n d l i n g t i m i n g dependent p r o b l e m s , q u e s t i o n s o? r u n - t i m e and o v e r 811 e f f i c i e n c y Dan be debated f o r h o u r s . Also o n e ' s r e c o u r s e i f 8 program, which I s t i m i n g d e p e n d e n t , does n o t run f•st enough t I s n o t c l e a r . High l e v e l language usage i n U p e can y i e l d some v e r y sucess? u l r e • u l t 8 b u t can alms l e a d t o d i s a s t e r . The deo l • l o n on high l e v e l languages i s system dependent end oonfllctlng vlewm on Its usage will probably n o t be r e s o l v e d f o r s o m e time t o come. SYSTER DEVELOPMENT Debugging 8 •yetem with 8 ~-p can either be dellghtful or nlghtmmrl•h. Prior thought, in the beginning of •yatam design, end the number of debugging a i d e s v m i l • b l a t w i l l d e t e r m i n e t h e speed •nd ease with which thla reek I• •ccompllshed. This section discus•am •ome of the t o o l • f o r debugging and p r a t e typing •y•tems which 8re c u r r e n t l y a v a i l a b l e , along with strategies for developing in house systems. Proper choice in selection of such tools and systems to supplement a ~-p w i l l n o t o n l y speed system d e v e l o p m e n t , b u t can a l s o run up d e v e l o p m e n t a l c o s t s c o n • l d • r • b l y i n the p r o c e s s . The • c r u e l c h o i c e s and declelon• made for • particular system a r e dlffIcult, but should be made wlth a great deal of conslderatlon. The f l r • t 8tap in debugging a system Is to bring the ~-p o n l i n e . To accomplish t h l e some p o l ar d e s i g n f e a t u r e s such •s • t a r t t s t b p , r e s e t and s i n g l e • t a p must b• a v a i l a b l e . Some t y p e o f m a i n t • n e n o • p a n e l I s r e q u i r e d which can d i s p l a y the program counter, data r e g l e t • r s , allow setting of bcamk points, and loading data i n t o the ~L-p, along with controlling Its •tatu•. On• such device for t h • I n t e l 4004 I s the Pro-Log R421 System A n a l y z e r . E s s e n t i a l l y m maintenance p a n e l on an u m b i l i c a l cord which c l i p • t o the ~ - p , the R421 f e a t u r e • tricing on a d d r • • s • s o r i n s t r u c t i o n s , reset, stopr u n , • l i e , and p r e s e n t program l o c a t i o n c o u n t e r t r a ce, whlch Is very h e l p f u l in debugging brenchlng I n 8 t r u c t l o n • , end i t s own power supplies. I n t e l also make• m s i m i l a r d e v i c e f o r the 4004 c e l l e d the PA404 Program A n a l y z e r . The PA4-04 has e s s e n t i a l l y the same capabilities ms t h e 421. I s o l a t i n g the U-p from i n t e r r u p t s and o t h e r e x t e r n a l proceeD•• a l l o w s c e n t e r i n g o f a t t e n t i o n on g e t t i n g t h e ~-p r u n n i n g . Careful consideration in d e s i g n o f • l g n m l o which a r e m o t i v e low ( f o r TTL), so t h a t I n unplugged o r e l • l i n g system component does n o t a c t i v a t e • s i g n a l i • q u i t e h e l p f u l h e r e . Once the g - p I s r u n n i n g much o f t h e system debuggi n g Den be completed w i t h i t s e l d . One o f the b e s t s i d e edvantege8 o f h a v i n g • g - p i n the system i s the a b i l i t y to run dlegnoetlo8 and debugging routines. Reaorle• ageln • • t e e the picture in program debugging m• anything but t r l v l a l programs require mNorlse which a:e a l t e r a b l e . C i H r l y Fuse l i n k PROMs and mukad ROMe are t o t a l l y uneulteblso While uv PRO~ ere a l t e r a b l e , debugging 8 large program in t h l • type or memory can be very tedious end t i m e consuming s i n c e t h e whole PROR must be erased end repcogremmed f o r • y e n s i n g l e e r r o r s . ROR simu l a t o r s c a n o v e r c o m e many o f these p r o b l e m s . A ROR s l m u l m t o r I s l i m p l y • BAR memory on an u m b i l i c a l c o l d w h i c h can. p l u g d i r e c t l y i n t o the PROM o r ROR s o c k e t • o f t h e system b e i n g debugged, thus s e r v i n g e • a o n e - f o ~ - o n e r e p l a c e m e n t f o r t h e m i s s i n g mamorle•. One much d e v i c e 1• t h e S c i e n t i f i c R l c r o System• IOOOA w h i c h c a n s i m u l a t e 651( b i t e o r ROR and has manual,
paper tap• and teletype I/O modem. Another feature o? the 1000A is a compatible assembler called RAPID. While t h i s assembler may not be any b e t t e r than another manufacturer's 88•ambler for • p a r t i c u l a r U-p, i t can bo used f o r almost a l l =-pc and is extremely useful ?or mlccocode development in b i p o l a r s l i c e or mlcroprogremmabla machines. RAPID l e e s s e n t i a l l y • general purpose assembler allowing the user to specify his own i n s t r u c t i o n format, mnemonics and op-codes. A device slmilac to the I000A, but l•so general in i t s a p p l i c • t l o n s , e l " though more sophisticated in other ways, is the PPS4RP designed by Applied Computing Technology and produced by Rockwell. The PPS-4MP is designed ?or use wlth the Rockwell PPS-4 system and can assemble and debug mlcroprograme, emulate RaRe, along with uses in system testing and prototyping. I t has a teletype with paper tape I / 0 option and allows assembly e i t h e r on the PPS-4RP i t s e l f , or on 8 larger machine or tlmeshara terminal. Other "debuggers" are the MCS-4 by Electronic Components and the Oxy Metal Industries COOB and COBO. Theee devices serve as replacements for the user's ~-p by plugging i n t o the system prototype in place of the actual ~-p chip. This allows the user to debug on actual prototype or system hardware, while having many features f o r debugging aid at his disposal. The RCS-4 emulates or replaces the Intel 4004 end some of Its associated components. It features 8 RAM memory, accee• to all simulated registers, a built-l• tape reader, break point capability, and ham a standby battery power supply for field use. The CDOB and CD80 •re the same general type of device but replace the In,el BOOB and B080, respectively. They provide start, stop, continue, break points, hexideclmal and binary displays, execution time camparS•one between two program locations, teletype and paper punch I/0 and ex•mlne and deposlt c•pabiliflee to all processor registers and memory looatlens. By developing interface standards in hie system the user can often enjoy many of the comforts of "debugger" or "slmulator" units within his own hardware. Proper system partitioning allow8 Functional substltutlon of memories between prototyplng systems and fielded systems. An I/O device of 80me sort may else b• placed in the system for debug purpos•o and then be deleted before fielding, thru such a •t•nd•rd. What•vet the system cho•en, compatible media with support eoftw•c• and the capabilities for permanent r e c o r d s and program l i s t i n g s a r e u s e f u l . A key p i e c e o f equipment I s the PROM progr•mmer. Many are available, with varied features, but the b•81o type8 are 81mpla, push button, hand entry devices, complete programming eta,lone, and pcogr•mming boards which •re addltlonm to complete table top ~-1~s or mlnl-computer8 in the form of I/O boards. Almost •vary memory manufacturer makes at least • hand entry type programmer. Low in cost, but prone to "human errors", they 1•ok hard copy and often only program 8 limited number o? memory types. It ie important to remember that most PROMs program differently in both timing r•qulr•m•nts and voltage level•. Varied programming tlme requires an " i n t e l l Igent" programmer I f PROM• are to be programmed in volume and •t reasonable rates. A somewhat general purpose hand programmer is made by Spectrum Dynamlo8 and employs • "personality card = system to ?•oilltate programming o? different types of fuse llnk PRORo. Pro-Loglo R810 Is • more sophisticated device which programs the Intel 1702A from either a keyboard or a "copy" PROM. It •leo
34
features a teletype interfacep paper tape reader and a built-in uv light for erasing PROMs. Some of its functional capabilities include list, program, duplicate, verify and check erase. Probably the most versatile line of programmers is offered by Data I/O. Their programmers will handle all technologies of PROMs and almost any manufacturer's device, regardless of pin configurations, etc. thru the use of personality cards. A wide range of features, depending on the particular model, are included. Some of these are paper taps readers and punches, card readers with optical scannners, code converters, and simultaneous programming of uo to 16 PROMs. The last type of programmers are those which are additions to manufacturers "complete processors" usually as I/O cards. Examples are IntelVs MPT-03 programmer board which iF,effaces to its 4 and 8-bit processors~ and NationalVs IMP-16P/BO5, IMP-15L/B05 and IMP-8P/805 which interface to the IMP-15P, IMP-16L and IMP-8P respectively. This type of programmer is a nice addition to a system, if you already have the processor which it works with~ either way it allows usage of existing peripherals and debug features. In short, there are many PROM programmers, with many features, avallable. Some semi-mandatory features are replication, selected cell programming, and some sort of hard copy input and output. The designer should be careful to select memories which can be programmed by s single, simple programmer and in-house or in the field. Testing of u-ps remains a somewhat insolved problem. On the positive side, overall reliability for u-p systems is almost always higher than that of random logic systems simply due to the reduced number of interconnections involved. Most reliability models for system failure rates show that as the number of interconnections goes up the reIiability goes down and not just linearly (2). Also field experience seams to show that, at present~ the reliability of a ~z-p chip is the same as that of any other IC with the same number of pins (3). Even so thorough testing, which can be expensive, may be required as soma batches of LSI chips (not u-ps~ however) have exhibited failure rates cf 30 to 50% and the cost of removing s defective chip from a finished product is somewhere around $200 if it doesn't get into the field (4). If it does get into the field expenses can mount up sstromically. Three basic methods of testing ~-ps are CPU self tests, comparison testing, and stored response testing. CPU self testing consists of the ~-p executing a diagnostic routine from within its system environment. The diagnostic program is designed to exercise as many instructions as possible under worst case data and instruction sequence conditions. The tests are designed such that if the ,,-p correctly executes them the program flows to an end condition indicating a passing score. If not, the diagnostics indicate an error which may or may not be iocatable. Often location is not desired as the whole I,-p must be discarded anyway. Some shortcomings of this technique are: multiple errors may not be detected t the actual cause of failure may not be found~ the tests may be extremely long and without special hardware external environment conditions like interrupts cannot be teated. Comparison testing compares the outputs of a "good" or reference ~-p end the .,-p ;nder test. Both
~-pa execute instructions simultaneously and outputs are compared, hrnile this method works fairly well for MSI and highly structured LSI, ~-ps ere complicated enough that finding a reference may be difficult along with resolving problems as to whet failed, the test u-p, the reference u-p, o r the tester. Lastly the test procedure cannot be executed at data rates faster than the ~-p will respond to correctly. Stored response testing uses stored data for ell inputs and outputs of the ~-p under test. The stored data or truth table represents logic signals for avery clock cycle. The truth table is usually long and must be derived with computer aided simulation of the t,-p. Also abnormal sequences may be used to expose some failure mechanisms. Whatever the procedure, test derivation for a device whose "insides" is not completely known, end Is highly sequential in nature, is vary difficult if a high r a t e of test c o v e r a g e is desired. Two available testers which can handle ~-ps are the Macrodata MO-IO4M and the Fairchild Sentry 500. The MO-IO4M is essentially a microprogrammable multiprocsssor which runs diagnostic tests on the ~-p and does parameter checks. The Sentry 600 uses s reference ~-p thru simulation software to generate truth table-type tests. The tester then exercises the IL-p under test. While these testing methods check out the *,-p#s logical operation, parameter tasting (to check such things as forward and reverse currents) and dynamic testing (to establish time domain parameters such as rise and fall times and propagation delays) are also required in a thorough test met-up. Development of test equipment is costly and the purchase route can also be expensive. Furthermore functionally identical chips from different manufacturers test out differently and the samp chip in two different test set-ups may not produce entirely matching resulte. AVAILABLE p.-p SYSTEMS While the possibilities for ~-p designs beginning at the chip level have been discussed in detail, thus far two other options, buying from systems houses that build boards or other forms of low cost microcomputer systems and buying complete turn-key microcomputer systems have not. These types of purchases allow the user to for go the details of grappling with the individual l~-ps end rather are a proven design that usually incorporates some debugging features and allows for system expansion. This type of approach allows faster design of systems or can be used as a prototyping unit while specific special system hardware is being developed. For turn-key systems, lower priced and also somewhat lower performance mini-computer-like systems can be used immedletely with only software development required, and even much of the software may be available thru the manufacturer of the system. Certainly software development tools such as simulators end possibly high level languages should be available. The most popular u-ps for usage in these types of products are the Intel 4004, BOOB, and 8080 with a few employing the Rockwell PPS-4, various National devices (some of which are custom made for only a few manufacturers) or a TTL, MSI design. Among the leaders in system housa~ s e l l i n g products above the chip level and below turn-kay systems
35
are Pro--Log end C o n t r o l L o g i c . T h e i r products ere characteristic of whet is available thru other systems houses such as Applied Computing, Comstar, Date Architects, Digital Products, Dynamic Data Systems, Three Phoenix, and V e r i t e l along w i t h chip manufact u r e r s who n o r m a l l y s e l l boards s t some l e v e l . ProLog f e a t u r e s the PLS-400 f a m i l y o f l o g i c cards which ere b u i l t around I n , e l l s 4004 CPU and 4002 RAMs and 1702A PROMs. A minimum system c o n s i s t s of a s i n g l e card w i t h 1K bytes o f memory end 32 TTL I/0 lines. For expanded capability, s three card system contains 4K bytes of memory and 128 TTL I/0 lines. Also available from Pro-Log is the RPS-BO0 family of cards designed for date processing end built around the Intsl 8008. The family consists of three and five card systems. Both units include 256 bytes of uv PROM end 1K bytes of RAM data/ instruction memory. The memory can be e x p a n d e d t o 16K bytes. Pro-Log also offers other cards for both systems which include driver output, relay output, opts-isolator AC/OC input, and two trisc output cards, along with power supplies, connectors and card racks. In short they have e complete store of proven parts from which systems can be configured. Control Logic offers the M series and L series of u-p logic system cards. The M series is based around the Intel 8080 end the basic processor includes cards for the CPU, memory end I/O control logic and clocking, and a data bus/multiplexer. Memory cards include e 512 byte PROM, a 256 byte static RAM, a 1K byte static RAM or s 256 byte uv PROM option. Other suppurt cards for I/O include a device address decoder, priority interrupt control, bus port, latched output t teletype interface and a serial interface for various BAUD rates, parity and data formats. A full line of compatible packaging supplies is also available. The L series features an In,el 8008 and is much the same as the M series in components'and available functions. A somewhat universal development tool is Control Logic's "Stand-Alone Programmsr/Maintence Console" which interfaces wlth its M series parts. The console is e diagnostic tool which allows full maintenance panel control of the t~-p including break points on instructions after they have been executed a variable number of times, along with the ability to simulate I/0 devices and peripheral control systems thru input port switches. A Memory Module is also available for inserting diagnostic and device simulation PROMs for testing and maintenance operations. Among vendors offering turn-key or semi-turnkey systems are Process Computer Systems, MITS, Realizations Etudes Elsctroniquss, Oats Architects end Computer Products Company. Somewhat innovative is MITS I Altair 8800 which is a do-it-yourself kit using the In,el 8080. For around $50 more than the cost of a single 8080 the 8800 includes a power supply, case and associated circuitry, along with a proven design. Such e design kit may well catch on in universities, high schools, homes end other areas outside of the immediate electronics world. Process Computer Systems' 8080 based MicroPac BO is characteristic of turn-key or table top systems. It is a complete table topt chasis built processor with operator's panel, memory options up to 65K, TTL input and output ports, and a teletype interface as standard components. Also available
ere optional interfaces fo~ the Ann Arbor Design 3 CRT and k e y b o a r d , s Remex dual oassmtte tape system, h i g h speed paper tape reeder~ a 132 column C a n t r o n i c e l i n e p r i n t e r , v a r i o u s communications i n t e r f a c e s w i t h up t o 80K BAUO r a t e s , • two channel~ 1 2 - b i t , D/A c o n v e r t e r and a 15 channel, 1 2 - b i t t A/D convemtar along wlth DC excited transformer controllers. A complete l i n e o f standard s o f t w a r e i n c l u d e s a basi c o p e r a t i n g system, s t a n d - a l o n e microaseemblar, i n t e r a c t i v e debug r o u t i n e , program t r a c i n g and t r a c k i n g t o o l s , t e x t e d i t o r s , and hardware d i a g n o s t i c s " to e x e r c i s e the memory, CPU module and c o n t r o l panel functions. Other a v a i l a b l e tL-p based p r o d u c t s are i n d u s t r i a l c o n t r o l l e r s . Examplesof these are the Struthers-Ounn SD-77, FX Systemst Series MC and RCA, along with the Controlpec 600. TTL, RSI designs, employed by D i g i t a l Equipment Company, D i g i t a l Labs, fsbri-Tek, Rlcrodete, Standard Logic and others, look much l i k e ~-p based systems at the board level and are competively priced. Someof these components are also faster than ,-p systems end have more extensive processing capabilities, along with supporting languages such as Fortran end Basic. Lastly the table top and board level designer offered by Intel, Motorola, National, Rockvell and other chip producers, have not been described here in detail. Virtually all of the chip producers either market such devices or have some type of plans in this direction. I / 0 ANO PERIPHERALS ~nile ~-ps show the tremendous amount of prograss, in both design end fabrlcetlon, that has been made in electronics; no real counterpart to this achievement exists in the area of peripherals. This implies that peripherals and I / 0 interfaces are going to cost much more than the processor in most system development e f f o r t s . Such i s the case, as many I/O f e a t u r e s which are h i g h l y acclaimed by manu f a c t u r e r s , show up q u i t e d i f f e r e n t l y when I/O i s actually done. Special interface parts are sometimes only elght-bit latches. Addressing of peripheral devlces normally invalves the use of an 8, 12, or 16-bit register which provides capabilities for selecting among 256, 4095 or 55~536 different devices. Many of the claims for I/0 interface ease depend on such tricks es using each bit of the device select register as the address for a specific I/O channel. Such schemes eliminate the address decoding logic end most of the cabling which goes slang with I/O bound systems; thus making the interface appear much simpler then it really is. Claims of interfacing ease should be substantiated by close scrutiny of the addressing end control schemes for a system. Systems which eliminate I/O instructions by using normal memory cells as special locations seem to be about the best bet at the present time. Such e scheme, as used in the Motorola 6800 series, allows I/0 to use normal LOAO and STORE instructions with peripheral control end date registers appearing as adjacent memory locations. This places the majority of the problem in hardware, which is the part of the system design process that seems to currently be best in hand. Along with this, a flexible addressing scheme for the system is needed. Then either RSl designs or special chips (such as those in the Rockwell PPS-4 family) can interface between the processor bus end the actual device. This allows designers
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and software strategies to worry only about processor and memory allocation with hardware taking up the translation problems. In the peripheral device area, a recent survey (5), showed that most applications require three or more peripherals or I/O devices. The popularity of devices, in order, were: numarlb display, 62%; keyboard, 49%; A/O or O/A converters, 39%; modem, 32%;
t e l e t y p e , 30%; CRT d i s p l a y , 27%; tape c a s s e t t e , 22%; paper tape r e a d e r , 20%; p l o t t e r or s t r i p r e c o r d e r , 11% and f l o p p y d i s c , 10%. Regardless of final system requirements, prototype or developmental stages require some sort of direct I/O with the processor. The selected device(a) should allow a common media such as paper tape or cards, etc. to be used with "hard" copy available. All efforts should be made to eliminate any changing o? media by hand. This type of incompatibility will cause many bookkeeping type errors. Also a little prior thought into a standard either in-house or for a system I/0 scheme will curtail many problems which might occur later on. The teletype provides most of the desired prototyping requirements for I/O devices. It does have the disadvantage o? being fairly slow in using paper tape. About a 20 to I or greater time savings can be achieved by switching over to a high speed tape reader and/or punch. First-infirst-out (FIFO) buffers also can ease the r-p's I/0 burden by taking up the rate or speed changes encountered in handling a teletype. Of course a printer is always nice but can begin to run up costs signlficantiy. Several interesting low cost, kit form psripheraIa are beginning to appear on the market. Southwest Technical Products a d v e r t i s e s ASCHII keyboards k i t s for $40 and RITS has plans for a disc d r i v e and c o n t r o l l e r along with a CRT u n i t and a 3 2 - c h a r a c t e r g a s - d i s c h a r g e d i s p l a y t e r m i n a l . Some o t h e r i n t e r e s t i n g low c o s t devices f o r use i n home systems have been proposed (6), such as using
TV sets end audio grade tape c a s s e t t e p l a y e r s . GETTING STARTED ECONOMICALLY Successful development of a i,-p system revolves around deciding if a u-p can do the task efficlantly and then how to get started quickly and get the iob done economically. The total cost of e system affects all ~ts parts and goes along way toward determining its success for b o t h t h e developer and user. While ~-ps enable designers to replace a large number of discrete devices and random logic with LSI, real cost savings is determined by the impact on the total system. For first-time usage of a particular P-p, development time will probably be longer (hence more costly) than a mini-computer based solution, due to absence of peripheral interfaces, software and documentation and customer support. A first-time, do-lt-yoursaIf development will probably require 500-2000 men hours and tie up some of e company's batter people. Using s basic proven design from a systems house and customizing it will require 4050% of this time. The price of the and product and • company's capabilities will, to a large extent, dictate whether to go from the ground up or Jump in up the line. If the developing company has electronics development facilities then ground up is fine. If these facilities are not available but the end product is not price sensitive then a systems house is probably the way to go. Other situations
will need some detailed consideration before deciding which way to go. Often mentioned savings when using ~-ps are lower chip insertion costs due to the increased capability par package size, along with reducing costs of repairing design errors end adding additional, user desired, options end features after initial design. It should also be noted that the costs of !.-ps end other LSI components should continue downward while other items such as fabrication, pc boards, power supplies, wiring, connectors, etc. are going upward and will probably continue to do so. Likewise the use of u-ps may mean getting a product to market sooner which can also increase savings and profits in an indirect manner. Regardless of cost t availability is the one parameter that must be investigated before going into production of a system contained a LL--p. Second sourcing of t~-ps is fairly limited and devices for other than commercial operating ranges are just beginning to appear. These facts along with the question of obtaining patents on systems, could make volume production s risky business. Field service, with ~-p based products, is simplified due to larger possibilities for standardization of parts and the ability to incorporate field changes often by simply changing memories and perhaps a jumper or two. Documentation is somewhat simpler as less hardware knowledge in the form of timing diagrams end schematics is required. Rather the same ~-p, if properly selected, may be used in several systems allowing maintenance men to learn one device and then use program listings, which ere usually much easier to follow than timing diagrams, for servicing needs. The least replac~ab]e parts unit in systems can also be made sufficiently larger. Other areas that cause costs of ~L-p designs to skyrocket include costs of PROM programmers, RUM simulators, peripherals, new expanded test facilities and the always lurking software costs. Software costs tend to coma in two forms. The first is the cost for support software, assemblers, compilers, and simulators, along with time to get them "up" on your system, along with the cost to use them. Support software can easily run $5000 and computer tim~ at $300/hour can get expensive fast. Reoccurring software costs due to new products, redesigns, etc. have really snowballed in system designs of the past. While there is no set solution to avoid these costs, prior planning and warning of the possibilities may allow at least partial solutions. It is important to remember that ~:-ps are driving logic designs to be programmable, which can be accomplished by either u-ps or other fle×ible types of logic design. The emphasis in system development is the creative use of hardware and software to yield cost-effective solutions to problems. ~-ps are, and will continue to be, a major factor in this type of development. REFERENCES I. 3.L. Ogdin, "Other Microcomputer Chips", Modern Dat.._._aa,February Ig75. 2. M.E. Hoff, Panel Oiscussion at 197=_.~4International Symposium on Fault-Tolerant Computing, June 1974. 3. E. Lea, Microprocessor Oesign Seminar, July 1974. 4. O. Gaudet, Electronic Enqlneerinq Times, July 1974. 5. 3. Neth and R. Forsberg, "Microprocessors and microcomputers: what will the future bring?", Electronic OesiQn News, November 1974. 6. 9. welabacksr, "A Practical, Low-Cost, Home/School Microprocessor System", Computer, August 1974.