Near-junction cooling for next-generation power electronics

Near-junction cooling for next-generation power electronics

International Communications in Heat and Mass Transfer 108 (2019) 104300 Contents lists available at ScienceDirect International Communications in H...

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International Communications in Heat and Mass Transfer 108 (2019) 104300

Contents lists available at ScienceDirect

International Communications in Heat and Mass Transfer journal homepage: www.elsevier.com/locate/ichmt

Near-junction cooling for next-generation power electronics Feng Zhou, Shailesh N. Joshi, Yanghe Liu, Ercan M. Dede



T

Toyota Research Institute of North America, 1555 Woodridge Avenue, Ann Arbor, MI 48105, USA

A R T I C LE I N FO

A B S T R A C T

Keywords: Embedded cooling Power electronics Microchannel flow Jet impingement

This article focuses on chip-scale single-phase cooling for high heat flux and high temperature power device operation. This technology is focused on future wide band-gap semiconductors, which are expected to survive harsh environments. To this end, strategies for near-junction cooling of vertical current power electronics devices are briefly reviewed, and two chip-scale coolers are experimentally investigated. Using single-phase water at an inlet temperature of 50 °C, a 40 mm × 20 mm straight microchannel (quantity 200, 38 μm × 313 μm) cooling chip is shown to dissipate up to 127.5 W/cm2 over a 1 cm2 area with a pressure drop of 40.2 kPa at 100 ml/min. A second 75% downsized 20 mm × 10 mm cooling chip based on a unique 500 μm × 500 μm unit cell microchannel plus jet impingement array architecture is then introduced. At the same inlet temperature and in single-phase operation, this chip-scale cooler is shown to dissipate up to 1.02 kW/cm2 over a 0.25 cm2 area. A maximum average heat transfer coefficient of 120.2 kW/m2K and a pressure drop of 81.2 kPa is further established at a 450 ml/min fluid flow rate. The unit cell jet impingement-based design is shown to additionally support average heater temperatures of 177.1 °C. Such technologies are anticipated to enable a 5-to-10-fold reduction in power package size when compared with traditional remote cooling strategies.

1. Introduction Traditional power electronics packaging employs silicon-based (Si) power semiconductor devices with a maximum temperature of 150 °C. Standard electronics packaging strategies consider a Si device, e.g. insulated gate bipolar transistor (IGBT), bonded to a substrate, which is usually mounted to a heat spreader [1]. Remote cooling is then adopted, where a thermal interface material (TIM) is interposed between the heat spreader and a cold plate [2]. This “remote” cooling package, Fig. 1(a), allows for correct electrical isolation and adequate heat transfer but tends to be bulky. Additionally, coefficient of thermal expansion effects and conductive thermal resistance are bottlenecks to performance improvement. Wide band-gap (WBG) devices such as silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) may operate at high temperatures, up to 300 °C, experience higher heat fluxes, up from 100–250 W/cm2 to 1 kW/cm2 [3–5], and utilize higher switching frequencies, which necessitates new packaging and cooling schemes. Embedded cooling is an innovation that exploits near-junction cooling in a highly compact form factor [6,7], and examples of cooling lateral current devices, e.g. gallium nitride (GaN) high electron-mobility transistor (HEMTs), with HEMT-level heat fluxes up to 30 kW/cm2 and die-level heat fluxes up to 1 kW/cm2 are found in [3]. In the



Corresponding author. E-mail address: [email protected] (E.M. Dede).

https://doi.org/10.1016/j.icheatmasstransfer.2019.104300

0735-1933/ © 2019 Elsevier Ltd. All rights reserved.

following paragraph, the most recent achievements in embedded cooling are reviewed. Researchers at Georgia Tech [8–11] designed and fabricated embedded micropin-fin heat sinks for three-dimensional (3-D) integrated circuit cooling. The heat sink has a two-layer structure, a Si wafer layer with an etched manifold pocket and a 1 cm × 1 cm array of staggered micropin-fins, and a glass layer which is bonded to the Si wafer to confine the coolant (deionized water). Heat fluxes up to 470 W/cm2 were applied to the 1 cm × 1 cm area of the embedded microfluidic heat sink, and the maximum heat transfer coefficient reached was 60 kW/m2K with the maximum pressure drop being up to 375 kPa for single-phase flow and 250 kPa for two-phase flow. IBM [12–16] has conducted extensive research on embedded two-phase cooling of large 3-D compatible chips. Radial expanding channels with embedded pin fins, which are suitable for through‑silicon-via (TSV) interconnects were adopted. Using R1234ze coolant, an average junction temperature of under 60 °C was maintained up to a heat flux of 350 W/cm2 with a pressure drop of around 300 kPa. Purdue University [17,18] fabricated and experimentally demonstrated a two-phase hierarchical manifold microchannel heat sink array for intrachip high-heat-flux dissipation. HFE-7100 was used as the working fluid to simultaneously dissipate background heat fluxes up to 450 W/cm2 and hotspot fluxes of greater than 2.5 kW/cm2 with the measured heat sink pressure drop of ~75 kPa

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reducing impact on the package electrical performance. Following the concept as shown in Fig. 1(d), the thermal-fluid performance of a straight microchannel chip-scale cooler was investigated by the authors [31]. A related concept with a 3D manifold microchannel structure and directly deposited heat source for power electronics application was studied by Stanford in collaboration with the authors [33,34]. Following the work reported in [31], the fabrication process for a more recent design based on a unique unit cell (UC) microchannel plus jet impingement architecture was explained in [32]. Thus, the contribution of this work is to report new experimental results for this second smaller chip design and provide a performance comparison with the straight microchannel chip-scale cooler. New singlephase thermal-fluid performance results at heat fluxes up to 1 kW/cm2, and average heat source device temperatures up to 177.1 °C, are highlighted. The manuscript is organized as follows. In Section 2, the straight microchannel and unit cell microchannel with jet impingement chipscale cooler designs are described; device fabrication is also reviewed. Experimental results are outlined in Section 3. A discussion is provided in Section 4, and conclusions are given in Section 5. 2. Device concepts and fabrication In this section, the design and fabrication of the straight microchannel cooling chip and unit cell microchannel with jet impingement chip-scale cooler is briefly described. Prototypes devices are built by leveraging both newly developed and established processes used in the fabrication of Si microelectromechanical (MEMS) systems. 2.1. Straight microchannel design The 40 mm × 20 mm straight microchannel cooling chip comprises 200 microchannels each with a 313 μm height, 38 μm width, and 12 mm length. Essentially, the flow enters the chip through an inlet port, passes through the parallel microchannels cooling the heat source, and exits the chip at an outlet port. The fabrication process is summarized in Fig. 2(a), where two 525 μm thick, 100 mm diameter Si wafers are used. Briefly, the microchannel structure is first etched in the backside of the first layer, while fluid inlet and outlet ports are etched through the second layer. The two wafers are then bonded together using a direct Si-to-Si fusion bond. A 12 mm × 12 mm titanium, nickel, gold (Ti/Ni/Au with respective 200/200/50 nm bottom-to-top thickness) metallization layer is then patterned on the top of the wafer stack prior to dicing. The cooled area of this device is intended to handle heat sources up to 1 cm2 in size similar to current Si IGBTs for traction drive systems. Extensive fabrication details for this structure are found in [31], a scanning electron microscope (SEM) image of the first layer of the final structure is provided in Fig. 2(b), and the fabricated chip with representative dimensions is shown in Fig. 2(c).

Fig. 1. Comparison of vertical current device power package concepts: (a) conventional package with remote cooling; (b) microchannels embedded in power device; (c) microchannels embedded in electrode; and (d) microchannels in separate chip-scale cooler. Note: figures not to scale.

and the average chip temperature being ~30 °C above the fluid inlet temperature. University of Maryland [19,20] adopted a similar manifold microchannel heat sink structure and R-245fa as the coolant, and was able to cool a SiC device of heat flux up to 1 kW/cm2 at ~85% exit vapor quality with a pressure drop up to 110 kPa. Additional work from other research institutes related to chip-scale cooling of electronics also exists, and the reader is referred to the literature for a comprehensive review [21–27]. Embedded cooling is a relatively new, high risk, high reward strategy for automotive power electronics applications, where vertical current devices are common due to a high breakdown voltage requirement and remote cooling still dominates the field [4,28]. With Si devices approaching their theoretical performance limit, wide band gap devices, e.g. GaN, SiC, etc., have evolved [29], and traditional remote cooling solutions are starting to become a limiting factor. Thus, direct cooling of vertical current devices is emerging, and early work by Vladimirova, et al. [30] focused on vertical power PIN diodes. Additionally, three proposed ideas for near-junction cooling of vertical current WBG power devices were proposed in [31] and are shown relative to the aforementioned remote cooling packaging strategy in Fig. 1. While embedding microchannels directly into the power device or lower electrode of the device, Fig. 1(b) and (c), respectively, is proposed, the attachment of a separate chip-scale cooler to the power device is examined here due to simplicity of micro-fabrication, as discussed in [32]. Additionally, the concept in Fig. 1(d) is possibly the most feasible in terms of minimizing power device modifications and

2.2. Unit cell microchannel with jet impingement design The second cooling chip design is targeted toward application to more compact, higher power density SiC MOSFETs. The 20 mm × 10 mm microchannel UC with jet impingement architecture consists of 144 units cells in a 12 × 12 array covering a 0.36 cm2 footprint area; each UC is 500 μm × 500 μm in footprint size. The microchannel layout in each UC is identical and based on prior singlephase conjugate heat transfer topology optimization numerical studies in [35]. The microchannels are 20–30 μm in width with a depth of 300 μm, while each jet orifice diameter is nominally 160 μm. Note that based on designed dimensions, the wetted fin surface area for this device is roughly 9% less than the wetted area for a similarly sized straight microchannel chip. Thus, primary differences in performance relate to the flow path. Essentially, the flow of liquid emanating from each nozzle empties into the center of each UC, flows radially outwards 2

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Fig. 2. Straight microchannel cooling chip: (a) overview of fabrication process for the 40 mm × 20 mm × 1.05 mm chip; (b) SEM image of the first layer of chip; (c) image of fabricated chip with representative dimensions; inset Section A-A shows typical microchannel cross-section dimensions, and the out-of-plane microchannel length (not shown) is 12 mm.

is then installed over and around the Si cooling chip edges to provide electrical connections between the power supply and the test chip. The Si thermal test chip is powered via a set of gold wires (ø25 μm) that are wire bonded (K&S 4123 Wire Bonder) between the thermal test chip and the PCB. The test section is then installed into the flow loop to conduct the experiments. The main components of the flow loop consist of the pump, flow meter, in-line heat exchanger, test section, condenser, and receiver. A brief description of the loop follows. The fluid is pumped from the receiver by a positive displacement pump (Micropump Series GA) to provide a range of fluid flow rates. The pump flow rate is measured and controlled by a Coriolis mass flow meter (Bronkhorst mini CORI-FLOW series, ± 0.1% of rate accuracy). The mass flow meter utilizes a proportional-integral-derivative controller ( ± 0.01%) to maintain a fixed flow rate through the test loop. An in-line heat exchanger is located downstream of the flow meter to control the temperature of the coolant entering the test section. The test section inlet temperature is measured and controlled ( ± 0.01 °C) using a resistance temperature detector (RTD) installed at the inlet of the test section. The RTD interfaces with the re-circulating chiller (Julabo A40). A 15 μm filter is installed prior to the test section to remove any contaminants that may enter and clog micro jets or channels. A condenser (i.e., Cu shell and tube heat exchanger), connected to a re-circulating chiller (Thermoflex 900), dissipates heat from the coolant, and maintains a constant temperature of 25 °C prior to entering the pump. The outlet coolant temperature is measured using a calibrated Type

and then is collected in the channels between the nozzle posts prior to flowing out of the chip. The three wafer fabrication process including novel double-sided etching techniques is summarized in Fig. 3(a), images of regions of the structure are provided in Fig. 3(b)-(d), and the fabricated chip with representative dimensions is shown in Fig. 3(e). Observe in Fig. 3(e) that a similar Ti/Ni/Au metallization layer of 6 mm × 6 mm size is deposited on top of the wafer stack. Complete fabrication process details for this cooling chip are found in [32]. 3. Experimental results The focus of this article is to provide new experimental results and comparisons between the two chip designs. Thus, a brief description of the experimental facility and the heat loss analysis is provided in this section. The experimental thermal-fluid results then follow. 3.1. Flow loop description The experimental test facility used to evaluate thermal-fluid performance of the Si cooling chip is shown schematically in Fig. 4 along with a zoomed view of the test section. The test section consists of a Si thermal test chip (TEA TTC-1001) solder bonded using a tin‑copper‑nickel (Sn-0.7Cu-0.06Ni) solder preform to the metallized pad of the chip-scale cooler, which is installed on a polyetheretherketone (PEEK) manifold, and then sealed around the edges using a silicone sealant to prevent leakage of the coolant. A printed circuit board (PCB) 3

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Fig. 3. Unit cell microchannel with jet impingement cooling chip: (a) overview of fabrication process for the 20 mm × 10 mm × 1.47 mm chip; (b) perspective SEM image of first layer of microchannel 500 μm × 500 μm unit cell array; (c) top SEM image of first layer microchannel units cells; the 20–30 μm wide microchannels have out-of-plane depth of 300 μm (not shown); (d) top optical microscope image of second layer of 160 μm diameter jet nozzles; (e) image of fabricated chip with representative dimensions.

range of 50–100 ml/min, in ~10 ml/min increments, are utilized for the straight microchannel cooling chip, while a flow rate range of 115–450 ml/min, in ~50 ml/min increments, is used for the unit cell microchannel with jet impingement cooler. Power to the thermal test chip, Qttc, is supplied in the range of 30–260 W, which covers the load conditions for both cooling chip designs. In tests where coolant volumetric flow rate is varied, a fixed power of Qttc = 70 W is applied to the heater for the straight microchannel cooling chip versus 75 W for the heater on the unit cell microchannel with jet impingement cooler. For experiments where the coolant flow rate is fixed and applied heater power is varied, a power increment of ~25 W is used. For each test case, at each set coolant flow rate, thermal-fluid measurements are made at a power level once steady-state thermal equilibrium is achieved. An IR image of the thermal test chip is then obtained to enable temperature averaging of the high resolution thermal contours of each heater. A list of the main experimental parameters is provided in Table 1. Representative thermal images from the two experimental setups are provided in Fig. 5. To process the heat transfer data, the heat loss (via conduction and convection) from the assembled chip is determined. The heat loss, Ql, is estimated by powering the thermal test chip at different power levels (without coolant flow) and measuring the corresponding thermal test chip average temperature, Tttc , via the IR camera; note that Tttc is taken as the spatial average of the thermal contours within each IR image shown in Fig. 5. A constant input power (i.e., 0.5 to 3.5 W in 0.5 W

K thermocouple (Omega Inc., ± 1.1° accuracy). The pressure drop of the test section is measured using a calibrated differential pressure transducer (OMEGA PX2300, 0–5 psi, ± 0.25% accuracy), which is installed between the inlet and the outlet pressure taps of the PEEK manifold. The wire bonded surface of the test chip is coated with a layer of flat black paint (ε ~ 0.96 − 0.98) for temperature measurement using a calibrated infrared (IR) camera (FLIR SC7650, ± 1 °C accuracy). The thermal test chip is powered via 100 V 14.4 A programmable DC power supply (B&K Precision XLN10014).

3.2. Experimental procedure and heat loss analysis For temperature measurements of the larger 10 mm × 10 mm thermal test chip bonded to the straight microchannel cooling chip, a 50 mm lens is mounted to the IR camera at a vertical working distance of ~25 cm with a field-of-view (FOV) of approximately 51 mm × 41 mm and spatial resolution of ~0.08 mm/pixel. For the smaller 5 mm × 5 mm thermal test chip attached to the UC microchannel with jet impingement cooling chip, the IR camera is reconfigured with a 1× close-up lens positioned at a ~30 cm working distance above the heater to provide an approximate overall FOV of 9.6 mm × 7.68 mm with a spatial resolution of ~0.015 mm/pixel. For the experiments, a constant inlet temperature of 50 °C is maintained, which is a value similar to a typical coolant inlet temperature for vehicle power electronics. Coolant volumetric flow rates in the 4

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Fig. 4. Flow loop schematic (left) with zoomed top view of the test section prior to wire bonding (right), where a 5 mm × 5 mm thermal test chip is bonded to the 20 mm × 10 mm cooling chip with PCB installed over the top. Table 1 List of main experimental parameters.

Table 2 Coefficients for heat loss estimation.

Parameter

Value

Cooling chip size

A

B

Inlet temperature, Tin Coolant volumetric flow rate, v̇, range (straight microchannel) Coolant volumetric flow rate, v̇, range (UC microchannel + jet impingement) Thermal test chip power, Qttc, range

50 °C 50–110 ml/min 115–450 ml/min

40 mm × 20 mm 20 mm × 10 mm

0.0472 0.0277

0.918 0.581

30–260 W

cooling chip designs. 3.3. Thermal-fluid performance

increments) is applied to all thermal test chip 1 mm × 1 mm resistive element heaters, which causes the temperature of the test section to increase linearly. At each power level after reaching steady state, the average temperature of the thermal test chip, Tttc , is recorded along with the power input to the chip from the DC power supply. A linear curve fit is then used to correlate the heat loss from the chip to the heater chip temperature and is given by (1),

Ql = A × Tttc − B,

For performance evaluation, the pressure drop, ΔP, across the device is measured directly using the differential pressure transducer, (2)

ΔP = Pin − Pout ,

as the difference between the inlet pressure, Pin, and the outlet pressure, Pout, of the test section. The pumping power, Qp, for the cooling chip is then

(1)

̇ P, Qp = v Δ

where the coefficients A and B vary depending on the cooling chip under test. Table 2 provides these coefficients for the two different

(3)

where v̇ is the measured fluid volumetric flow rate. Fig. 5. (a) Representative IR image of the 10 × 10 mm2 thermal test chip for the straight microchannel cooling chip at 127.5 W/cm2 heat flux and 100 ml/min coolant flow rate; (b) IR image of the 5 × 5 mm2 thermal test chip for the UC microchannel with jet impingement cooling chip at 144.2 W/cm2 heat flux and 115 ml/min coolant flow rate. Note: in both cases, the global coolant flow direction across the cooling chip is from bottom to top, as shown in each side schematic; also, each IR image indicates the spatial region for temperature averaging.

5

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Table 3 Measurement accuracy and ranges for uncertainty analysis. Parameter

Accuracy ( ± )

Flow rate, v̇ Pressure drop, ΔP Thermal test chip temperature, Tttc Fluid inlet temperature, Tin Solder thickness range, tTIM Thermal test chip power, Qttc

0.01% 0.25% 1 °C 0.01 °C 10 μm 0.9%

Fig. 6. Electrical resistance analogy for the assembly of the thermal test chip to the Si cooling chip.

overall uncertainty range for the average heat transfer coefficient, Uh , for the straight microchannel cooling chip is ± 9–16% versus ± 3–6% for the unit cell microchannel with jet impingement cooling chip. The lower uncertainty in h for the unit cell microchannel with jet impingement cooling chip is due to 4–14× higher applied heat fluxes and larger measured ΔT values thus reducing the effect of various measurement accuracies. The uncertainty in the pumping power, UQp, for both cooling chips is quite low at ± 0.3%.

The power, Qd, dissipated by the cooling chip is determined as follows

Qd = Qttc − Ql ,

(4)

where Qttc is the applied thermal test chip heater power measured via a sense line at the power supply, and Ql is found by (1). Following [36], the total thermal resistance, Rthtot, of the assembled cooling chip plus thermal test chip is then

Rthtot =

Tttc − Tin , Qd

3.5. Experimental results (5) The measured flow rate versus pressure drop, using (2), for the straight microchannel cooling chip and unit cell microchannel with jet impingement cooler is shown in Fig. 7. Both data sets are curve fit by a second-order polynomial with a minimum R-squared value of 0.999; note that the R-squared value or correlation coefficient is a measure of how well the curve fit represents the experimental data. The maximum measured pressure drop for the straight microchannel cooling chip in this data set is 39.8 kPa at a 95 ml/min flow rate. For the unit cell microchannel with jet impingement cooler, a maximum pressure drop of 81.2 kPa was recorded at a flow rate of 450 ml/min. Observe in Fig. 7 that for an equivalent pressure drop (e.g. 40 kPa, as highlighted by the red dashed lines) the achievable flow rate through the unit cell microchannel with jet impingement cooling chip is approximately 3× higher. This lower flow resistance is by design [35] and due to parallel fluid flow though the jet orifice array followed by a shorter flow path through the microchannel unit cells. Conversely, by extrapolating the pressure drop curves in Fig. 7, at a constant volumetric flow rate the pressure drop for the straight microchannel cooling chip is significantly higher than the pressure drop for the unit cell microchannel with jet impingement design. The measured heat transfer coefficient, calculated using (10), as a

where Tttc is the measured surface temperature of the thermal test chip, and Tin is the coolant inlet reference temperature. The total thermal resistance in (5) is the summation of the conduction thermal resistances of the thermal test chip, Rthttc, and TIM layer, RthTIM, plus the convection thermal resistance, Rthcnv, of the chipscale cooler as shown using the electrical resistance analogy in Fig. 6,

Rthtot = Rthttc + RthTIM + Rthcnv .

(6)

Here, the conduction resistances of the thermal test chip and TIM layer may be expressed as

Rthttc =

tttc ,and Attc kttc

(7)

RthTIM =

tTIM , ATIM kTIM

(8)

respectively. In (7), tttc, Attc, and kttc are, respectively, the thickness, footprint area, and thermal conductivity of the thermal test chip, which are well known based on the specifications of the heater chip and independent measurements. The thickness, footprint area, and thermal conductivity of the solder layer are tTIM, ATIM, and kTIM, respectively, in (8). Based on the solder material composition, kTIM is found, and tTIM is independently measured by cross-sectioning a representative assembly, polishing, and measuring the solder thickness by SEM. Finally, simply rearranging (6), we obtain the convection thermal resistance of the cooling chip as

Rthcnv = Rthtot − Rthttc − RthTIM .

(9)

Following [36], (9) may be used to obtain the average convection heat transfer coefficient, h , of the chip-scale cooler device,

h =

1 , As Rthcnv

(10)

where As is the actively cooled planar interface surface area between the chip-scale cooler and the remainder of the package. 3.4. Uncertainty analysis The uncertainty in the derived quantities is found based on a standard uncertainty analysis [37]. The solder TIM thickness variation (quantified by SEM) is a primary contributor to the overall uncertainty in the average convection heat transfer coefficient. Table 3 summarizes the accuracy of relevant instruments and physical measurements. The

Fig. 7. Measured pressure drop as a function of flow rate. 6

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Fig. 9. Unit cell microchannel with jet impingement chip-scale cooler measured average device temperature and pressure drop as a function of heat flux. Note: coolant flow rate is 300 ml/min with Tin = 50 ° C.

Fig. 8. Measured heat transfer coefficient as a function of pump power.

function of pump power, determined using (3), is plotted in Fig. 8 with a minimum curve fit R-squared value of 0.983 for both data sets. The error bars in this figure reflect the prior heat loss and uncertainty analysis. The maximum measured average heat transfer coefficient for the straight microchannel cooling chip is 62.78 kW/m2K at a 95 ml/min coolant flow rate and a 67.8 W/cm2 heat flux. For the unit cell microchannel with jet impingement cooling chip, the maximum measured average heat transfer coefficient is 120.2 kW/m2K at a 450 ml/min coolant rate and a 293.4 W/cm2 heat flux. In Fig. 8, it is shown that the unit cell microchannel with jet impingement cooling chip design is more efficient than the straight microchannel design for the same value of pumping power. A separate set of experiments was conducted to examine thermalfluid single-phase performance in a constant pressure drop system. The pressure drop in each case was fixed to an approximate value of 40 kPa by adjusting the coolant flow rate, and the applied heat flux was then increased. Since the unit cell microchannel with jet impingement design has higher cooling performance, it was taken to much higher applied heat flux values to challenge the 1 kW/cm2 target. The straight microchannel cooling chip was tested up to a maximum heat flux of 127.5 W/ cm2 at a coolant flow rate of 100 ml/min. The measured pressure drop for this test was 40.2 kPa, and the calculated average heat transfer coefficient is 65.91 kW/m2K. For the unit cell microchannel with jet impingement cooling chip, the additional experiments were performed at a fixed flow rate of 300 ml/min. The average chip temperature as a function of the applied heat flux is shown in Fig. 9. Plotted on the secondary vertical axis is the measured pressure drop. Here, the maximum applied heat flux is 1.02 kW/cm2 with an average thermal test chip temperature of 177.1 °C and a measured pressure drop of 41.2 kPa.

Fig. 10. Comparison of 1 kW, 400 V buck converter power packaging using a traditional remote cooling approach for TO-247 packaged Si power devices (upper image) versus a representative module under development with chipscale cooling of SiC bare dies (lower image).

capacitor technologies. Through further packaging optimization, including possible heterogeneous integration [3,6,27], eventual 10-fold reduction over traditional packaging strategies may be realized. 5. Conclusions In this article, chip-scale cooling was covered for high heat flux and high temperature operation power electronics. Two chip-scale cooling devices were introduced including a straight microchannel cooler and a unit cell microchannel with jet impingement cooling structure. The following main conclusions are drawn.

4. Discussion The test section assembly comprising the thermal test chip bonded to the chip-scale cooler closely resembles the packaging concept proposed in Fig. 1(d). Through this work, it is shown that the near-junction cooling device concept can support high temperature, > 150 ° C, power device operation at high heat fluxes up to 1 kW/cm2 in a simple singlephase cooling loop. Future challenges to realization of this concept for practical power conversion applications include successful integration of the chip-scale cooling devices into functional electronics packages. Ongoing work, as shown in Fig. 10, is focused on this integration, where ~5× higher buck converter module power density is estimated to be immediately feasible through the adoption of chip-scale cooling devices, custom flow manifolding, a planar inductor, and downsized

• Both chip-scale cooling devices were successfully fabricated using Si MEMS processes. • Thermal-fluid testing was performed for each device and revealed • 7

higher performance for the unit cell microchannel with jet impingement cooling chip design due to the arrayed jet orifices and shorter flow length through the microchannel unit cells. The cooling of heat fluxes up to 1 kW/cm2 in single-phase operation with modest pressure drop and pumping power was shown to be

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feasible for 0.25 cm2 bare dies, which is relevant for future SiC power semiconductor devices.

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