Power consumption estimation using statistical signal properties

Power consumption estimation using statistical signal properties

MJcroprocessingand Microprogramrning35 (1992) 691-696 North-Holland 691 Powe~ConsumpfionEstimafion!t~ngStat~dcalSicnRIProperlies Wolfgang ROETHIG, E...

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MJcroprocessingand Microprogramrning35 (1992) 691-696 North-Holland


Powe~ConsumpfionEstimafion!t~ngStat~dcalSicnRIProperlies Wolfgang ROETHIG, Elmar MELCHER, Sami CHAKROUN, and Michel DANA TELECOM Paris University, Electronics Departement, 46 rue Barranlt, 75013 Paris, France This paper describes a new method for mean power consumption estm~ation in digital circuits, based on logic activity and probability. Probahilistic event parameters are calculated for all nodes by propagation of statistical input event parameters through the circuit using booleanprobabilistic transfer fimctions and gate del~y. Results from benchmark circuits show the accm'acy of our model and the gain of CPU time compared to logic simulation.

L Introduction Predicting the power consl~mption of an integrated circuit, along v;ith predicting the speed performance, is becoming a more and more important objective in circuit design. The term power eon91tmption covers two aspects that need to be clearly distinguished: instanta~esus power consumption ]inked to the peak curr,mt aud average power consumption linked to meaL, current. Many power estimators are focused on peak current which is important for noise and electromigration [1], [2], [3]. On the other hand, mean current is a criterion for rentability and feasibility, since it provides information about heat dissipation and determines thus the choice of the package. This paper presents a new method optimized for m e a n power e s t i m a t i o n . There are few a l t e r n a t i v e s to determine the mean power consumption in a circuit. Many designers simply use the number of transistors to evaluate it. This method is fast but very unreliable. The alternative method, using an electrical simnlater such as SPICE applying all possible i n p u t transitions to the circuit gives accurate results, but this method is not viable for large circuits, since the number of possible input patterns grows exponentially with the number of primary inputs. We propose a method that overcomes the complexity problem: instead of a large number of i n p u t patterns, a small set of parameters

con~.aining statistical information about all possible input patterns, is propagated from the primary inputs through the circuit. These parameters characterize each node by its mean number of logical transitions and its probability to be at logic high (respectively low) level. Our method is technology-independent, since it deals only with logical aspects. Statistical signal properties for circuit analysis have been used successfully in the domains of testing [4] and reliability [5]. An experimental version of the method has been i~,~plemented in LISP. It works with circuits con~iuing only combinational logic and accepts a netli~t described in a subset of VHDL. Section IT links logic behavior and electrical power consu~ption; Section III gives definitions and properties o~? statistical events; Section IV describes the calculation of event parameters within our model, which are the bases for calculation of power consumption as shown in section V. Section VI gives experimental results.

ELDy.~mlq and Static P o w ~ Consmaption In any technology, the power coilsumption can be expressed as the sum of the following terms: 1 • Vdd* Vdd"

~ ( I u + ID) ° act all nodes


~ IH* p + IL* (lop) all nodes



W. ROth~J et at.

IIL Sta ~ical D~mm~iption of a Signal

where Vdd p(node)

power supply voltage probability of t h e node to be in logic "high" state act(node) logic activity of the node IH(nodel m e a n c u r r e n t flowing through t h e power supply terminal of the driving gate, the node being in logic "high" state IL(nede) m e a n c u r r e n t flowing t h r o u g h the power supply terminal of the of the driving gate, the node being in logic "low" state ]U(node) c u r r e n t flowing through t h e power supply t e r m i n a l of the driving gate, when t h e node changes from logic "low" to logic "high" state (going "up") ID(node) c u r r e n t flowing through the power supply terminal of the driving gate, w h e n t h e node changes from logic "high" to logic "low" s t a t e (going "down") (1) represents the dynamic, (2) the static power consumption. I n technologies w i t h multiple power supplies, such as GaAs DCFL and SBFL [6], there is a s u m of corresponding terms. I n CMOS [2], s t a t i c consumption can be neglected. Dynamic consumption can be obtained from I U = C(node) * FClock * Vdd




where C(node) equivalent node capacitance FClock clock frequency I f more accuracy is required, look-up tables with precharacterized values for I U and ID can be used instead of(3). In NMOS and GaAs, I L is the dominant term for static power consumption [6].

The concept of state probabilities has become popular in test coverage evaluation [4], [5]. It is easy to propagate these probabilities from input nodes to output nodes using the circuit topology as long as there is no redundancy. However, the state probability alone gives no information about the number of occurring transitions. Let us consider a combinational circuit driven by registers working a t frequency F. In a first step, only ,~he functional aspect will be taken into account, neglecting the delays in the circuit. Thus, only one logic transition can occur per node and per clock period T = ~. Each node of the circuit can be in either of the following states: H: logic high level, L: logic low level. So let us introduce two node parameters: pu: probability that the node "goes up", i. e. changes from L to H during a period, a s s u m i n g t h a t it w a s a t L at t h e beginning of the period. pd: probability that the node "goes down", i. e. changes from H to L during a period, a s s u m i n g t h a t it w a s a t H at t h e beginning of the period. The probability of the node to be at H at the end of the nth period, p(n), can be expressed as p(n) ffip(n-1) (1-pd) + (1-p(n-1)) pu (4) As pu and pd are constant, (4) can be reduced to u]~__ + (p(0) - p~u + p d ) (1-pu-pd) n p(n) -_ _pu+pd


In a physical interpretation, the first t e r m is the stationary probability, since the second term can be neglected for big values of n, if l>pu>0 and l>pd>0. The stationary probability p can also be o b t a i n e d directly f r o m (4) by a s s u m i n g p(n) = p(n-1) = p: pu p=(1-pd)p + (1-p)pu <=> p = pu+pd (b'b) An indicator for the node activity can be defined, representing the average number of transitions: act = p p d + ( 1 - p ) p u



using (Sb) we get: 2pu pd act = pu+pd



P l = puN (1 - PN) + (1 - pdN) PN P2 = p u l (1 - Pl) + (1 - p d l ) P l (8)

Please note that the two parameters pu and pd cannot be reduced to a single parameter which would represent the activity without taking care of the logic state. The activity is independent of the logic state only when z

pN ffiprON.1 (1 - pN-1) + (1 - pdN-1) PN-1

The two variables pu and pd are sufficient to characterize the stationary behavior of a node. We prefer t h e m to the two variables p and act because they can be propagated more easily. Multiple transitions, due to different delay paths within a combinational circuit, are not taken into account by this first model. The constraint of only one transition per clock period and per node will be released in the following section.

We define for a gate with inputs a k and output y and for i in {1,2,3, ..., n): pui(ak) probability t h a t the k-th input node changes from L to H a t the be~nn~ng of the interval li, assuming that i t was in the state L pdi(ak) probability t h a t the k-th input node changes from H to L at the b e g ~ = ~ g o£ the interval Ii, assuming that it was in the state H pui(y) probability t h a t t h e o u t p u t node changes from L to H at the beginning of the interval Ii, assuming t h a t it was in the state L pdi(y) probability t h a t t h e output node changes from H to L at the beglnm'ug of the interval Ii, assuming that it was in the state H A s s u m i n g a m u l t i p l e - u n i t d e l a y g, t h e parameters pui(y) and pdi(y) of the outputs can be calculated from the p a r a m e t e r s pui-g ( o k ) , pdi-~ ( o k ) and Pi-~ ( a k ) of the inputs u s i n g boolean-probabilistic transfer ftmstions deri-~d from the boolean function of the gate. The transfer functions (ga,b,c) of a NAND gate for example can be derived from table 1.

IV. P r o b a b f l i ~ c Event Model 1

A clock period T = ~ is divided into N intervals I1, I2, .. I N . The nodes can m a k e a transition from H to L or from L to H at the beginning of each interval. Hence the m a x i m a l number of possible transitions per node and per clock period is N. For each node, we introduce 3N parameters: pui for i in (1,2,3 . . . . . N) the probability that the node changes from L to H at the beginning of the interval Ii, aseuming that it was in the state L. pdi for i in (1,2,3 . . . . . N) the probability that the node changes from H to L at the beginning of the interval Ii, assuming that it was in the state H. Pi for i in (1,2,3, . . . , N) the probability of the node to be in the state H before the beginning of the interval Ii. Let us consider an arbitrary node in the circuit. Assuming stationarity, the Pi of the node can easily be d e r i v e d f r o m i t s p u i a n d pdi parameters, resolving the following system:

In our model, the delay of each logic gate is expressed as a number of intervals.

transition from to sbysby L L H ~I H L L H H ~I H L ~I L H ~ I H L H L L, L H H L LHH H L [-I L H

probability (1-p(a))pu(a)(l-p(b)) pu(b) (1.p(a))pu(a)p(b)(l-pd(b)) p(a)(1-pd(a))(1-p(b))pu(b) p(a) pd(a) p(b) pd(b) p(a) pd(a) p(b) (1-pal(b)) p(a) (1-pal(a)) p(b) pd(b)

Table 1: transition probabilities of a NAND gate


W. R~thig et al.

pu(y) = p(n) pal(a) p(b) _pd(b) + p(a) pd(a) p(b) (1-pd(b)) + p(a) (1-pd(a)) p(b) pd(b) p(a)p(b)


pal(y) = (1-p(a)) pu(a) (1-p(b)) pu(b) + (1-p(a)) pu(a) p(b) (1-pd(b)) + p(a) (l-pal(a)) (1-p(b)) pu(b) (1-p(a))(1-p(b)) + (1-p(a))p(b) + p(a)(1-p(b))


p(y) = (1-p(a)Xl-p(h)) + (1-p(a))p(b) + p(a)(1-p(b))


V. E l S v c ~ Powe~ ~ t i o n Each node of the circuit is characterized by a queue of statistical events. An event occurs when the node changes with a non-zero probability tYom L to H e r from H to L. :~ach event is defined by: • a date of occurrence between 0 and T, • the conditional probability pu of a transition from L to H assuming that the preceding state was L, • the conditional probability pd of a transition from H to L assuming that the preceding state was H. F i g u r e 1 i l l u s t r a t e s the example of e v e n t propagation through a NAN]) gate, using (9). The power consumption calculation is performed in 3 phases: 1) Calculation of the p parameters from pu and pd of the primary inputs using (8). 2) Propagation of the p, pu, and pd parameters from p r i m a r y inputs to p r i m a r y outputs using transfer functions as shown in (9). 3) Calculation of power consumption by means of (1) and (2): Mean probability is obtained from p and all event occurrence dates of each node. Mean activity is obtained from p, pu, pd of each node using (6). Electrical parameters (node capacitance, stat~: currents) must be provided from circuit characterization or extraction. Our mode] assumes that all logic transitions are complete and that they are propagated through the whole circuit without damping, in the same w a y as in logic simulation. Since the power consumption of complete transitions is always bigger as for incomplete transitions [2], our m e t h o d t e n d s to o v e r e s t i m a t e power, i f incomplete transitions occur a t different dates.

On t h e other hand, incomplete t r a n s i t i o n s occurring during a time smaller than the chosen sampling interval T/N, cannot be t a k e n into account. Since the same problems occur in logic simulation, logic simulations versus electrical simu!ations rather than probabilistic simulations versus logic slmu!latious have to be studied under the power constunption aspect. The damping of short pulses can be modeled using the concept of latency probabilities which is analog to a spike suppression mechanism used in some logic simulators [7]. The phenomenon of spikes due to simultaneously occurring input transitions could be modeled by introducing a spike generation t e r m in the transfer function. p act

~.~ oA

o~ 0.4

AI pu X o , ~


p 0~$







p 0.79

0.6 0,8







_.,,, pd

date o








5 6

7 0


FiEure 1: Event transfer through a NAND gate

Powerconsumptionestimationusingstatisticalsignalproper~es VI. Itexulto Within the project PATMOS, we implemented a program that performs the calculation of state probability and activity from the statistical parameters pu and pd for each node. A compiler of transfer functions from logic tables and a generator of test vectors following the statistics of the primary inputs are also included. This set of vectors is used to perform logic simulations on HILO t7]. Logic simulation is only needed for validation of the PATMOS method. Results from HILO have been taken as reference in order to compare them with PATMOS. The results for a 32 bit Ripple Carry Adder (RCA32) and a set of benchmark circuits [ 8 ] are summarized in table 2, where mean activity is d e f i n e d as HILO


all nodes number of nodes Signed error and absolute error on activity are defined as PATMOS activity - HR,O activity all nodes ~100% HILO activity all nodes and IPATMOS activity - HILO activity I all nodes *100% HILO activity all nodes


"i'he corresponding values on state probabifity are defined in an analog manner. Activity and state probability of primary inputs are not taken into account, since t h e i r power i s d i s s i p a t e d externally. The signed error of activity and probability is related to the error on mean power consumption, since mean power is obtained by summing up activities and probabilities multiplied with meau current values according to (1) and (2). The absolute error measures the accuracy of the PATMOS e v e n t model c o n c e r n i n g t h e distribution of activity and probability in time and space and therefore gives hints, whether t h i s model could be applied in other domains, for i n s t a n c e peak c u r r e n t e s t i m a t i o n , noise m-odelling, test and so on. The activity and probability values calculated by our program are excellent as far as internal gate inputs are not correlated or weakly correlated (RCA32, C17). When the number of internal nodes is big compared to the number of primary inputs, the error due to the assumption of independence becomes important (C1355, C1908). Since the errer is not easily predictable from the number of nodes (see the different results for C432, C499, C880), we are currently developping a general approach for correlated nodes, using the concept of supergatos [3]. A special approach for the estimation of power consumption for circuits with. high regularity, where correlation can be derived easily from the architecture (RAM, RaM, PLA) is under study.


no. no. no. PATMOS HILO no. mew state ~igmdc~ro~ absolute mere signed al~vbNe pt'obabiihy oo ¢nl~rOfl ~ i ~ l y erloroo t,rmlroll n~es inputs outputs CPU lime CPU time ~ OnVAX onVAX input ~ H]LO pl~ab0By p¢obability ~ acdvity acdvily 4000 4000 ve~m~ E~LO ~CA32 129 65 33 17.2 sec 39.3 ~ c 500 0.50 -0.7 % 3.4 % 0.96 0.7 % 6.7 % 5 2 0.2 sec L4 sec I000 0.65 -0,2 % 3.9 % 0.48 5.9 % ,!1 % C17 15 36 ? 3.9 SeC 24.2 sec I000 0.36 3.9 % 12 % 0.66 -3.7 % 24 % C432 200 C499 247 41 32 3.2 see 28.6 sec [000 0.37 -0.3 % 2.9 % 0.56 -0.4 % 3.9 % 60 26 7.5 sec 46.0 ~ec 1000 0.49 1.4 % 4,8 % 0,57 -8.7 % 15 % C880 383 41 32 24,3 sec 42,6 sec 500 0,61 -5,9% I1% 0.St -22% 27% C1355 591 CtP08 917 33 25 52.0sec 80.4~ 500 0.58 -0.5 % 5.7 % 1-05 -38% 40 % Table 2: probability and activity calculation compared to logic simulation


w. R#thig et al.

Conelu~on A technology independent method for m e a n p o w e r c o n s u m p t i o n e s t i m a t i o n b a s e d on statistical signal properties w a s exposed. State probability and logic activity for each node in a circuit are calculated using boolean-probabilistic t r a n s f e r functions. Validation a g a i n s t logic simulation h a s been done for some complex ~ts. Compared to logic simulation, there is a considerable gain of CPU time (factor 6...9 for 1000 H I L O input vectors, although our LISP p r o g r a m is i n t e r p r e t e d and not compiled). Validation against electrical simulation is also possible, but limited in complexity. In the future, we intend to apply our method to VLSI circuits developed in our d e p a r t m e n t in order to get validation with respect to measurements.

The authors are grateful for the encouragement a n d a d v i c e f r o m Prof. F r a n c i s J u t a n d , TELECOM Paris, Prof. Antonio Nuflez and his crew from Lns P a l m a s University, and P r o f H a r t e n s t e i n and his crew from Kaisersiautern University. This work h a s been accomplished within t h e PATMOS E S P R I T Basic Research Action 3237, supported by t h e E u r o p e a n Community.

P~erences [1]

S. Chowdhury and Javed Sabir Barkatullah, "Estimation of Maximum Currents in MOS IC Logic Circuits", IEEE Transactions on CAD, voL9, us.6, June 1990. [2] Srinivas Devadas, Kurt Keutzer, and Jacob White, "Estimation of Power Dissipation in CMOS Combinational Circuits", in Prec. IEEE Custom Integrated Circuits Conference, 1990 [3] F a r i d Najm, Richard Burch, Ping Yang, and Ibr~b~m Hajj, "CREST - A Current E s t i m a t o r for CMOS Circuits", in Prec. IEEE I n t e r n a t i o n a l Conference on Computer-Aided Design, ICCAD-89. [4] K e n n e t h P. P a r k e r and E d w a r d J. McCluskey, "Prebabilistic T r e a t m e n t of General Combinational Networks", in IEEE Trans. on Computers, pp. 668-670, J u n e 1975. [5] Farid N. Najm, Richard Bureh, Ping "fang, a n I b r a h i m N. H a j j , " P r o b a b i l i s t i c Simulation for Reliability Analysis of CMOS VLSI Circuits", in IEEE Transactions on CAD, vol.9, no.4, April 1990. [6] Stephen I. Long, Steven E. Butner, Gallium Arsenide Digital Integrated Circuit Design, McGraw-Hill 1990 [7] "System Hilo G H D L Reference M a n u a l Issue 1", GenRad 1988. [8] F. Brglez, H. Fujiwara, " A Neutral Netlist of 10 Combinational Benchmark Circuits", Special Session on "Recent Algorithms for Gate-Level ATPG with F a u l t Simulation and Their Performance Assessment", a t I E E E Int. Syrup. Circuits and Sys., J u n e 1985.