16th of Optimization 16th IFAC IFAC workshop workshop on on Control Control Applications Applications of online Optimization Available at www.sciencedirect.com October 6-9, 2015. Garmisch-Partenkirchen, Germany October 6-9, 2015. Garmisch-Partenkirchen, Germany 16th IFAC workshop on Control Applications of Optimization October 6-9, 2015. Garmisch-Partenkirchen, Germany
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IFAC-PapersOnLine 48-25 (2015) 156–161
REALIZATION REALIZATION OF OF ROBUST ROBUST CONTROLLER CONTROLLER ALGORITHM ALGORITHM USING USING FPGA FPGA Ján Michal Kozák REALIZATION OF ROBUST CONTROLLER USING FPGA Ján Cigánek, Cigánek, Michal Kocúr, Kocúr, Štefan ŠtefanALGORITHM Kozák Ján Cigánek, Michal Kocúr, Štefan Kozák Faculty of Electrical Engineering and Faculty of Electrical Engineering and Information Information Technology, Technology, Slovak University of Technology in Slovak University of Technology in Bratislava Bratislava Faculty of Electrical Engineering and Information Technology, Bratislava, Slovakia Bratislava, Slovakia in Bratislava Slovak University of Technology e-mail:
[email protected],
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[email protected],Bratislava,
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[email protected] Slovakia e-mail:
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Abstract: The presented presented paper paper deals deals with with the the development development of of robust robust control control algorithm algorithm based based on on Abstract: The reflection vectors methodology. This approach of controller design is guaranteeing stability, robustness reflection methodology. approach of development controller design is guaranteeing stability, robustness The presented paperThis deals with the of robust control algorithm based on Abstract: vectors and The method was successfully tested for strong and high high performance. performance. The presented presented method of wascontroller successfully tested for stable, stable, unstable unstable and strong reflection vectors methodology. This approach design is guaranteeing stability, and robustness oscillating processes and for systems with parametrical model uncertainty. The proposed algorithm can oscillating processes andThe for presented systems with parametrical model uncertainty. proposed algorithm can and high performance. method was successfully tested for The stable, unstable and strong be effectively realized using field-programmable gate array (FPGA) structure as it is shown in the case be effectively realizedand using gate array (FPGA) structure it is shown in the case oscillating processes for field-programmable systems with parametrical model uncertainty. Theasproposed algorithm can study –– the using DC All simulations and study the hardware hardware realization using FPGA FPGA technology technology for(FPGA) DC motor. motor. All presented presented simulations and be effectively realizedrealization using field-programmable gate arrayfor structure as it is shown in the case co-simulations were in co-simulations were realized realized in MATLAB-Simulink. MATLAB-Simulink. study – the hardware realization using FPGA technology for DC motor. All presented simulations and co-simulations were realized in MATLAB-Simulink. © 2015, IFAC (International Federation of Automatic Control) Hosting byquadratic Elsevier Ltd. All rights reserved. Keywords: robust control; stability; parametrical uncertainty; programming; reflection Keywords: robust control; robust robust stability; parametrical uncertainty; quadratic programming; reflection vectors; FPGA; co-simulation. vectors; FPGA; co-simulation. Keywords: robust control; robust stability; parametrical uncertainty; quadratic programming; reflection vectors; FPGA; co-simulation. achieved achieved by by magnetic magnetic relays relays extensively extensively used used in in old old industry industry automation systems. Then, it became achievable by of automation became achievable means of achieved bysystems. magneticThen, relaysit extensively used in by oldmeans industry digital logic gates and Medium Scale Integration (MSI) digital logicsystems. gates and Integration (MSI) automation Then,Medium it becameScale achievable by means of components. When system size and components. Whenandthe theMedium system Scale size Integration and complexity complexity digital logic gates (MSI) increases, Application Specific Integrated (ASICs) increases, Application Specific Integrated Circuits (ASICs) components. When the system size Circuits and complexity are utilized. The be on are utilized. The ASIC ASIC must be fabricated fabricated on aa increases, Application Specificmust Integrated Circuits (ASICs) manufacturing process that takes several manufacturing line, processmust that be takesfabricated several months, months, are utilized. line, The aaASIC on a before it used or tested [1],[2]. FPGAs are before it can can be be used or even even that tested [1],[2]. FPGAs are manufacturing line, a process takes several months, configurable ICs and used to implement logic functions. configurable usedortoeven implement functions. before it canICs beand used tested logic [1],[2]. FPGAs are configurable ICs and used to implement logic functions. Today’s Today’s high-end high-end FPGAs FPGAs can can hold hold several several millions millions gates gates and and have some significant advantages over ASICs. They ensure have some significant advantages ASICs. They ensure Today’s high-end FPGAs can hold over several millions gates and ease of lower development ease of design, design, loweradvantages development costs, more product have some significant over costs, ASICs.more Theyproduct ensure revenue the to to [3]. revenue and the opportunity opportunity to speed speed products products to market market [3]. ease of and design, lower development costs, more product At the same they superior to At the and samethetime, time, they are are superior to software-based software-based revenue opportunity to speed products to market [3]. controllers as more compact, power-efficient, while controllers as they they arethey moreare compact, power-efficient, while At the same time,are superior to software-based adding high speed capabilities. adding highasspeed controllers they capabilities. are more compact, power-efficient, while adding high speed capabilities. 2. 2. PROBLEM PROBLEM STATEMENT STATEMENT 2. PROBLEM STATEMENT Let Let us us consider consider the the robust robust control control synthesis synthesis of of aa scalar scalar discrete-time control loop. The transfer function the discrete-time control loop. The transfer function ofscalar the Let us consider the robust control synthesis of a of original continuous-time system is described by the transfer original continuous-time system describedfunction by the transfer discrete-time control loop. Theis transfer of the function function original continuous-time system is described by the transfer function
1. 1. INTRODUCTION INTRODUCTION 1. INTRODUCTION of robust control During During last last ten ten years, years, development development of robust control elementary and evolution robust elementary principles and development evolution of of new new robust control control During lastprinciples ten years, of robust methods for different model uncertainty types are methods forprinciples different and model uncertainty types are visible. visible. elementary evolution of new robust control Based on theoretical modelling and simulation Based on for theoretical assumptions, modelling andare simulation methods differentassumptions, model uncertainty types visible. methods, effective approach the of processes methods, an effectiveassumptions, approach to to modelling the control controland of simulation processes Based on an theoretical with strong and undefined uncertainties is designed. Such with strong undefined uncertainties is designed. Such methods, an and effective approach to the control of processes uncertainties are typical for biotechnology processes, uncertainties areundefined typical uncertainties for biotechnology processes, with strong and is designed. Such chemical plants, aviation, For chemical plants, automobile industry, aviation, etc. etc.processes, For such such uncertainties areautomobile typical industry, for biotechnology processes, it necessary design robust practical processes, it is is automobile necessary to to design aviation, robust and and practical chemical plants, industry, etc. For such algorithms ensure performance robust algorithms itwhich which ensure the theto high high performance andpractical robust processes, is necessary design robust andand stability techniques with stability using using proposed mathematical techniques with algorithms whichproposed ensure themathematical high performance and robust respect the parametric and unmodelled uncertainties. respect the unmodelled uncertainties. stability usingparametric proposed and mathematical techniques with Solution problems possible using predictive Solution to to such problems is isand possible using robust robust predictive respect thesuch parametric unmodelled uncertainties. methods and “soft-techniques” which include fuzzy sets, methods toand “soft-techniques” which include sets, Solution such problems is possible using robustfuzzy predictive neuron networks and genetic algorithms. neuron networks and genetic algorithms. methods and “soft-techniques” which include fuzzy sets, neuron networksisand genetic algorithms. Robust Robust control control is used used to to guarantee guarantee stability stability of of plants plants with with parameter changes. The controller design consists of parameter changes. Thetorobust robust controller design consists of Robust control is used guarantee stability of plants with two steps: two steps: changes. The robust controller design consists of parameter two steps: •• analysis analysis of of parameter parameter changes changes and and their their influence influence for closed-loop stability, closed-loop stability,changes and their influence • for analysis of parameter for closed-loopsynthesis. stability, •• robust robust control control synthesis. • robust control synthesis. There There are are two two approaches approaches for for implementing implementing control control systems systems using digital technology. The first approach is on using are digital Theimplementing first approach is based based on There two technology. approaches for control systems software which implies a memory-processor interaction. The software which implies a memory-processor interaction. The using digital technology. The first approach is based on memory application program the memory holds the application program while while the processor processor software holds which the implies a memory-processor interaction. The fetches, executes the instructions. fetches, decodes, and executes the program program instructions. memory decodes, holds the and application program while the processor Programmable Logic (PLCs), microcontrollers, Programmable Logic Controllers (PLCs), microcontrollers, fetches, decodes, andControllers executes the program instructions. microprocessors, Digital Signal Processors (DSPs) microprocessors, Digital Signal (PLCs), Processors (DSPs) and and Programmable Logic Controllers microcontrollers, general purpose computers tools software general purpose Digital computers areProcessors tools for for software microprocessors, Signalare (DSPs) and implementation. the second is implementation. On computers the other other hand, hand, thetools second approach is general purposeOn are the forapproach software based on hardware. Early hardware implementation is based on hardware. implementation implementation. On theEarly other hardware hand, the second approach is based on hardware. Early hardware implementation is
_ _
_ _
_ _
_ _
m 1 b mm ss mm B b b b_ mm11 ss m1 b_ 00 e Ds B_ ss e Ds Ds b G s _ P e Ds GP s __ e __ m __ _ m 1 _ 1 n n b s b s b B s 1 0 m m ss e Ds aa_ nn ss n aa_ nn11 ss n1 GP s A a a_ 00 e Ds A _ n 1 toa 0its discretes n be a nconverted As of (1)a ncan 1 s The transfer function function The transfer of (1) can be converted to its discrete-
time counterpart time transfer counterpart The function of (1) can be converted to its discretetime counterpart b b z 11 b z nn b00 b11 z11 bnn znn zz dd G P zz 11 G P 1 n b b z b z 1 a z a z d 1 n 0 1 G P z 1 a11 z 1 a nn z n z 1 a1 z a n z For For (2) (2) aa discrete-time discrete-time controller controller is is to to be be designed designed in in form form For (2) a discrete-time controller is to be designed in form
2405-8963 © 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved. Peer review under responsibility of International Federation of Automatic Control. Copyright © 156 Copyright © IFAC IFAC 2015 2015 156 10.1016/j.ifacol.2015.11.076
156 156
Copyright © IFAC 2015
156
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GR z
q0 q1 z 1 q z Q( z ) U ( z ) 1 p1 z 1 p z P( z ) E ( z )
1 GP ( z 1 )GR ( z 1 ) 0
C Gx
Now, we can formulate the following control design problem: find a discrete controller, where the closed-loop characteristic polynomial C(z) is placed:
Substituting (3) and (2) in (4), after a simple manipulation yield the characteristic equation
In a stable target polytope V, C( z ) V (to guarantee stability),
a)
1
1
n
1 GPGR (1 p1 z p z )(1 a1 z an z )
(q0 q1 z 1 q z )(b1 z 1 bn z n ) z d 0
where G is the Sylvester matrix of the plant [12] with dimensions n d 1 2 and x is the of controller parameters: 2 -vector T . x p , , p1, 1, q , , q0
The corresponding closed-loop characteristic equation is
157
b) As close as possible to a target polynomial e(z), e( z ) V (to guarantee performance).
Unknown coefficients of the discrete controller can be designed using various methods. In this paper, a robust controller design method based on reflection vectors is used.
Let the polytope V denote the (k+1)×N matrix composed of coefficient vectors vj, j=1,…,N corresponding to vertices of the polytope V[13].
The pole assignment problem is as follows: find a controller GR(z) such that C(z)=e(z) where e(z) is a given (target) polynomial of degree k. It is known [4] that, when μ=n–1, the above problem has a solution for arbitrary e(z) whenever the plant has no common pole-zero pairs. In general, for μ < n – 1 exact attainment of a desired target polynomial e(z) is impossible.
Then we can formulate the above controller design problem as an optimization task: Find x that minimizes the cost function 2
J1 min xT GT Gx 2eT Gx min Gx e x
Let us relax the requirement of attaining the target polynomial e(z) exactly and enlarge the target region to a polytope V in the polynomial space containing the point e representing the desired closed-loop characteristic polynomial. Without any restriction we can assume that an p0 1 and deal with monic polynomials C(z), i.e.,
x
subject to the linear constraints
0 1 .
G x V w(x), w j ( x) 0, j 1,..., N ,
w ( x) 1.
j
j
Here, w(x) is the vector of weights of the polytope V vertices to obtain the point C = G x. Fulfillment of the latter two constraints (12), (13) guarantees that the point C is indeed located inside the polytope V. Then, finding the robust poleplacement controller coefficients represents an optimization problem that can be solved using the Matlab Toolbox OPTIM (quadprog) with constraints.
Let us introduce the stability measure as ρ = cT c, where c S 1C
and S is a matrix of dimensions (n + μ + 1) x (n + μ + 1) representing vertices of the target polytope V. For monic polynomials holds k 1
ci 1
Generally J1 is a kind of distance to the centre of the target polytope V. It is better to use another criterion J2, which measures the distance to the Schur polynomial E(z)
i 1
where k = n + μ. If all coefficients are positive, i.e., ci > 0,
J 2 (C E)T (C E) (Gx E)T (Gx E).
It is possible to use the weighted combination of J1 and J2
i = 1,..., k + 1, then the point C is placed inside the polytope V.
The minimum ρ is attained if
and to solve the following quadratic programming task
c1 c2 ck 1
1 k 1
J (1 ) J1 J 2 , 0 1
J min xT GT (1 )(SS T ) 1 I k 1 Gx 2E T Gx , x 1
S Gx 0.
Then the point C is placed in centre of the polytope V.
Assume the discrete robust controller design task with parametrical uncertainties in system description. Let us also assume that coefficients of the discrete-time system transfer
In matrix form, we have 157
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effectively used in many applications of signal processing [7] and system identification [8]. A complete characterization and classification of polynomials using their reflection coefficients instead of roots (zeros) of polynomials is given in [5].
functions an , ..., a1 and bn , ..., b1 are placed in polytope W with the vertices d j anj ,a1j , bnj ,, b1j :
W conv{d j , j 1,..., M }
As (9) is linear in system parameters, it is possible to claim that for arbitrary vector of the controller coefficients x is the vector of the characteristic polynomial coefficients C(z) placed in the polytope A with vertices a1 ,,a M :
A conv{a j , j 1, ..., M }
The main advantage of using reflection coefficients is that the transformation from reflection to polynomial coefficients is very simple. Indeed, according to (22) and (24), polynomial coefficients ci depend multilinearly on the reflection coefficients ri. If the coefficients ci R are real,
then also the reflection coefficients ri R are real.
where a j = D j x and D j is the Sylvester matrix of dimensions (n + μ + d + 1) x (μ + υ + 2), composed of vertices set d j , as in case of the exact model (9).
Transformation from reflection coefficients ri,i=1,...,k, to polynomial coefficients ci,i=1,...,k, is as follows ci ci( k )
2.1 Stable Region Computation via Reflection Coefficients
ci(i ) ri
Polynomials are usually specified by their coefficients or roots. They can be characterized also by their reflection coefficients using Schur-Cohn recursion.
(i )
cj
C ( z 1 ) 1 c1 z 1 ... ck z k
1
1
C ( z ) ck ck 1 z c1z
k 1
Lemma 2. A polynomial C(z-1) has all its roots inside the unit
k
disk if and only if ri 1, i = 1, ..., k.
z
A polynomial C(z-1) lies on the stability boundary if some ri 1, i = 1, ..., k. For monic Schur polynomials, there is a one-to-one correspondence between C ck , ,c1 T and
[6]
1 z Ci1 ( z ) Ci ( z 1 ) ri Ci ( z 1 ) 1 ri 2 1
1
r r1 ,,rk T .
Stability region in the reflection coefficient space is simply the k-dimensional unit hypercube R ri ( 1,1 ), i 1,,k. . The stability region in the polynomial coefficient space can be found starting from the hypercube R[14].
where ri ci and ci is the last coefficient of Ci ( z 1 ) of degree i. From (21) we obtain in a straightforward way:
Ci ( z 1 ) z 1Ci 1( z 1 ) ri Ci1( z 1 ).
Expressions for polynomial coefficients
Ci 1 ( z 1 )
2.2 Stable Polytope of Reflection Vectors and It will be shown that, for a family of polynomials the linear cover of the so-called reflection vectors is Schur stable.
Ci ( z 1 ) result from equations (22,23):
The stability criterion in terms of reflection coefficients is as follows [5].
Reflection coefficients ri, i = 1, ..., k, can be obtained from the polynomial Ck ( z 1 ) using backward Levinson recursion
( i 1 )
ri ci j
Lemma 1. A linear discrete-time dynamic system is stable if its characteristic polynomial is Schur stable, i.e., if all its poles lie inside the unit circle.
Reciprocal polynomial C k ( z 1 ) of the polynomial C ( z 1 ) is k defined in [5] as follows k
( i 1 )
cj
i 1,, k ; j 1,, i 1
Let Ck(z-1) be a monic polynomial of degree k with real coefficients ci R, i = 0, ..., k
Ci 1( z 1 )
i 1 ci , j 1 ri ci ,i j 1 z j 2 1 ri j 0
1
Ci ( z 1 ) ci 1, j 1 ri ci 1,i j 1 z j . i
)
Definition 1. The reflection vectors of a Schur stable monic polynomial C(z-1) are defined as the points on stability boundary in polynomial coefficient space generated by changing a single reflection coefficient ri of the polynomial C(z-1).
j 0
Let us denote the positive reflection vectors of C(z-1) as vi ( C ) C ri 1, i 1,,k , and the negative reflection vectors of
The reflection coefficients ri are also known as Schur-Szegö parameters [5], partial correlation coefficients [8] or kparameters [7]. Presented forms and structures were
C(z-1) as vi ( C ) C ri 1, i 1,,k . 158
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The following assertions hold: 1.
2.
polynomial is placed inside the stable polytope of reflection vectors V(C).
every Schur polynomial has 2k reflection vectors vi (C ) and vi (C ), i 1,, k ;
3. IMPLEMENTATION OF CONTROL ALGORITHM
all reflection vectors lie on the stability boundary
(ri 1);
The digital form of the controller can be obtained from (3). Recursive form of control algorithm is expressed by the following equation:
the line segments between reflection vectors vi (C ) and vi (C ) are Schur stable.
v
3.
1.
Consider
r1C 1,1, rk 1,1 C
uk q1ek 1 q2 ek 2 p1uk 1 p2uk 2
For implementation of control algorithm (27) for FPGA is necessary to decompose equation into simple arithmetic operations:
In the following theorem a family of stable polynomials is defined such that the polytope generated by reflection vectors of these polynomials is stable [13]. Theorem
ek wk yk
and
q1e1 q1 * ek 1 q2 e2 q2 * ek 2
r2C rkC1 0 .
Then the inner points of the polytope V(C) generated by the reflection vectors of the point C
V (C ) conv vi (C ), i 1,, k
159
p1u1 p1 * uk 1 p2u2 p2 * uk 2
s1 q1e1 q2e2 s2 p1u1 p2u2
are Schur stable.
s3 s1 s2
2.3 Robust Controller Design
Control output u must be bounded in the range from umin to umax.
A robust controller is to be designed such that the closedloop characteristic polynomial is placed in the stable polytope (linear cover) of reflection vectors. It means that the following problems have to be solved:
3.
choice of a target polynomial E(z-1).
In this case, the parallel design of control algorithm is used, which means that each of the operation has its own arithmetic unit, either accumulator or multiplier. Parallel design is shown in Figure 1.
In the following section some “thumb rules” are given for choosing a stable target simplex S.
Reg2
* q2
q2e-2
w
To choose k + 1 vertices of the target simplex S we use the well known fact that poles with positive real parts are preferred to those with negative ones [9]. The positive reflection vectors vi ( C ) with i odd and negative reflection vectors vi ( C ) with i even are chosen yielding k vertices. The (k+1)th vertex of the target simplex S is chosen as the mean of the remaining reflection vectors.
+
e(k)
-
e(k-1)
q1e-1
y
q1
<
s1
Reg1
*
U_max
U_min
-
u(k-2)
s3
u(k)
mux
choice of k + 1 most suitable vertices of V(C) to build a target simplex S,
u min if s3 u min
choice of initial polynomial C(z-1) for generating the polytope V(C),
2.
u k s3 if u min s3 u max
mux
1.
u max if s3 u max
Reg4 p2
*
s2
p2e-2
U_max
>
+ u(k-1) p1e-1
Reg3
The target polynomial E(z-1) of order k is reasonable to be chosen inside the stable polytope of reflection vectors V(C). A common choice is E(z-1)=C(z-1).
p1
*
Figure 1. Parallel design of the control algorithm
For higher-order polynomials, the size of the target simplex S is considerably less than the volume of the polytope of reflection vectors V. That is why the above quadratic programming method with a preselected target simplex S works only if uncertainties are sufficiently small. Otherwise, it is reasonable to use some search procedure to find a robust controller such that the polytope of closed-loop characteristic
Each sampling period is loaded the motor system output y(k) from the input in. Control error e(k) is computed in sub block where the signal y(k) is subtracted from w(k). Signal e(k) is held in the registry REG1 for one sampling period. Register REG1 output signal is thus e(k-1). In the same manner, e(k−2), u(k−1) and u(k−2) are recorded at REG2, REG3 and REG4 by latching e(k−1), u(k) and u(k-1) respectively. For 159
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multiplication, they are using digital signal processor (DSP) cores in FPGA chip. Results of multiplications are counted in to control output. This control output is then bounded in the range from −12V to 12V. Inputs w and y are represented with rpm (Revolutions per minute). Input range is -2048 to 2047 rpm, because of the 12bit signed data type. Output of the controller is represented with volts. In signed binary representations the maximum control output is 12(10)V = 01100(2) and the minimum is −12(10) V = 10100(2). We can write this range into 5 bits. Real numbers are useful for better quantization of the control output. For implementation of the real numbers it has been used fixed point arithmetic [10]. As we can see in Figure 2 first (MSB) bit of output vectors is reserved for a sign. Next four bits are reserved for the integer part and last seven bits are used for the fractional part.
Figure 3. Schematic of control circuit using Xilinx blocks
4. CASE STUDY Consider a DC system described by the first order nominal transfer function
Integer part
153.4 Bs Ds K e e Ds e 0.01s 0.07392s 1 As T1 s 1
where coefficients K, T1 are varying in uncertainty intervals K 150; 160 , T1 0.070; 0.078
00010.1110000(2) = 2.875(10)
Sign bit
GP s
Consider the nominal continuous-time transfer function which is converted to the discrete-time form with the sampling period T=0.01s:
Fractional part
Figure 2. Fixed-point control output
Fixed point arithmetic is applied throughout the control algorithm. In designing this algorithm, the fixed-point arithmetic range rules must be respected. The data widths in the fixed-point arithmetic were designed that there is no possibility of an overflow. For example, the result of summation or subtraction of two 12-bit vectors has range 13bit.
G p ( z 1 )
19.41.z 2 1 0.8735 z 1
The main task is to design a robust discrete-time controller (3), with polynomial degrees υ=1, μ=2. From the transfer function (31) and matrix form of (9) we can obtain:
In the case of parallel design of control algorithm, the control output after last summation (resp. subtraction) has range 40bit (16-bit for fractional part). It must be used a bounder block to ensure of range (-12 V to 12 V) for 12bit. Bounder is the value limitation logic that keeps the output in the defined range. Bounded signal is latched at register REG3, thus becomes u(k−1) of next cycle. In this way the antiwindup protection is also ensured.
0 0 19.4097 0 p2 0 p 0.8735 0 0 0 19 . 4097 1 C 1 0 0 0 1 0.8735 1 0 0 q1 0.8735 0 0 0 1 0 0 q 0
Let us choose the initial polynomial C(z-1) for generating the polytope V(C) as follows
Before the hardware implementation the control algorithm is verified of software Matlab-Simulink. System Generator toolbox ensures that between the blocks gateway in and gateway out algorithm performs as it was implemented on FPGA. We proposed decomposed control algorithm to be consisted of Xilinx blocks (in Fig. 3). In this step we determined the minimum widths of the internal signals. For the implementation of decimals numbers it has been used fixed point arithmetic.
C ( z) 1 0.1z 1
with reflection coefficients r1 0.1, r2 r3 r4 0 . Now, we can find the reflection vectors vi ( C ) of the initial polynomial C(z-1) leading to the matrix form of the target simplex S (vertex polynomial coefficients)
Based on the successful verification of the Xilinx blocks algorithm we created the VHDL code which is used in the resulting hardware solutions. The VHDL code we have developed in Xilinx ISE Design Suite. For the implementation of fixed point arithmetic in VHDL code there is used library (ieee_proposed.fixed_pkg). Simulation of VHDL code is possible using Xilinx black box block. Simulation results are in Fig. 4.
0 0.3 0.15 0.1 0.25 0 0 0.7 0.3 0.5 S 0.25 0.5 0 0.5 0.2 0 . 5 0 0 . 4 0.4 0 1 1 1 1 1
The discrete-time controller design task for the nominal transfer function (30) has been solved via quadratic programming taking α=0.05 in the cost function J (16).
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For the selected target simplex S we have obtained the following discrete-time feedback controller
GFB z 1
Q( z 1 ) 0.03145 0.01117 z 1 1 P( z ) 1 0.9311z 1 0.6679 z 2
successfully implemented and hardware realized on Artix-7 FPGA board. FPGA structure is very suitable for high speed processes.
161
In proposed paper were presented the basic necessary principles how to realize and to modify existing digital robust control algorithms. The option of co-simulation can be useful to accelerate simulation of advanced control algorithms. In results comparison of control simulation and hardware realization on DC motor were obtained following facts. The closed control loop in simulation offered higher quality, i.e. lower overshoot and shorter control time. One of the reasons of this difference could be non-accurate process identification by acceptation of the first order.
and the control law is expressed in recursive form u 2 k 0.931u 2 k 1 0.668u 2 k 2 0.0315 y(k ) 0.0112 y(k 1)
Corresponding closed-loop step response under the feedback controller (34) and feed-forward controller GFF z 1 S ( z 1 ) / P( z 1 ) 2 is in Fig.5.
ACKNOWLEDGMENT
For verification of the FGPA implementation of the digital controller we realized a practical experiment. In simulation with Xilinx blocks we made step of reference signal at 0.01s.
This paper is supported by APVV project No. APVV-077212. REFERENCES [1]
[2] [3] [4] [5] Figure 4. Time response of outputs and reference variable under robust controller
[6]
The same controller (31) was used also for hardware realization to control real DC-motor. The graphical results are shown in Fig. 5.
[7] [8] [9] [10] [11] [12]
[13] [14] Figure 5. Hardware realization of control algorithm
5. CONCLUSION The presented paper deals with the new approach of robust controller design using the reflection vectors techniques. The control structure consists of feed-forward and feedback part. Proposed algorithm was tested using FPGA technology for DC motor. The illustrative example was solved using quadratic programming for suitably defined performance function. The obtained results demonstrate very effective applicability of the theoretical principles for process control with parametrical model uncertainty. Digital controller was 161
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