- Email: [email protected]
Reconfigurable Logic Controller with FPGA
Copyright © IFAC Algorithms and Architectures for Real-Time Control, Vilamoura, Portugal, 1997
RECONFIGURABLE LOGIC CONTROLLER WITH FPGA
Marek Wegrzynl), Prof. Marian A.Adamski1,2), Prof. Joao L.Monteiro
2
)
Zielona Gora Technical University, Computer Eng. & Electronics Dept. 50. Podgoma Street, 65-246 Zielona Gora, Poland tel. (+4868) 254831 x.526; fax (+4868) 244733, 253944 E-mail: [email protected]. [email protected] 2)Universidade do Minho, Braga-Guimaraes, Departamento de Electronica Industrial Azurem, 4800 Guimaraes, Portugal tei. (+35153) 510190, fax (+35153) 510189,514400 E-mail: [email protected] J)
Abstract: An implemented design framework contains the Programmable Logic based synthesis of rule-based descriptions that are obtained from several specification models of Concurrent Controllers (for example: Control Interpreted Petri net, Grafcet or IEC 1131-3 Sequential Function Chart). The specification in the form of symbolic conditional decision rules is transformed into a format that is accepted by standard FPLD & FPGA simulators and synthesizers, for example OrCAD or VHDL. The Concurrent State Machine model of Logic Controller is verified using the well-developed Petri net theory. and then it is translated through automated processes into selected FPGA specification format, for example Xilinx netlist format (XNF). Keywords: Custom VLSI devices. Industrial process control, Petri Net, Sequential Function Chart (SFC), Logic Controllers. FPGAs
The translation is straightforward and simple. The general 'If-Then' Decision Rules (non-procedural conditional statements) may be mapped into Xilinx format constructs directly, or after some simple additional transformations. The final multi-level combinational optimisation, placement and routing are performed by standard design tools.
1. INTRODUCTION
The main aim of this paper is the practical, direct mapping of a Logic Controller program into a Field Programmable Gate Arrays (FPGAs). In one of the possible methodologies, we apply a rule-based logic specification format and direct mapping of Petri net into the hardware library, by means of the Xilinx Automated CAE Tools (XACT). Proposed Decision Rule Specification, as a textual equivalent of Petri net can be also easily modelled using other hardware Description Languages (HDL), particularly with VHDL (Wegrzyn, et.al. , 1996). The experimental results show that our approaches may produce economical and flexible LCA implementations of relatively simple, dedicated Logic Controllers .
2. FPGA AS A LOGIC CONTROLLER FPGAs are electronic circuits, which can be reconfigured by the user to perform a particular combinational or registered logic function (Fig. 1). As user-programmable Application Specific Integrated Circuits, they provide a valuable compromise which combines the benefits of standard
239
Svrnbolic Petri net description is based on the c~ncept of extended production rules, described by means of the conditional logic. The first implementation was performed in Logician CAD system (Adamski, 1991). The syntax of language was revised over years. Some major syntax modifications have been made in PARIS system. and a new description format called the Petri Net Specification Format (PNSF) for VLSI design was introduced (Kozlowski , et.a!. , 1995). The CONPAR specification format (Fernandes, et.a!. , 1996) is consistent with previously introduced rule-based specification languages and was also created mainly as a bridge between textual logic description of Petri nets and their VHDL models. Transition rules are usually treated as production rules Cif-then' non procedural statements). The rule-based description, supported by means of logic deduction techniques (Gentzen natural logic calculus), was recently presented in Programmable Logic Controller design context (Adamski and Monteiro, 1996). A Petri net can be first expressed graphically, and then manually or automatically translated into an equivalent textual format. Some graphical Petri net tools are under development. The specifications with sound Grafcet (David and AlIa 1992) or SFC (lEC, 1992; Halang, 1989; Jiang and Holding, 1992) are treated as special forms of Control Interpreted safe Petri Nets. We have implemented an intermediate rule-based language in extended Petri Net Specification Format (PNSF) (Kozlowski , et. a!. , 1995).
InputlOu tpu t
m
Configur.,~
Bl od<~OB)
Logic Block (CLB)
Fig. 1. Architecture of FPGA microcontrollers with many of the benefits of other semi-custom logic. The design process is greatly simplified due to the powerful FPGA compilers, as well as some new modem and effective CAD tools, which are recently available. The effective simulation allows Logic Controller to be simulated and debugged before the device is programmed. If design change is needed, it is a simple matter to reedit the original specification and then re-program the former device. It could be expected that after some time industrial electronic oriented Complex PLD and FPGA would be introduced. Advanced PLDs or FPGAs together with modem CAD tools may easily replace some of the old fashioned Programmable Controllers (Mandado, et. a!. , 1996; Adamski and Monteiro, 1996). The Logic Cell Array (LCA) provides fixed array of logical function cells (Fig. 1). The internal function cells are identical and may be con figured (Jenkins, 1994; Xilinx, 1996), allowing flip flops as D, JK, and so on. The LCA design software is called XACT and it supports design entry, design implementation, and design simulation . Design entry occurs by schematic capture (for example OrCAD) or logical equations (for example PALASM or ABEL) . The XACT design netlist, as the XNF file . is passed to the placement and routing software or the simulation software.
4 . METHODOLOGY FOR FPLD&FPGA MODELLING AND AlITOMA TIC SYNTHESIS
4. 1. Examp/e
As an example we have selected the simplified version of Logic Controller taken from the lEC standard (Adamski and Monteiro, 1996) . The system controls the mixing of two bricks of solid material , brought one at time on a bell with weighted quantities of two liquid components A and B (Fig. 2). For the sake of simplicity, we consider only the particular part of Logic Controller, which is described by means of Sequential Function Chart (SFC) (Halang , 1989) (Fig. 3). SFC is a graphical sequencing language, which is based on Grafcet and Petri net (David and AlIa, 1992). It is a flowchart of steps, representing one or more action . Transitions represent events and they define conditions before passing to the next step. The equivalent interpreted Petri net model (Fig. 4) contains level-action (type N) depicted around the places, and stored actions (type RS), invoked by events and set by S-type signal and reset by R-type signal . The external inputs, and
3. APPLICATION SPECIFIC LOGIC CONTROLLERS Safe Petri nets (David and AlIa, 1992) can be viewed as a natural extension to Finite State Machine (FSM) specification. Each place of the Control Interpreted Petri Net (CIPN) is viewed as a local control state. The global state of the controller is given by the PN marking (the distribution of tokens by the places). The Petri net may be directly mapped into the Boolean equations (decision rules) without explicit enumeration of all possible global states and all possible global state changes (Adamski, 1991 ; Bilinski, er.a!. , 1994). The specification is given in terms of the local state changes (local transitions) and different kinds of local state assignment (encoding of places) are used.
240
eventually also internal conditions. that are associated with transitions (events) are represented as logic expressions. bricks
~d
transit detector
"Up" limit sWllch
tipping mixe
"Down" limit SI switch
Fig. 2. Physical model of MIX_2_BRIX control system
Fig. 4 . Equivalent Petri net model of Logic Controller Two components of the control algorithm are implemented on the data path of the controller. that is not consider in the paper. There are: • relational operations used by conditional statements (as a multi-level comparator); • delay operation (as a digit timer, a special purpose counter with comparator).
4.2 Design methodology
The interpreted Petri net model (or equivalent SFC) is translated into a rule-based specification. which is composed of discrete local state symbols, input signal symbols and output signal symbols of controller (Fig. 5). Discrete state transition rules are written in the extended PNSF and describe local state changes. influenced by the external environment. A Petri net
Fig. 3. SFC model of Logic Controller
241
transition with its input and output places is mapped into the particular rule, in which the precondition is formed from its input place symbols, and postcondition respectively from its output place symbols (Adamski, 1991 ; Adamski and Monteiro, 1996). When the preconditions of a rule are satisfied (hold) the postconditions are made true (they will hold). Although it is possible to optimise poorly designed initial descriptions, the compilation process takes much longer, is less predictable and result is usually worse then if the code was well structured. To model an explicit Concurrent State Machine, the current state register, next state, and control outputs are explicitly declared by the designer.
I
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.,..... . . """"'
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.,.....
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4.3. LCA Implementation
This section describes our sub-system for Logic Controllers design with Xilinx FPGAs, such like devices from 3000 and 4000 LCA families. The extended design environment for Xilinx FPGA contains our additional design entry for behavioural specification of Logic Controllers, which are described by means of Petri nets or related SFCs (Petri Nel Specification entry module in Fig. 6). Textual PNSF is translated directly into the netlist in unified Xilinx format. The next steps of the design implementation are realised by the XACT. Functional and timing simulations are performed, for example, in OrCAD or ViewLogic tools.
DESIGN COMPLETE
Fig . 6. Extended design flow Fig. 7 presents the general model of LCA-based Logic Controller. It contains four conceptual blocks that are represented by separated files. The files: inpul.xnf, OUlpul.xnj and ff.xnj describe input buffers, output buffers and flip-flops, respectively. They are identical for all designs, except from a quantity of elements. The structure of the Petri net is directly reflected in the Logic Block .
.cloc k CLK . input ST SI SO WZ WAZ WABZ d TM .output DONE VA VB VC MPl MP O MT MR . plac e STl'.RT ;VEI GH_l'. WEIGH_B FILL BRICK_I DROP_I BRICK_2 DROP_2 MIX TIP RJI.ISE . t r a n s i t i o n Tl T 2 T3 T4 T5 T 6 T7 TB T9 TI 0 .pr edica t e Cl C2 . n et Tl : START* Cl 1- weIGH_A * BRICK_l * S_ MT ; T2: WEIGH_l * WAZ 1- weIGH_B; T3 : WEIGH_B * Wl'~Z 1- FI LL ; T4: BRICK_l * d i - DRO P_I ; T 5: DROP _1 * ! d 1- BP.I CK_2; T 6 : BRICK_2 * d 1- DROP_2 * R_MT; T7: FILL * DROP_ 2 : - MIX * S_MR; TIP ; T B : MIX * TM T9: TI P * S I /- ~~I S E * R_MR ; S T.~T; T I0 : RAISE * so . Moo reOutputs ST.".RT 1 - DONE ; i iEI GH_ A 1- v .:"' ; ;\eI GH_B 1- 'VB; F I L!.. i - vc; BRICK / - MT; T I P / - MPl ; Rll,.ISE / - MP O; . marking ST.~T .predicateDescription Cl ST * SO * ~ Z ; C2
= t.\-Z
'*
File ff.xnf
Rle project.xnf
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F~nf
-
110 Blocks
~
File!2fJ!.c.xnf
b$ Input Block
Register Block
LogiC Block
CLBs
1=
FOe ou.!E..ut.xnf
Output Block
110 Blocks
Fig. 7. Conceptual block-diagram of logic controller with LCA The input data is loaded into the LCA I/O cells, whicb work as the simple, transparency buffers (Fig . 7). The outputs of each input buffer connect to the Configurable Logic Blocks (CLBs) through interconnection resources. The places of the Petri net are treated as distributed local states and assigned to the particular D flip-flops in Register Block . They
! d;
.e
Fig . 5. Logic Controller description in PNSF
242
for MIX place and the JK flip-flop for the registered output MR (Fig. lOc). In addition, there are shown excitation function for D flip-flop for MIX place (Fig. lOd). It relates the description focused in a bold face in the Fig. 8 as rule P9.
are labelled by the particular place names, for example START, WEIGH_A. etc. The registered outputs (MR and MT) are assigned to the separated JK flip-flops . Signals S_MR and S_MT are connected to J excitation inputs, and signals R_MR and R_MT to K inputs, respectively.
In our experimental first version, we use XNF description only with textual equivalents of twoinput gates, eventually with some inverted inputs (Fig. 9, Fig. 10d). The optimisation is performed before mapping to CLBs by XACT system.
~~IS E
* so + START * ! (ST * so • WZ) \ - @START; p2: START' ST • sO • WZ + WEIGH_A' !WAZ \- @WEIGH_A; p3: WEIGH_A' WAZ + WEIGH_B' !WABZ t - @WEIGH_B; P4: WEIGH_B' WABZ + FILL * ! (DROP_2*WZ* !d) 1- @FILL; ps: START' ST*SO*WZ + BRICK_l * !d 1- @BRICK_l; P6: BRICK_l * d + DROP_l * d 1- @DROP_l; p 7: DROP_l * !d + BRICK_2' !d 1@BRICK_2; P8: BRICK_2 * d + DROP_2 * ! (FILL*WZ*!d) 1- @DROP_2; P9: PILL * DROP_2 * WZ * Id + MIX· ITM
PI:
a) SYM, TM , IBUF , SCHNM=IBUF, LIBVER=2 .0.0 PIN , I , I, TM_PAD PIN, 0, 0, TM END
EXT, TM PAD, I
b) SYM, PIN, PIN, END EXT ,
1- @MIX;
PlO: MIX * TM + TIP * !Sl 1- @TIP; Pll: TIP * SI + RAISE * !SO 1- @RAISE; ROl: START' ST * SO * WZ 1- S_MT; BRICK_2 * d 1- R_MT; R02: PILL • DROP_2 * WZ * Id 1- S_MR; TIP * Sll- R_MR; +
or
• and
! not
MR , OBUF , SCHNM=OBUF, LIBVER=2.0.0 I, I, MR 0, 0, MR_PAD MR PAD,
°
c) SYM, MIX_FF, FDC, LIBVER=2.0 .0, SYSTEM=XMACRO PIN, Q, 0, MIX PIN, D, I, MIX_D PIN , C, I, CLK PIN, CLR, I , GND
/- y1eld
Fig. 8. Implementation description
END
SYM, MR_FF, FJKC, LIBVER=2.0.0 , SYSTEM=XMACRO PIN, Q, 0, MR PIN, J, I, MR_SET PIN, K, I, MR_RESET PIN, C, I, CLK PIN, CLR, I, GND
The logic decision rules, which reflect exactly the description in PNSF, are transformed from the transition-oriented form T (Fig. 5) into the placeoriented description P (Fig. 8). The simplest technique for Petri net place encoding is to use oneto-one mapping of places onto flip-flops in the style of one-hot state assignment. The presented approach to synthesizing a controller is based on creating a one-to-one direct mapping between the Petri net (Fig. 4) and the hardware realisation (Fig. 9).
END
d) SYM, PIN, PIN, PIN, END SYM, PIN, PIN, PIN,
.J
lIIr_D - m.L. DACI'_.2- WZ·!d • .MZ:r-.t'fJI RAlSE_D'"' 'UP. 51 • RAI2 •.'9)
1033, AND, SCHNM=AND2, LIBVER=2.0 .0 10, I, FILL 11, I, DROP_2 0, 0, 1033 1034, AND , SCHNM=AND2, LIBVER=2.0.0 10 , I, 10 33 Il, I, WZ 0, 0, 1034
END
SYM, PIN, PIN, PIN,
1035, AND, SCHNM=AND2Bl, LIBVER=2.0 .0 10, I, d, , INV 11, I, 1034 0 , 0, 1035
END
SYM, PIN, PIN, PIN,
bJ
1036 , 10, I 11, I 0, 0,
AND, SCHNM=AND2Bl, LIBVER=2 .0.0 , TM, , INV , MIX 1036
END
SYM, PIN, PIN, PIN,
Fig. 9. Implementation of rules: a) P9, b) R02
MIX_D , OR , SCHNM=OR2, LIBVER=2.0.0 10, I , 1035 11, I , 1036 0, 0, MIX_D
END
As an illustration, Fig. 10 depicts only the selected parts of the XNF files . We demonstrate: the input buffer Specification of TM input (Fig. lOa), the output buffer of MR output (Fig. lOb), the D flip-flop
Fig. 10. Selected parts of the XNF fJ.les: a) input.xnf, b) output,xnj, c) ff.xnf, d) logic.xnj
243
REFERENCES
It is easy to introduce to the design an operational part, e.g. input comparator and other functional blocks, like timers, from the user-defined library.
Adamski M. (1991). "Parallel Controller Implementation using Standard PLD Software", In FPGAs, eds. W.R.Moore, W.Luk, (from the 1991 Oxford International Workshop on Field Programmable Logic and Applications), pp. 296-304, Abingdon EE&CS, Abingdon, England Adamski MA and J.L.Monteiro, (1996), "Declarative SpeCification of System Independent Logic Controller Programs", Proc. of the IEEE International Symposium on Industrial Electronics ISIE'96, Warsaw, Poland, pp.305-31O Adamski M. and M.Wegrzyn, (1994), "Hierarchically Structured Coloured Petri Net Specification and Validation of Concurrent Controllers", Proc. of the 39. Internationales Wissenschaftliches Kolloquium IWK'94, Technische Universitat Ilmenau, Germany, 27-30.09.1994, Band 1, pp.517-522 Bilinski K., M.Adamski, 1.M.Saul and E.L.Dagless, (1994), "Petri net based algorithms for parallel controller synthesis", lEE Proceedings-E, Computers and Digital Techniques, Vol.141, No.6, Nov. 1994, pp.405-412 David R. and H.Alla, (1992), Petri Nets and Grafcet, Prentice Hall, New York Femandes J.M., M.Adamski and AJ.Proenr,:a, (1996), "VHDL Generation from Hierarchical Petri Net Specifications of Parallel ContrOllers", lEE Proceedings-E, Computers and Digital Techniques, Vol.l44 Halang WA, (1989), "Languages and Tools for the Graphical and Textual System Independent Programming of Programmable Logic Controllers", Microprocessing and Microprogramming, North Holland, Vol.27, pp.583-590 Jenkins J.H., (1994), Designing with FPGAs and CPWs, Prentice Hall, Englewood Cliffs, New Jersey Jiang 1. and DJ. Holding, (1996), "The Formalisation and Analysis of Sequential Function Charts using a Petri Net Approach", 13 th World Congress of IFAC, International Federation Of Automatic Control, IFAC'96, San Francisco, CA, USA, VoI.J, Discrete Event Systems, pp.513-518 Kozlowski T., E.L.Dagless, J.M.Saul, M.Adarnski and J .Szajna, (1995), "Parallel controller syntheSis using Petri nets", lEE Proceedings-E, Computers and Digital Techniques, Vo1.142, NoA, July 1995, pp.263-271 Mandado E., J .Marcos and S.A.Perez, (1996), Programmable Logic Devices and Logic Controllers, Prentice Hall, London Wegrzyn M. , P.Wolanski, MAAdarnski and J.L.Monteiro, (1996), "Field Progranunable Device as a Logic Controller", Proc. of the Conference on Automatic Control - Control '96, Oporto, Portugal, 11-13.09.1996, YoU, pp.715-720 Xilinx, Inc, (1996), The Programmable Logic Data Book, San Jose, California
4.4. Experimental results
The design uses only fourteen logic modules (Fig. 11) for the considered example and easily fits less then a quarter of the LCA 3000 integrated circuit. The XACT software merged the registered outputs with registered state variables. For example, the registered state signal RAISE replaces the output signal MPO. Some places need for direct mapping more than one CLB, for example the place MIX.
5. CONCLUSIONS We have introduced a systematic approach, which allows one to construct simple logic controllers implemented as FPGA. We particularly have demonstrated how to use XilinxIXACT and Field Programmable Logic (FPL) oriented algorithms to manage the design of flexible Application Specific Logic Controllers. Design summary: Part type=3020PC68-100 17 of 58 1/0 pins used 14 of 64 CLBs used (13 CLB flipflops) Clock Signals Report: Signal Name = CLK; Fan Out = 13 The signals have been merged together as a result: Signal = RAISE Replaces Signal MPO Replaces Signal Signal = TIP MP1 Signal = VC Replaces Signal FILL Signal = VB Replaces Signal WEIGH_B Replaces Signal Signal VA WEIGH_A Signal = START Replaces Inv. Signal = DONE
Fig. 11. Summary of implementation The proposed technique can be successfully used both for simulation and automatic synthesis. Initially, the behavioural specifications of Logic Controller can be represented graphically in different fashions, for example as Petri nets, Grafcets, SFCs, linked state diagrams, linked ASMcharts, and symbolic transition tables (transition lists). All these kinds of initial description can be easily represented in our symbolic unified format, then formally verified and partially optimised. The common internal specification is translated automatically into FPGA, for example Xii in x LCA. The graphical entries for Petri nets and SFC are under development.
r
The research was supported by Polish State Committee for Scientific Research and Portuguese Ministry of Science.
244
RECONFIGURABLE LOGIC CONTROLLER WITH FPGA
Marek Wegrzynl), Prof. Marian A.Adamski1,2), Prof. Joao L.Monteiro
2
)
Zielona Gora Technical University, Computer Eng. & Electronics Dept. 50. Podgoma Street, 65-246 Zielona Gora, Poland tel. (+4868) 254831 x.526; fax (+4868) 244733, 253944 E-mail: [email protected]. [email protected] 2)Universidade do Minho, Braga-Guimaraes, Departamento de Electronica Industrial Azurem, 4800 Guimaraes, Portugal tei. (+35153) 510190, fax (+35153) 510189,514400 E-mail: [email protected] J)
Abstract: An implemented design framework contains the Programmable Logic based synthesis of rule-based descriptions that are obtained from several specification models of Concurrent Controllers (for example: Control Interpreted Petri net, Grafcet or IEC 1131-3 Sequential Function Chart). The specification in the form of symbolic conditional decision rules is transformed into a format that is accepted by standard FPLD & FPGA simulators and synthesizers, for example OrCAD or VHDL. The Concurrent State Machine model of Logic Controller is verified using the well-developed Petri net theory. and then it is translated through automated processes into selected FPGA specification format, for example Xilinx netlist format (XNF). Keywords: Custom VLSI devices. Industrial process control, Petri Net, Sequential Function Chart (SFC), Logic Controllers. FPGAs
The translation is straightforward and simple. The general 'If-Then' Decision Rules (non-procedural conditional statements) may be mapped into Xilinx format constructs directly, or after some simple additional transformations. The final multi-level combinational optimisation, placement and routing are performed by standard design tools.
1. INTRODUCTION
The main aim of this paper is the practical, direct mapping of a Logic Controller program into a Field Programmable Gate Arrays (FPGAs). In one of the possible methodologies, we apply a rule-based logic specification format and direct mapping of Petri net into the hardware library, by means of the Xilinx Automated CAE Tools (XACT). Proposed Decision Rule Specification, as a textual equivalent of Petri net can be also easily modelled using other hardware Description Languages (HDL), particularly with VHDL (Wegrzyn, et.al. , 1996). The experimental results show that our approaches may produce economical and flexible LCA implementations of relatively simple, dedicated Logic Controllers .
2. FPGA AS A LOGIC CONTROLLER FPGAs are electronic circuits, which can be reconfigured by the user to perform a particular combinational or registered logic function (Fig. 1). As user-programmable Application Specific Integrated Circuits, they provide a valuable compromise which combines the benefits of standard
239
Svrnbolic Petri net description is based on the c~ncept of extended production rules, described by means of the conditional logic. The first implementation was performed in Logician CAD system (Adamski, 1991). The syntax of language was revised over years. Some major syntax modifications have been made in PARIS system. and a new description format called the Petri Net Specification Format (PNSF) for VLSI design was introduced (Kozlowski , et.a!. , 1995). The CONPAR specification format (Fernandes, et.a!. , 1996) is consistent with previously introduced rule-based specification languages and was also created mainly as a bridge between textual logic description of Petri nets and their VHDL models. Transition rules are usually treated as production rules Cif-then' non procedural statements). The rule-based description, supported by means of logic deduction techniques (Gentzen natural logic calculus), was recently presented in Programmable Logic Controller design context (Adamski and Monteiro, 1996). A Petri net can be first expressed graphically, and then manually or automatically translated into an equivalent textual format. Some graphical Petri net tools are under development. The specifications with sound Grafcet (David and AlIa 1992) or SFC (lEC, 1992; Halang, 1989; Jiang and Holding, 1992) are treated as special forms of Control Interpreted safe Petri Nets. We have implemented an intermediate rule-based language in extended Petri Net Specification Format (PNSF) (Kozlowski , et. a!. , 1995).
InputlOu tpu t
m
Configur.,~
Bl od<~OB)
Logic Block (CLB)
Fig. 1. Architecture of FPGA microcontrollers with many of the benefits of other semi-custom logic. The design process is greatly simplified due to the powerful FPGA compilers, as well as some new modem and effective CAD tools, which are recently available. The effective simulation allows Logic Controller to be simulated and debugged before the device is programmed. If design change is needed, it is a simple matter to reedit the original specification and then re-program the former device. It could be expected that after some time industrial electronic oriented Complex PLD and FPGA would be introduced. Advanced PLDs or FPGAs together with modem CAD tools may easily replace some of the old fashioned Programmable Controllers (Mandado, et. a!. , 1996; Adamski and Monteiro, 1996). The Logic Cell Array (LCA) provides fixed array of logical function cells (Fig. 1). The internal function cells are identical and may be con figured (Jenkins, 1994; Xilinx, 1996), allowing flip flops as D, JK, and so on. The LCA design software is called XACT and it supports design entry, design implementation, and design simulation . Design entry occurs by schematic capture (for example OrCAD) or logical equations (for example PALASM or ABEL) . The XACT design netlist, as the XNF file . is passed to the placement and routing software or the simulation software.
4 . METHODOLOGY FOR FPLD&FPGA MODELLING AND AlITOMA TIC SYNTHESIS
4. 1. Examp/e
As an example we have selected the simplified version of Logic Controller taken from the lEC standard (Adamski and Monteiro, 1996) . The system controls the mixing of two bricks of solid material , brought one at time on a bell with weighted quantities of two liquid components A and B (Fig. 2). For the sake of simplicity, we consider only the particular part of Logic Controller, which is described by means of Sequential Function Chart (SFC) (Halang , 1989) (Fig. 3). SFC is a graphical sequencing language, which is based on Grafcet and Petri net (David and AlIa, 1992). It is a flowchart of steps, representing one or more action . Transitions represent events and they define conditions before passing to the next step. The equivalent interpreted Petri net model (Fig. 4) contains level-action (type N) depicted around the places, and stored actions (type RS), invoked by events and set by S-type signal and reset by R-type signal . The external inputs, and
3. APPLICATION SPECIFIC LOGIC CONTROLLERS Safe Petri nets (David and AlIa, 1992) can be viewed as a natural extension to Finite State Machine (FSM) specification. Each place of the Control Interpreted Petri Net (CIPN) is viewed as a local control state. The global state of the controller is given by the PN marking (the distribution of tokens by the places). The Petri net may be directly mapped into the Boolean equations (decision rules) without explicit enumeration of all possible global states and all possible global state changes (Adamski, 1991 ; Bilinski, er.a!. , 1994). The specification is given in terms of the local state changes (local transitions) and different kinds of local state assignment (encoding of places) are used.
240
eventually also internal conditions. that are associated with transitions (events) are represented as logic expressions. bricks
~d
transit detector
"Up" limit sWllch
tipping mixe
"Down" limit SI switch
Fig. 2. Physical model of MIX_2_BRIX control system
Fig. 4 . Equivalent Petri net model of Logic Controller Two components of the control algorithm are implemented on the data path of the controller. that is not consider in the paper. There are: • relational operations used by conditional statements (as a multi-level comparator); • delay operation (as a digit timer, a special purpose counter with comparator).
4.2 Design methodology
The interpreted Petri net model (or equivalent SFC) is translated into a rule-based specification. which is composed of discrete local state symbols, input signal symbols and output signal symbols of controller (Fig. 5). Discrete state transition rules are written in the extended PNSF and describe local state changes. influenced by the external environment. A Petri net
Fig. 3. SFC model of Logic Controller
241
transition with its input and output places is mapped into the particular rule, in which the precondition is formed from its input place symbols, and postcondition respectively from its output place symbols (Adamski, 1991 ; Adamski and Monteiro, 1996). When the preconditions of a rule are satisfied (hold) the postconditions are made true (they will hold). Although it is possible to optimise poorly designed initial descriptions, the compilation process takes much longer, is less predictable and result is usually worse then if the code was well structured. To model an explicit Concurrent State Machine, the current state register, next state, and control outputs are explicitly declared by the designer.
I
.,Ubr..,.
I
.,..... . . """"'
•
.,.....
Ub
•
4.3. LCA Implementation
This section describes our sub-system for Logic Controllers design with Xilinx FPGAs, such like devices from 3000 and 4000 LCA families. The extended design environment for Xilinx FPGA contains our additional design entry for behavioural specification of Logic Controllers, which are described by means of Petri nets or related SFCs (Petri Nel Specification entry module in Fig. 6). Textual PNSF is translated directly into the netlist in unified Xilinx format. The next steps of the design implementation are realised by the XACT. Functional and timing simulations are performed, for example, in OrCAD or ViewLogic tools.
DESIGN COMPLETE
Fig . 6. Extended design flow Fig. 7 presents the general model of LCA-based Logic Controller. It contains four conceptual blocks that are represented by separated files. The files: inpul.xnf, OUlpul.xnj and ff.xnj describe input buffers, output buffers and flip-flops, respectively. They are identical for all designs, except from a quantity of elements. The structure of the Petri net is directly reflected in the Logic Block .
.cloc k CLK . input ST SI SO WZ WAZ WABZ d TM .output DONE VA VB VC MPl MP O MT MR . plac e STl'.RT ;VEI GH_l'. WEIGH_B FILL BRICK_I DROP_I BRICK_2 DROP_2 MIX TIP RJI.ISE . t r a n s i t i o n Tl T 2 T3 T4 T5 T 6 T7 TB T9 TI 0 .pr edica t e Cl C2 . n et Tl : START* Cl 1- weIGH_A * BRICK_l * S_ MT ; T2: WEIGH_l * WAZ 1- weIGH_B; T3 : WEIGH_B * Wl'~Z 1- FI LL ; T4: BRICK_l * d i - DRO P_I ; T 5: DROP _1 * ! d 1- BP.I CK_2; T 6 : BRICK_2 * d 1- DROP_2 * R_MT; T7: FILL * DROP_ 2 : - MIX * S_MR; TIP ; T B : MIX * TM T9: TI P * S I /- ~~I S E * R_MR ; S T.~T; T I0 : RAISE * so . Moo reOutputs ST.".RT 1 - DONE ; i iEI GH_ A 1- v .:"' ; ;\eI GH_B 1- 'VB; F I L!.. i - vc; BRICK / - MT; T I P / - MPl ; Rll,.ISE / - MP O; . marking ST.~T .predicateDescription Cl ST * SO * ~ Z ; C2
= t.\-Z
'*
File ff.xnf
Rle project.xnf
!88888!
F~nf
-
110 Blocks
~
File!2fJ!.c.xnf
b$ Input Block
Register Block
LogiC Block
CLBs
1=
FOe ou.!E..ut.xnf
Output Block
110 Blocks
Fig. 7. Conceptual block-diagram of logic controller with LCA The input data is loaded into the LCA I/O cells, whicb work as the simple, transparency buffers (Fig . 7). The outputs of each input buffer connect to the Configurable Logic Blocks (CLBs) through interconnection resources. The places of the Petri net are treated as distributed local states and assigned to the particular D flip-flops in Register Block . They
! d;
.e
Fig . 5. Logic Controller description in PNSF
242
for MIX place and the JK flip-flop for the registered output MR (Fig. lOc). In addition, there are shown excitation function for D flip-flop for MIX place (Fig. lOd). It relates the description focused in a bold face in the Fig. 8 as rule P9.
are labelled by the particular place names, for example START, WEIGH_A. etc. The registered outputs (MR and MT) are assigned to the separated JK flip-flops . Signals S_MR and S_MT are connected to J excitation inputs, and signals R_MR and R_MT to K inputs, respectively.
In our experimental first version, we use XNF description only with textual equivalents of twoinput gates, eventually with some inverted inputs (Fig. 9, Fig. 10d). The optimisation is performed before mapping to CLBs by XACT system.
~~IS E
* so + START * ! (ST * so • WZ) \ - @START; p2: START' ST • sO • WZ + WEIGH_A' !WAZ \- @WEIGH_A; p3: WEIGH_A' WAZ + WEIGH_B' !WABZ t - @WEIGH_B; P4: WEIGH_B' WABZ + FILL * ! (DROP_2*WZ* !d) 1- @FILL; ps: START' ST*SO*WZ + BRICK_l * !d 1- @BRICK_l; P6: BRICK_l * d + DROP_l * d 1- @DROP_l; p 7: DROP_l * !d + BRICK_2' !d 1@BRICK_2; P8: BRICK_2 * d + DROP_2 * ! (FILL*WZ*!d) 1- @DROP_2; P9: PILL * DROP_2 * WZ * Id + MIX· ITM
PI:
a) SYM, TM , IBUF , SCHNM=IBUF, LIBVER=2 .0.0 PIN , I , I, TM_PAD PIN, 0, 0, TM END
EXT, TM PAD, I
b) SYM, PIN, PIN, END EXT ,
1- @MIX;
PlO: MIX * TM + TIP * !Sl 1- @TIP; Pll: TIP * SI + RAISE * !SO 1- @RAISE; ROl: START' ST * SO * WZ 1- S_MT; BRICK_2 * d 1- R_MT; R02: PILL • DROP_2 * WZ * Id 1- S_MR; TIP * Sll- R_MR; +
or
• and
! not
MR , OBUF , SCHNM=OBUF, LIBVER=2.0.0 I, I, MR 0, 0, MR_PAD MR PAD,
°
c) SYM, MIX_FF, FDC, LIBVER=2.0 .0, SYSTEM=XMACRO PIN, Q, 0, MIX PIN, D, I, MIX_D PIN , C, I, CLK PIN, CLR, I , GND
/- y1eld
Fig. 8. Implementation description
END
SYM, MR_FF, FJKC, LIBVER=2.0.0 , SYSTEM=XMACRO PIN, Q, 0, MR PIN, J, I, MR_SET PIN, K, I, MR_RESET PIN, C, I, CLK PIN, CLR, I, GND
The logic decision rules, which reflect exactly the description in PNSF, are transformed from the transition-oriented form T (Fig. 5) into the placeoriented description P (Fig. 8). The simplest technique for Petri net place encoding is to use oneto-one mapping of places onto flip-flops in the style of one-hot state assignment. The presented approach to synthesizing a controller is based on creating a one-to-one direct mapping between the Petri net (Fig. 4) and the hardware realisation (Fig. 9).
END
d) SYM, PIN, PIN, PIN, END SYM, PIN, PIN, PIN,
.J
lIIr_D - m.L. DACI'_.2- WZ·!d • .MZ:r-.t'fJI RAlSE_D'"' 'UP. 51 • RAI2 •.'9)
1033, AND, SCHNM=AND2, LIBVER=2.0 .0 10, I, FILL 11, I, DROP_2 0, 0, 1033 1034, AND , SCHNM=AND2, LIBVER=2.0.0 10 , I, 10 33 Il, I, WZ 0, 0, 1034
END
SYM, PIN, PIN, PIN,
1035, AND, SCHNM=AND2Bl, LIBVER=2.0 .0 10, I, d, , INV 11, I, 1034 0 , 0, 1035
END
SYM, PIN, PIN, PIN,
bJ
1036 , 10, I 11, I 0, 0,
AND, SCHNM=AND2Bl, LIBVER=2 .0.0 , TM, , INV , MIX 1036
END
SYM, PIN, PIN, PIN,
Fig. 9. Implementation of rules: a) P9, b) R02
MIX_D , OR , SCHNM=OR2, LIBVER=2.0.0 10, I , 1035 11, I , 1036 0, 0, MIX_D
END
As an illustration, Fig. 10 depicts only the selected parts of the XNF files . We demonstrate: the input buffer Specification of TM input (Fig. lOa), the output buffer of MR output (Fig. lOb), the D flip-flop
Fig. 10. Selected parts of the XNF fJ.les: a) input.xnf, b) output,xnj, c) ff.xnf, d) logic.xnj
243
REFERENCES
It is easy to introduce to the design an operational part, e.g. input comparator and other functional blocks, like timers, from the user-defined library.
Adamski M. (1991). "Parallel Controller Implementation using Standard PLD Software", In FPGAs, eds. W.R.Moore, W.Luk, (from the 1991 Oxford International Workshop on Field Programmable Logic and Applications), pp. 296-304, Abingdon EE&CS, Abingdon, England Adamski MA and J.L.Monteiro, (1996), "Declarative SpeCification of System Independent Logic Controller Programs", Proc. of the IEEE International Symposium on Industrial Electronics ISIE'96, Warsaw, Poland, pp.305-31O Adamski M. and M.Wegrzyn, (1994), "Hierarchically Structured Coloured Petri Net Specification and Validation of Concurrent Controllers", Proc. of the 39. Internationales Wissenschaftliches Kolloquium IWK'94, Technische Universitat Ilmenau, Germany, 27-30.09.1994, Band 1, pp.517-522 Bilinski K., M.Adamski, 1.M.Saul and E.L.Dagless, (1994), "Petri net based algorithms for parallel controller synthesis", lEE Proceedings-E, Computers and Digital Techniques, Vol.141, No.6, Nov. 1994, pp.405-412 David R. and H.Alla, (1992), Petri Nets and Grafcet, Prentice Hall, New York Femandes J.M., M.Adamski and AJ.Proenr,:a, (1996), "VHDL Generation from Hierarchical Petri Net Specifications of Parallel ContrOllers", lEE Proceedings-E, Computers and Digital Techniques, Vol.l44 Halang WA, (1989), "Languages and Tools for the Graphical and Textual System Independent Programming of Programmable Logic Controllers", Microprocessing and Microprogramming, North Holland, Vol.27, pp.583-590 Jenkins J.H., (1994), Designing with FPGAs and CPWs, Prentice Hall, Englewood Cliffs, New Jersey Jiang 1. and DJ. Holding, (1996), "The Formalisation and Analysis of Sequential Function Charts using a Petri Net Approach", 13 th World Congress of IFAC, International Federation Of Automatic Control, IFAC'96, San Francisco, CA, USA, VoI.J, Discrete Event Systems, pp.513-518 Kozlowski T., E.L.Dagless, J.M.Saul, M.Adarnski and J .Szajna, (1995), "Parallel controller syntheSis using Petri nets", lEE Proceedings-E, Computers and Digital Techniques, Vo1.142, NoA, July 1995, pp.263-271 Mandado E., J .Marcos and S.A.Perez, (1996), Programmable Logic Devices and Logic Controllers, Prentice Hall, London Wegrzyn M. , P.Wolanski, MAAdarnski and J.L.Monteiro, (1996), "Field Progranunable Device as a Logic Controller", Proc. of the Conference on Automatic Control - Control '96, Oporto, Portugal, 11-13.09.1996, YoU, pp.715-720 Xilinx, Inc, (1996), The Programmable Logic Data Book, San Jose, California
4.4. Experimental results
The design uses only fourteen logic modules (Fig. 11) for the considered example and easily fits less then a quarter of the LCA 3000 integrated circuit. The XACT software merged the registered outputs with registered state variables. For example, the registered state signal RAISE replaces the output signal MPO. Some places need for direct mapping more than one CLB, for example the place MIX.
5. CONCLUSIONS We have introduced a systematic approach, which allows one to construct simple logic controllers implemented as FPGA. We particularly have demonstrated how to use XilinxIXACT and Field Programmable Logic (FPL) oriented algorithms to manage the design of flexible Application Specific Logic Controllers. Design summary: Part type=3020PC68-100 17 of 58 1/0 pins used 14 of 64 CLBs used (13 CLB flipflops) Clock Signals Report: Signal Name = CLK; Fan Out = 13 The signals have been merged together as a result: Signal = RAISE Replaces Signal MPO Replaces Signal Signal = TIP MP1 Signal = VC Replaces Signal FILL Signal = VB Replaces Signal WEIGH_B Replaces Signal Signal VA WEIGH_A Signal = START Replaces Inv. Signal = DONE
Fig. 11. Summary of implementation The proposed technique can be successfully used both for simulation and automatic synthesis. Initially, the behavioural specifications of Logic Controller can be represented graphically in different fashions, for example as Petri nets, Grafcets, SFCs, linked state diagrams, linked ASMcharts, and symbolic transition tables (transition lists). All these kinds of initial description can be easily represented in our symbolic unified format, then formally verified and partially optimised. The common internal specification is translated automatically into FPGA, for example Xii in x LCA. The graphical entries for Petri nets and SFC are under development.
r
The research was supported by Polish State Committee for Scientific Research and Portuguese Ministry of Science.
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