Silicon Multinomial Conjunctoid Statistical Learning Modules

Silicon Multinomial Conjunctoid Statistical Learning Modules

Silicon Multinomial Conjunctoid Statistical Learning Modules Yoshiyasu Takefuji, Robert J. Jannarone, Tatung Chen, and Yong B. Cho Center for Ma...

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Silicon

Multinomial

Conjunctoid

Statistical

Learning

Modules

Yoshiyasu Takefuji, Robert J. Jannarone, Tatung Chen, and Yong B. Cho Center for Machine Intelligence Department of Electrical and Computer Engineering University of South Carolina Columbia, SC 29208 (803)777-5099 Abstract Muttinomial Conjunctoids are supervised statistical modules that learn the relationships among binary events. This paper describes analog and digital multinomial c o n j u n c t o i d modules that are currently under silicon fabrication using a MOSIS program based on CMOS tcchnology. The digital m u h i n o m i a l conjunctoid module is featured, but digital and ~nalog modules are compared as well. The feasibility of large scale m u l t i n o m i a l m a c h i n e s arc discussed. Detailed designs for p a r a m e t e r estimation modules and i n d i s p e n s a b l e digital components are also given. Figure 1 shows a simple schematic diagram for a digital multinomial conjunctoid module. The diagram is composed of interconnections among 2 M+N parameter storage units, called REGs, paramctcr estimators PEA0 and PLA1, and a multiplexer MAX unit. The circuit in Figure 1 is based on M = 3 and N = 2, so that 25 = 32 parameter units are provided. In Figure 1 PLA0 and PLAI units are used to compute Otol d + Luw 1 + L Given an input w value, the contents of a single REG having an ID matching the input data value w are first sent to the PLA0 unit. The PLA0 unit then increases the corresponding parameter value in accordance with L and Uw = 1. Meanwhile, the contents of three REGs having the same x ID as w but a different v 1D are sequentially sent to the PLA1 unit. The PLA1 unit decreases their parameter values in accordance with L and uw = 0. The rest of parameter values are not changed at all. Thus, the PLA0 unit computes Ctol d + L Ctol d C~new = 1 + L , and the PLA1 unit computes e~new - 1 + L O~ne w

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Just as the experience segment of Figure 1 executes one learning cycle for each input (w, LI learning unit, the performance segment executes one behavior cycle for each input x value. At the beginning of each behavior cycle, the parameter decoder uses the input x value to admit only the 2 N parameter estimates, { a f x . v ) , v e B M+N } associated with the input x value, among the 2 M+N parameter estimates coming from the experience segment. In Figure 1 the 2 N parameter estimates are sequentially transferred through 3-state buses to the MAX unit. The MAX unit, in turn, identifies the y value having the highest parameter estimate value. Figure 2 shows a functional diagram of the MAX unit. The output pattern accumulator (REGISTER~ in Figure 2 selects and stores the single estimate coming from the parameter storage unit's REG in Figure 1 that corresponds to its associated y value. The output comparator (MAX unit) in Figure 2 sequentially compares the REGISTER contents with each REG value, retaining the larger of the two in the REGISTER. Thus, the MAX unit identifies the single output pattern having the highest estimated parameter value (or any one of lhc highestvalued accumulators in case of a tie) and outputs its y value. The largest parameter value among thc 2 N p a r a m e t e r estimates will be retained in the REGISTER. Each b e h a v i o r cycle is quick because the oulput comparator's sole task is to locate the address containing the largest value among 2 N words of storage. A simple multinomial conjunctoid module based on digital logic design is pictured in Figure 3~a). In l~rder to investigate the feasibility of a large silicon multinomial conjunctoid machine bascd on CMOS VLSI technology, analog mulfinomial conjunctoid modules are also being investigated. One such module is picturcd in Figure 3(b). Both prototype modules are under silicon fabrication using a MOSIS program. The silicon size of the digital multinomial conjunctoid module in Figure 3 is about 20 times bigger than that of analog multinomial module. The main reason for the size difference is that the analog parameter estimation circuit is much simpler. However thc manipulation of L in the analog module is hardcr than that of the digital m u l t i n o m i a l conjunctoid module. Also, the resolution of parameter values is limited in analog modules. On the other hand, digital modules require more silicon area but have no significant limitations in the p a r a m e t e r resolution. We are currcntly exploring design for much larger multinomial conjunctoid modules. One possibility that we are pursuing the location of the parameter storage units outside the parameter estimation chip. When we can install the parameter storage units outside of a chip, 2 N memory accesses are only required to update the parameters for a single stimulus w.

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