Control Engineering Practice 6 (1998) 879—887
The application of reconfigurable logic to controller design Marek Wegrzyn!,*, Marian A. Adamski!, Joao L. Monteiro" ! Zielona Gora Technical University, Computer Eng. and Electronics Dept., 50. Podgorna Street, 65-246 Zielona Gora, Poland " University of Minho, GuimaraJ es, Industrial Electronics Dept., Campus Azure´ m, 4800 GuimaraJ es, Portugal
Abstract This paper presents a framework that performs the programmable logic synthesis of rule-based descriptions of concurrent controllers. These descriptions can be obtained from several specification models of those controllers (for example, Control Interpreted Petri net, Grafcet or the IEC 1131-3 Sequential Function Chart). The internal description, in the form of symbolic conditional decision rules, is then transformed into a format that is accepted by standard FPLD and FPGA simulators and synthesisers, for example OrCAD or VHDL. The concurrent state machine model of the logic controller is verified using the well-developed Petri-net theory, and then it is translated through automated processes into a selected FPGA specification format, for example the Xilinx netlist format (XNF). This paper presents part of a broad project in the field of hardware/software co-design. The main purpose is to develop different implementations of controllers using a simple, standard and well-known design methodology like SFC (Grafcet) or Petri nets. The paper deals exclusively with the design of FPGA-based controllers. ( 1998 Published by Elsevier Science Ltd. All rights reserved. Keywords: Industrial process control; Petri nets; sequential function charts (SFC); logic controllers; FPGAs
1. Introduction A mechanical—electronic system, to be controlled, contains sensors and actuators that allow one to observe it and control its operation. The increasing importance of electronics in the control tasks is mainly due to the improvements in miniaturisation and microelectronics. Furthermore, the use of discrete digital control has proven to be cost-effective and reliable. On the other hand, rapid design adaptation is very often necessary in order to cope with the flexibility of modern process-control systems. The use of generalpurpose design languages and strategies allows the specification of control algorithms to be defined by less experienced users; this fact has been one of the reasons for the diffusion of the use of PLCs. Nevertheless, this is often not the best technical solution for a discrete controller. In fact, it is possible to replace the classical programmable logic controller with a hierarchical network of easily reprogrammable application-specific logic controllers. They can be modelled, simulated and synthesised in the
*Corresponding author. E-mail:
[email protected]
user-friendly hardware description language (HDL) environment. Since this is a new research area, there have been only a few papers directly related to it, such as, for example, Adamski, 1991; Mandado et al., 1996. Designing industrial logic controllers with reprogrammable Xilinx FPGAs has been proposed by the authors of this paper. The same design language can be used for system design, simulation and modelling, and for test development. The unified design environment makes much easier to reuse existing designs, and to work on large designs in a top-down manner. The proposed approach is particularly useful for distributed logic controller design, since sub-controllers may be redesigned and combined into a larger programmable device or gate array. The use of state-of-the-art Xilinx chips makes it possible to design flexible and distributed logic control systems. The specific application often dictates the system design requirements, such as modularity and flexibility. In general, the design procedure involves the integration of analytical and graphical descriptions. Graphical descriptions, such as control-interpreted Petri nets, Grafcet, Grafchart, and SFC, provide established techniques for proper system designs. They have helped industrial engineers to understand the system behaviour and performance over many years.
0967-0661/98/$ — See front matter ( 1998 Published by Elsevier Science Ltd. All rights reserved PII: S 0 9 6 7 - 0 6 6 1 ( 9 8 ) 0 0 0 7 5 - 6
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A behavioural representation describes the system’s functionality independently of its implementation. It treats a system as a black box, and defines how the black box responds to any combination of input values. The process of designing a system proceeds from a behavioural specification (SFC diagram or Petri net) to a programmable logic implementation (FPGA). A design in purely behavioural form, like a Petri net, is converted into an intermediate rule-based description, void of any technology-specific implementation details. The final FPGA implementation is generated by automatic synthesis using CAD tools, instead of manual, tedious design process. The textual format serves as a bridge with some related university tools. The main aim of this paper is the practical, direct mapping of a logic controller program into field programmable gate arrays (FPGAs). In one of the possible methodologies, a rule-based logic specification format and direct mapping of Petri nets into the hardware library, by means of the Xilinx Automated CAE Tools (XACT), is applied. The proposed decision rule specification, as a textual equivalent of the Petri net, can also be easily modelled using other hardware description languages (HDL), particularly with VHDL (Wegrzyn et al., 1996). The experimental results show that new approaches may produce economical and flexible LCA implementations of relatively simple, dedicated logic controllers. The translation is straightforward and simple. The general ‘If—Then’ decision rules (non-procedural conditional statements) may be mapped directly into Xilinx format constructs, or after some simple additional transformations. The final multi-level combinational optimisation, placement and routing are performed by standard design tools (Wegrzyn et al., 1997). Simple autonomous sub-systems are created in form of encapsulated units in a very comfortable and less expensive way, by means of FPGA and CPLD applications supported by HDL tools. The integration of these devices with microprocessors and microcontrollers in a single chip is easily foreseen as a common approach for use by electronic engineers, leading to an important expansion of the use of tailored solutions, including heterogeneous distributed controllers. To cope with the industrial need for flexibility, the automated design technique for these FPGA-based controllers is part of a broad project in the field of hardware/software co-design. The main purpose is to develop different implementations of controllers using a simple, standard and well-known design methodology like SFC (or Grafcet) or Petri nets. It is envisaged that the development of these controllers can be automated, as a first stage, based on FPGAs, single-chip microcontrollers and PLCs that co-operate to achieve a final goal. The present paper deals exclusively with the design of FPGA-based controllers.
2. Background 2.1. Petri nets, Grafcet and SFC By means of using Petri-net techniques, intuitiveness is related with formality (David and Alla, 1992). Up to the point of local state assignment (place encoding) the Petri-net diagram is implementation-independent (Adamski, 1991). A control algorithm is specified, analysed and transformed by using the diagram alone. Using the Petri-net theory one can detect and correct design errors before investing in synthesis. A Petri-net diagram is not only a high-level abstraction of intended controller behaviour (Adamski and Wegrzyn, 1994; Bilinski et al., 1994; Kozlowski et al., 1995; Fernandes et al., 1997), as interpreted Petri nets maintain a direct correspondence to local states which are mapped into flip-flops. In the diagram, places are represented by a circle containing symbolic names. Transitions are represented by bars that are labelled with Boolean input conditions and associated Mealy-type outputs. A transition from source places (preconditions) to destination places (postconditions) can fire (occur) only after the source places are marked and the Boolean condition is satisfied. Conditional equations (rules) are used for design entry and documentation for specification, local state assignment and design validation. A Petri net with a Grafcet-type input interpretation (David and Alla, 1992) is equivalent to Grafcet, whose aim is the specification of logic controllers. It can form a basis for a sequential function chart (SFC), which is a part of the IEC-1131-3 standard (Lewis, 1995; Halang, 1989). 2.2. FPGA as a logic controller An FPGA consists of an array of uncommitted elements that can be interconnected in a general way. Like a PAL, the interconnections between the elements are user-programmable. FPGAs were introduced in 1985 by the Xilinx company, and since then, many different FPGAs have been developed by a number of companies: Actel, Altera, Plessey, AMD, QuickLogic, Algotronix, Concurrent Logic, Crosspoint Solutions, and others. Fig. 1 depicts a conceptual diagram of a typical FPGA. As shown in the figure, it consists of a two-dimensional array of logic blocks that can be connected by general interconnection resources. The interconnection comprises segments of wire. The segments may be of various lengths. In the interconnection there are programmable switches that enable one to connect the logic blocks to the wire segments, or one wire segment to another. Logic circuits are implemented in the FPGA by partitioning the logic into individual logic blocks, and then interconnecting the blocks as required via the switches (Jenkins, 1994; Xilinx, 1996; York, 1993).
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Fig. 1. A conceptual FPGA.
To facilitate the implementation of a wide variety of circuits, it is important that an FPGA be as versatile as possible. This means that the design of the logic blocks, coupled with that of the interconnection resources, should facilitate the implementation of a large number of digital logic circuits. There are many ways of designing an FPGA, involving trade-offs in the complexity and flexibility of both logic blocks and interconnection resources. In terms of their structure, the FPGAs can be divided into four main classes: symmetrical array (Manhattan), row-based (terraced), hierarchical PLD (Red Square) and sea-of-gates (York, 1993). Another problem is the realisation of the programming elements. The programming technologies that are currently in use are: static RAM, antifuses, EPROM transistors, and EEPROM transistors. Logic-block architectures can be designed in many different ways: as simple gates (e.g., 2-input NAND gates), or as more complex structures, such as multiplexors or look-up tables. In some FPGAs, a logic block
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corresponds to an entire PAL-like structure. Fig. 2 shows a Xilinx FPGA with more details. The variety and complexity of currently produced FPGAs make them suitable for use in a wide set of applications. Two significant advantages of FPGAs are as follows: lower prototype costs and shorter production time. In addition, some FPGA vendors provide an opportunity for simple, no-risk migration from FPGAs to MPGAs (mask-programmable gate arrays), e.g., the Xilinx Hard-wire (Xilinx, 1996). Another solution to decrease the costs is the large-volume fabrication of a VLSI chip based on the tested FPGA prototype. As user-programmable application-specific integrated circuits, they provide a valuable compromise which combines the benefits of standard microcontrollers with many of the benefits of other semi-custom logic. The design process is greatly simplified, due to the powerful FPGA compilers, as well as some new modern and effective CAD tools, which have recently become available. The effective simulation allows a logic controller to be simulated and debugged before the device is programmed. If design changes are needed, it is a simple matter to re-edit the original specification and then reprogram the former device. It could be expected that after some time industrially oriented complex PLD and FPGA would be introduced. Advanced PLDs or FPGAs, together with modern CAD tools, may easily replace some of the old fashioned programmable controllers (Adamski, 1991; Mandado et al., 1996; Adamski and Monteiro, 1996). The logic cell array (LCA) provides a fixed array of logical function cells (Fig. 2). The internal function cells are identical, and may be configured (Jenkins, 1994; Xilinx, 1996), allowing different flip-flops types such as D and JK. The LCA design software is called XACT, and it supports design entry, design implementation, and design simulation. Design entry occurs by schematic capture (for example OrCAD) or logical equations (for example PALASM or ABEL). The XACT design netlist,
Fig. 2. Architecture of a FPGA.
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like the XNF file, is passed to the placement and routing software or the simulation software.
3. Application-specific logic controllers Safe Petri nets (David and Alla, 1992) can be viewed as a natural extension to finite state machine (FSM) specification. Each place of the control-interpreted Petri net (CIPN) is viewed as a local control state. The global state of the controller is given by the PN marking (the distribution of tokens by the places). The Petri net may be directly mapped into the Boolean equations (decision rules) without explicit enumeration of all the possible global states and all the possible global state changes (Adamski, 1991; Bilinski et al., 1994). The specification is given in terms of the local state changes (local transitions) and the use of different kinds of local state assignment (encoding of places). A symbolic Petri net description is based on the concept of extended production rules, described by means of conditional logic. The first implementation was performed in the Logician CAD system (Adamski, 1991). The syntax of the language has been revised over the years. Some major syntax modifications have been made in the PARIS system, and a new description format called the Petri net specification format (PNSF) for VLSI design was introduced (Kozlowski et al., 1995). The CONPAR specification format (Fernandes et al., 1997) is consistent with previously introduced rule-based specification languages, and was also created mainly as a bridge between the textual logic description of Petri nets and their VHDL models. Transition rules are usually treated as production rules (‘if—then’ non-procedural statements). The rule-based description, supported by means of logic deduction techniques (Gentzen natural logic calculus), was recently presented in a programmable logic controller design context (Adamski and Monteiro, 1996). A Petri net can be first expressed graphically, and then manually or automatically translated into an equivalent textual format. Some graphical Petri-net tools are under development. The specifications with Grafcet (David and Alla, 1992) or SFC (Lewis, 1995; Halang, 1989; Jiang and Holding, 1992) are treated as special forms of controlinterpreted safe Petri nets.
Fig. 3. Physical model of MIX — 2 — BRIX control system.
The system controls the mixing of two bricks of solid material, brought one at a time on a belt, with weighed quantities of two liquid components A and B (Fig. 3). For the sake of simplicity, only the particular part of the logic controller that is described by means of a sequential function chart (SFC) (Halang, 1989) is considered (Fig. 4). An SFC is a graphical sequencing language, which is based on Grafcet and Petri nets (David and Alla, 1992). It is a flowchart of steps, representing one or more actions. Transitions represent events, and they define the conditions to pass to the next step. The equivalent interpreted Petri-net model (Fig. 5) contains level-actions (type N) depicted around the places, and stored actions (type RS), invoked by events and set by S-type signals and reset by R-type signals. The external inputs, and eventually also the internal conditions, that are associated with transitions (events) are represented as logic expressions. Two components of the control algorithm are implemented on the data path of the controller, but are not considered in the paper: f relational operations used by conditional statements (as a multi-level comparator); f delay operations (as a digital timer, a special-purpose counter with a comparator). 4.2. Design methodology
4. Methodology for FPLD & FPGA modelling and automatic synthesis 4.1. Example As an example, a simplified version of a logic controller, taken from the IEC standard, has been selected (Adamski and Monteiro, 1996).
The interpreted Petri-net model (or equivalent SFC) is translated into a rule-based specification, which is composed of the discrete local state symbols, input signal symbols and output signal symbols of the controller (Fig. 6). Discrete state transition rules are written in the extended PNSF, and describe local state changes,
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Fig. 4. SFC model of the logic controller.
influenced by the external environment. A Petri-net transition, with its input and output places, is mapped into the particular rule, in which the precondition and postcondition are respectively formed from its input and output place symbols (Adamski, 1991; Adamski and Monteiro, 1996). When the preconditions of a rule are satisfied (hold), the postconditions are made true (they will hold). Although it is possible to optimise poorly designed initial descriptions, the compilation process takes much longer and is less predictable, and the result is usually worse than if the code is well structured. To model an explicit concurrent state machine, the current state register, next state, and control outputs are explicitly declared by the designer. 4.3. LCA implementation This section describes an experimental sub-system for the design of logic controllers with Xilinx FPGAs, such as devices from the 3000 and 4000 LCA families. The extended design environment for a Xilinx FPGA contains a new, additional design entry for the behavioural specification of logic controllers, which are described by
Fig. 5. Equivalent Petri-net model of the logic controller.
means of Petri nets or related SFCs (Petri-net Specification entry module in Fig. 7). Textual PNSF is translated directly into the netlist in unified Xilinx format. The next steps of the design implementation are realised by the XACT. Functional and timing simulations are performed, for example, in OrCAD or ViewLogic tools. Fig. 8 presents the general model of an LCA-based logic controller. It contains four conceptual blocks, which are represented by separate files. The files
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Fig. 6. Logic controller description in PNSF.
input.xnf, output.xnf and ff.xnf describe, respectively, the input buffers, output buffers and flip-flops. They are identical for all designs, except in the number of elements. The structure of the Petri net is directly reflected in the logic block. The input data is loaded into the LCA I/O cells, which work as simple transparent buffers (Fig. 8). The outputs of each input buffer connect to the configurable logic blocks (CLBs) through interconnection resources. The places of the Petri net are treated as distributed local states, and are assigned to particular D flip-flops in the Register Block. They are labelled by the particular place names, for example START, WEIGH—A, etc. The registered outputs (MR and MT) are assigned to the separate JK flip-flops. Signals S—MR and S—MT are connected to J excitation inputs, and signals R—MR and R—MT to K inputs, respectively. The logic decision rules, which exactly reflect the description in PNSF, are transformed from the transition-oriented form T (Fig. 6) into the place-oriented description P (Fig. 9). The simplest technique for Petrinet place encoding is to use a one-to-one mapping of places onto flip-flops in the style of one hot state assignment. This approach to synthesising a controller is based on creating a one-to-one direct mapping between the Petri net (Fig. 5) and the hardware realisation (Fig. 10).
Fig. 7. Extended design flow.
Fig. 8. Conceptual block-diagram of logic controller with LCA.
As an illustration, Fig. 11 depicts only selected parts of the XNF files. It demonstrates: the input buffer specification of the TM input (Fig. 11a), the output buffer of the MR output (Fig. 11b), the D flip-flop for the MIX place and the JK flip-flop for the registered output MR (Fig. 11c). In addition, the excitation function for the D flip-flop for the MIX place is shown (Fig. 11d).
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Fig. 9. Implementation description.
Fig. 10. Implementation of rules: (a) P9, (b) RO2.
It relates the description shown in bold face in Fig. 9 as rule P9. The first version includes the XNF description only, with the textual equivalents of two-input gates, and eventually with some inverted inputs (Figs. 10, 11d). The optimisation is performed before mapping to CLBs by the XACT system. It is easy to introduce into the design, an operational part from the user-defined library, like for example input comparators and other functional blocks such as timers. 4.4. Experimental results The design uses only fourteen logic modules (Fig. 12) for the example being considered, and easily fits into less than a quarter of the LCA 3000 integrated circuit. The
XACT software merged the registered outputs with the registered state variables. For example, the registered state signal RAISE replaces the output signal MP0. Some places need, for a direct mapping, more than one CLB; an example is the place MIX. The implementation of the logic controller has been examined to determine the amount of resources it would require for different design strategies. The design has been synthesised, placed and routed (automatically and manually). The realisation of the design has been compared with expectations. It is too early to present the final conclusions, since the number of benchmarks is still limited. An estimation of the logic cells counts for this example, implemented with PeNCAD and Xilinx XACT, is 14 CLBs. After re-designing (manual placement) the total logic cell count for this implementation is 11 CLBs.
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Fig. 12. Summary of implementation.
ed approach, and to test the experimental design system. Benchmarks were taken from published papers, among others from (Toulotte, 1978; Ferrarini, 1992; Adamski, 1991; Wegrzyn et al., 1996; Adamski and Monteiro, 1996; Fernandes et al., 1997). The Petri nets or SFCs were one hot encoded (one flip-flop per place) and then synthesised using PeNCAD and Xilinx XACT with a FPGA XC3020A. In Table 1, the symbols are as follows: f f f f f
dIn — number of inputs; dOut — number of outputs; dP — number of places in Petri net (steps in SFC); dT — number of transitions; CLB — number of logic blocks and utilisation in the part; f IOB — number of input/output blocks and utilisation in the part; f CLB Gen. — number of combinatorial function generators (in the CLB) and utilisation in the part; f CLB FF — number of CLB flip-flops and utilisation in the part.
Fig. 11. Selected parts of the XNF files: (a) input.xnf; (b) output.xnf; (c) ff.xnf; (d) logic.xnf.
5. Conclusion A systematic approach, which allows a user to develop a simple logic controller using Petri nets or SFC charts, and implement it using FPGAs, has been introduced. It has been particularly demonstrated how to use Xilinx/XACT and Field Programmable Logic (FPL) oriented algorithms to manage the design of flexible application-specific logic controllers. The research is still at an initial stage. A number of well-known designs have been used to verify the present-
The proposed technique can be successfully used for both simulation and automatic synthesis. Initially, the behavioural specifications of a logic controller can be represented graphically in different fashions, for example as Petri nets, Grafcets, SFCs, linked state diagrams, linked ASM-charts, and symbolic transition tables (transition lists). All these kinds of initial description can be easily represented in an unified symbolic format, and then formally verified and partially optimised. The common internal specification is translated automatically into FPGA, for example Xilinx LCA. The graphical entries for Petri nets and SFC are under development. An important advantage is also related to the integration of this methodology into a more complex and large framework that includes the specification of discrete controllers using different specification languages, simulation and validation, and producing a final system in either software, or hardware, or as a combined solution. As stated in the introduction, the present paper presents part of a larger project aimed at producing heterogeneous controllers to be used in control applications in industry. The purpose is to establish a common design
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Table 1 Experimental results Controller
Mixer Drill station Reactor Reactor (small) MIX — 2 — BRIX Link adapter
dIn
11 16 10 7 8 11
dOut
15 11 9 7 8 4
dP
15 16 16 9 11 29
dT
12 18 13 8 10 35
CLB
IOB
CLB Gen.
CLB FF
d
%
d
%
d
%
d
%
24 16 16 9 14 38
37 25 25 14 22 59
26 28 20 15 17 16
45 48 34 26 29 28
34 20 18 11 20 46
26 15 14 9 15 36
17 16 16 9 13 33
13 12 12 7 10 26
methodology that automatically produces different controllers that co-operate for a common goal. The first stage has considered PLCs, single-chip controllers and software-based systems. The use of FPGAs as single-chip controllers is promising and cost-effective for several applications. The main advantages of using this technology is related to the time-to-market and the ability to import a specification and quickly produce a provable solution using a low-cost reconfigurable device. The research was supported by the Polish State Committee for Scientific Research, and the Portuguese Ministry of Science and Technology.
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