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4709366 Computer assisted fault isolation in circuit board testing
Microelectron. Reliab., Vol. 28, No. 4, pp. 665 670, 1988. Printed in Great Britain.
0026 2714/8853.00+ .00 Pergamon Press plc
NEW PATENTS This Section contains abstracts and, where appropriate, illustrations of recently issued United States patents and published patent applications filed from over 30 countries under the Patent Cooperation Treaty. This information was obtained from recent additions to the Pergamon PATSEARCH" online database in accordance with interest profiles developed by the Editors. Further information about Pergamon PATSEARCH ~ can be obtained from Pergamon Orbit InfoLine Inc., 8000 Westpark Drive, McLean, Virginia 22102 U.S.A. Copies of complete patents announced in this Section are available from Pergamon Orbit InfoLine Inc. for $8 per copy. Payment with order is required. Orders outside North America add $2 for air postage. Order by patent number for Pergamon Orbit InfoLine only.
4707654
c o m p a r e d to a predetermined response corresponding to an operational U U T to generate a failure accusation or recommend the next node to be probed. The computer is programmed to expedite the search for the source of the failure by displaying to the technician clues which define the circuit nodes most apt to be defective as a result of preliminary functional testing of the U U T . The computer is further p r o g r a m m e d to have a form of intuition whereby the particular nodes recommended for probing are determined in part by prior testing of the same type of U U T .
INTEGRATED CIRCUIT HAVING INPUT AND OUTPUT TERMINALS FOR TESTING Toshir Suzuki, Fumiaki Fujii, Izuru Yamada, T a m a , J a p a n assigned to Hitachi Ltd An integrated circuit is constructed in order that tests can be conducted on a plurality of circuits to determine which of the circuits is defective. In particular, the circuit is constructed to allow such testing with the use of fewer input and output pins for testing. To accomplish this, a first buffer gate circuit, a resistor, and a second buffer gate are connected in series in the order mentioned between the output terminal o f a first circuit and the input terminal of a second circuit. An input and output terminal pin for testing is located at a junction point of the resistor and second buffer gate.
4710440 TEST MASK FOR DETERMINING ALIGNMENT OF AN AUTOMATIC IC MASK TESTING APPARATUS Priore Paul J Del assigned to RCA Corporation
4709366
A test mask is provided for determining that an automatic IC photomask testing machine is scanning within a desired die area. The test mask includes a plurality of care areas which correspond to the die areas of a mask to be tested. The peripheral region surrounding each care area includes portions which may be opaque and portions which may be transparent. These opaque and transparent portions are arranged so that when two care areas are being scanned and the scan improperly leaves the care area and enters the peripheral region, the portion of the peripheral region o f the one care area being scanned is opaque while the portion of the peripheral region of the other care area is transparent. This will be interpreted by the mask testing machine as an error and will therefor be indicative that the machine will scan outside of the desired die areas when testing an IC photomask.
COMPUTER ASSISTED FAULT ISOLATION IN CIRCUIT BOARD TESTING Marshall Scott, John D Polstra assigned to John Fluke Mfg Co Inc Circuit faults in an electronic system are isolated by a p r o g r a m m e d computer that guides a technician node-by-node on a unit under test (UUT), such as a circuit board, to the source of a failure. Stimulus pattern signals are applied to the circuit, and responses at the circuit nodes are made by a measurement probe under the hand of the technician. As each node is probed, a stimulus pattern signal tailored for testing that node is applied to the U U T . The measured response is 665
0026 2714/8853.00+ .00 Pergamon Press plc
NEW PATENTS This Section contains abstracts and, where appropriate, illustrations of recently issued United States patents and published patent applications filed from over 30 countries under the Patent Cooperation Treaty. This information was obtained from recent additions to the Pergamon PATSEARCH" online database in accordance with interest profiles developed by the Editors. Further information about Pergamon PATSEARCH ~ can be obtained from Pergamon Orbit InfoLine Inc., 8000 Westpark Drive, McLean, Virginia 22102 U.S.A. Copies of complete patents announced in this Section are available from Pergamon Orbit InfoLine Inc. for $8 per copy. Payment with order is required. Orders outside North America add $2 for air postage. Order by patent number for Pergamon Orbit InfoLine only.
4707654
c o m p a r e d to a predetermined response corresponding to an operational U U T to generate a failure accusation or recommend the next node to be probed. The computer is programmed to expedite the search for the source of the failure by displaying to the technician clues which define the circuit nodes most apt to be defective as a result of preliminary functional testing of the U U T . The computer is further p r o g r a m m e d to have a form of intuition whereby the particular nodes recommended for probing are determined in part by prior testing of the same type of U U T .
INTEGRATED CIRCUIT HAVING INPUT AND OUTPUT TERMINALS FOR TESTING Toshir Suzuki, Fumiaki Fujii, Izuru Yamada, T a m a , J a p a n assigned to Hitachi Ltd An integrated circuit is constructed in order that tests can be conducted on a plurality of circuits to determine which of the circuits is defective. In particular, the circuit is constructed to allow such testing with the use of fewer input and output pins for testing. To accomplish this, a first buffer gate circuit, a resistor, and a second buffer gate are connected in series in the order mentioned between the output terminal o f a first circuit and the input terminal of a second circuit. An input and output terminal pin for testing is located at a junction point of the resistor and second buffer gate.
4710440 TEST MASK FOR DETERMINING ALIGNMENT OF AN AUTOMATIC IC MASK TESTING APPARATUS Priore Paul J Del assigned to RCA Corporation
4709366
A test mask is provided for determining that an automatic IC photomask testing machine is scanning within a desired die area. The test mask includes a plurality of care areas which correspond to the die areas of a mask to be tested. The peripheral region surrounding each care area includes portions which may be opaque and portions which may be transparent. These opaque and transparent portions are arranged so that when two care areas are being scanned and the scan improperly leaves the care area and enters the peripheral region, the portion of the peripheral region o f the one care area being scanned is opaque while the portion of the peripheral region of the other care area is transparent. This will be interpreted by the mask testing machine as an error and will therefor be indicative that the machine will scan outside of the desired die areas when testing an IC photomask.
COMPUTER ASSISTED FAULT ISOLATION IN CIRCUIT BOARD TESTING Marshall Scott, John D Polstra assigned to John Fluke Mfg Co Inc Circuit faults in an electronic system are isolated by a p r o g r a m m e d computer that guides a technician node-by-node on a unit under test (UUT), such as a circuit board, to the source of a failure. Stimulus pattern signals are applied to the circuit, and responses at the circuit nodes are made by a measurement probe under the hand of the technician. As each node is probed, a stimulus pattern signal tailored for testing that node is applied to the U U T . The measured response is 665