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4894605 Method and on-chip apparatus for continuity testing
New Patents
elongate body. A hooked gripping tip for probing Integrated circuit devices and the like is formed on one end of a conductive shaft inserted into the elongate body. Axial movement of the conductive shaft relative to the elongate body alternately extends and retracts the hooked gripping tip out of and into the elongate body. The electrically conductive elongate body provides a low contact resistance path between the gripping tip and the output connector.
4891684 SEMICONDUCTOR
DEVICE
Yasushiro Nishioka, Hiroshi Shinriki, Noriyuki Sakuma, Kiichiro Mukai assigned to Hitachi Ltd A reaction-preventing film is provided between a capacitor insulating film made of a material having a high dielectric constant, such as Ta205, and an upper electrode in order to prevent a reaction of the upper electrode with the capacitor insulating film. This effectively prevents the reaction between the upper electrode and the capacitor caused by a heat treatment conducted after formation of the capacitor, and hence prevents an increase in leakage current caused by the reaction. Thus, the reliability of a semiconductor device is remarkably increased.
4894114 PROCESS FOR PRODUCING IN SEMICONDUCTOR
VIAS
Harvey C Nathanson, Michael Driver, Michael W Cresswell, Ronald G Freitag, Donald K Alexander, Daniel F Yaw assigned to Westinghouse Electric Corp An improved phased-array active antenna transmit-receive means utilizing a multiplicity of individual transmit-receive cells positioned in an array format upon a common wafer of semiconductor material. Each transmit-receive cell, comprises a multiplicity of redundant, integrated circuit, electronic devices implanted upon the common semiconductor substrate. The transmit-receive cells utilize novel mitered mechanical switches to permanently interconnect individual electronic devices into either transmit or receive circuits during the fabrication and test of the transmit-receive cells. Radio frequency and direct current input and output vias formed from a novel metal evaporation
iii
technique connect the devices upon the surface of the common semiconductor wafer to underlying, insulated direct current distribution circuits and a radio frequency manifold. This array of improved phased-array active antenna transmit-receive means comprised of transmitreceive cells sharing common central processing means, logic control and heat dissipation means results in a significant reduction in the size and weight of the standard phased-array active antenna system. This significant reduction in antenna system size and weight is very important in broad band electronic countermeasure systems or narrow band phased array active antenna radar systems as used in advanced tactical fighters, or space applications.
4894605 METHOD AND ON-CHIP APPARATUS FOR CONTINUITY TESTING Diethelm Ringleb, Reinhard Schumann, Elsworth Stearns, Tom Stylianos, John Sweeney assigned to Digital Equipment Corporation A method of performing continuity testing of individual lead sets bonded to an integrated semiconductor component with a continuity test circuit fabricated on the component. The continuity test circuit includes a plurality of current gates, each of which is associated with a different semiconductor component contact pad a lead set is bonded to. Each current gate includes a first terminal connected to the associated contact pad and a second terminal connected to a common conductor all the current gate second terminals are connected to. The common conductor terminates at a semiconductor component contact test pad a lead set is bonded to. Whenever a test signal is applied to either the first or second terminal of a current gate, a measurable response signal is generated by the current gate over the other terminal. Continuity testing of the lead sets bonded to the chip is performed by applying a test signal to either a wiring board conductor connected to the lead set being tested or a wiring board conductor connected to the lead set connected to the semicondcutor component test contact pad. A test probe is then applied to the board conductor the test signal is not applied to. If the response signal is sensed, the leads are properly bonded; if no response signal is detected either the lead set being tested on the lead set connected to the semiconductor component is improperly bonded. The current gate blocks signals on the first terminal from appearing on
iv
New Patents
the second terminal or the common conductor. Thus, when the semiconductor component is in use, the continuity test circuit is isolated from the other individual circuit components forming the integrated semiconductor component.
4894708 LSI PACKAGE HAVING A MULTILAYER CERAMIC SUBSTRATE Toshihik Watari, Tokyo, Japan assigned to NEC Corporation A large scale integrated package comprises a substrate having a power supply layer and a signal wiring layer. A plurality of pads for connecting IC terminals are formed on the top surface of the substrate. Additionally, a plurality of spare pads are also provided on the top surface of the substrate. The lower surface of the substrate has a plurality of input/output terminals which can be inserted into connectors. Additionally, the lower surface of the substrate has a plurality of spare terminals. Each of the pads and spare pads are electrically connected through the substrate to a corresponding terminal and spare terminal. A broken connection between a first pad and a first input/output terminal can be repaired by connecting the first pad to a spare pad and the first input/output terminal to the spare input/output terminal corresponding to the spare pad.
metallization process simultaneously with the other MOS or other type of transistors to be tested. The two test transistors share a common diffused region, a self-aligned c o m m o n controlled electrode contacting a diffused region underneath it, and a common control electrode. During test operation, both est transistors are kept O N by means of an applied abovethreshold control voltage, while a current source forces current through one of the transistors. The resulting voltage, developed across the common controlled electrode and the controlled electrode of the other transistor is a measure of the specific contact resistivity thereat.
4897817 SEMICONDUCTOR MEMORY DEVICE WITH A BUILT-IN TEST CIRCUIT Naoki Katanosaka, Tokyo, Japan assigned to N E C Corporation A semiconductor memory device provided with an on-chip test circuit is disclosed. The on-chip test circuit includes a test write circuit for writing the same write data to at least two memory cells, simultaneously in a test mode, a selection circuit for simultaneously reading stored data from the above at least two memory cells and a comparison circuit for comparing data read from the at least two memory cells whose comparison output shows whether at least one of the at least two memory cells is bad, or all of the at least two memory cells are good.
4896108 TEST CIRCUIT FOR M E A S U R I N G SPECIFIC CONTACT RESISTIVITY OF SELF-ALIGNED CONTACTS IN INTEGRATED CIRCUITS
4899055 THIN FILM THICKNESS MEASURING METHOD Arnol Adams assigned to Tencor Instruments
William T Lynch, K w o k K Ng assigned to American Telephone and Telegraph C o m p a n y A T & T Bell Laboratories A test circuit is described for measuring the specific contact resistivity rc of self-aligned electrodes contacting underlying diffused regions at a major surface of an underlying semiconductor wafer, as well as the sheet (lateral) resistance rs of the underlying diffused regions in some embodiments. The test circuit illustratively includes a pair of test MOS or other type of transistors advantageously made by a self-aligned
A method of measuring thin film thickness, especially on semiconductor substrates, in which the substrate is illuminated with ultraviolet light of a fixed wavelength corresponding to a persistent spectral line and the amount of light reflected from the substrate is detected and measured. The ultraviolet light preferably has a wavelength in the range from 240 nm to 300 nm, and the 253.6 nm spectral line of mercury is considered best. Comparing the measured amount of light from the substrate to a known amount of light detected from a standard calibration substrate
elongate body. A hooked gripping tip for probing Integrated circuit devices and the like is formed on one end of a conductive shaft inserted into the elongate body. Axial movement of the conductive shaft relative to the elongate body alternately extends and retracts the hooked gripping tip out of and into the elongate body. The electrically conductive elongate body provides a low contact resistance path between the gripping tip and the output connector.
4891684 SEMICONDUCTOR
DEVICE
Yasushiro Nishioka, Hiroshi Shinriki, Noriyuki Sakuma, Kiichiro Mukai assigned to Hitachi Ltd A reaction-preventing film is provided between a capacitor insulating film made of a material having a high dielectric constant, such as Ta205, and an upper electrode in order to prevent a reaction of the upper electrode with the capacitor insulating film. This effectively prevents the reaction between the upper electrode and the capacitor caused by a heat treatment conducted after formation of the capacitor, and hence prevents an increase in leakage current caused by the reaction. Thus, the reliability of a semiconductor device is remarkably increased.
4894114 PROCESS FOR PRODUCING IN SEMICONDUCTOR
VIAS
Harvey C Nathanson, Michael Driver, Michael W Cresswell, Ronald G Freitag, Donald K Alexander, Daniel F Yaw assigned to Westinghouse Electric Corp An improved phased-array active antenna transmit-receive means utilizing a multiplicity of individual transmit-receive cells positioned in an array format upon a common wafer of semiconductor material. Each transmit-receive cell, comprises a multiplicity of redundant, integrated circuit, electronic devices implanted upon the common semiconductor substrate. The transmit-receive cells utilize novel mitered mechanical switches to permanently interconnect individual electronic devices into either transmit or receive circuits during the fabrication and test of the transmit-receive cells. Radio frequency and direct current input and output vias formed from a novel metal evaporation
iii
technique connect the devices upon the surface of the common semiconductor wafer to underlying, insulated direct current distribution circuits and a radio frequency manifold. This array of improved phased-array active antenna transmit-receive means comprised of transmitreceive cells sharing common central processing means, logic control and heat dissipation means results in a significant reduction in the size and weight of the standard phased-array active antenna system. This significant reduction in antenna system size and weight is very important in broad band electronic countermeasure systems or narrow band phased array active antenna radar systems as used in advanced tactical fighters, or space applications.
4894605 METHOD AND ON-CHIP APPARATUS FOR CONTINUITY TESTING Diethelm Ringleb, Reinhard Schumann, Elsworth Stearns, Tom Stylianos, John Sweeney assigned to Digital Equipment Corporation A method of performing continuity testing of individual lead sets bonded to an integrated semiconductor component with a continuity test circuit fabricated on the component. The continuity test circuit includes a plurality of current gates, each of which is associated with a different semiconductor component contact pad a lead set is bonded to. Each current gate includes a first terminal connected to the associated contact pad and a second terminal connected to a common conductor all the current gate second terminals are connected to. The common conductor terminates at a semiconductor component contact test pad a lead set is bonded to. Whenever a test signal is applied to either the first or second terminal of a current gate, a measurable response signal is generated by the current gate over the other terminal. Continuity testing of the lead sets bonded to the chip is performed by applying a test signal to either a wiring board conductor connected to the lead set being tested or a wiring board conductor connected to the lead set connected to the semicondcutor component test contact pad. A test probe is then applied to the board conductor the test signal is not applied to. If the response signal is sensed, the leads are properly bonded; if no response signal is detected either the lead set being tested on the lead set connected to the semiconductor component is improperly bonded. The current gate blocks signals on the first terminal from appearing on
iv
New Patents
the second terminal or the common conductor. Thus, when the semiconductor component is in use, the continuity test circuit is isolated from the other individual circuit components forming the integrated semiconductor component.
4894708 LSI PACKAGE HAVING A MULTILAYER CERAMIC SUBSTRATE Toshihik Watari, Tokyo, Japan assigned to NEC Corporation A large scale integrated package comprises a substrate having a power supply layer and a signal wiring layer. A plurality of pads for connecting IC terminals are formed on the top surface of the substrate. Additionally, a plurality of spare pads are also provided on the top surface of the substrate. The lower surface of the substrate has a plurality of input/output terminals which can be inserted into connectors. Additionally, the lower surface of the substrate has a plurality of spare terminals. Each of the pads and spare pads are electrically connected through the substrate to a corresponding terminal and spare terminal. A broken connection between a first pad and a first input/output terminal can be repaired by connecting the first pad to a spare pad and the first input/output terminal to the spare input/output terminal corresponding to the spare pad.
metallization process simultaneously with the other MOS or other type of transistors to be tested. The two test transistors share a common diffused region, a self-aligned c o m m o n controlled electrode contacting a diffused region underneath it, and a common control electrode. During test operation, both est transistors are kept O N by means of an applied abovethreshold control voltage, while a current source forces current through one of the transistors. The resulting voltage, developed across the common controlled electrode and the controlled electrode of the other transistor is a measure of the specific contact resistivity thereat.
4897817 SEMICONDUCTOR MEMORY DEVICE WITH A BUILT-IN TEST CIRCUIT Naoki Katanosaka, Tokyo, Japan assigned to N E C Corporation A semiconductor memory device provided with an on-chip test circuit is disclosed. The on-chip test circuit includes a test write circuit for writing the same write data to at least two memory cells, simultaneously in a test mode, a selection circuit for simultaneously reading stored data from the above at least two memory cells and a comparison circuit for comparing data read from the at least two memory cells whose comparison output shows whether at least one of the at least two memory cells is bad, or all of the at least two memory cells are good.
4896108 TEST CIRCUIT FOR M E A S U R I N G SPECIFIC CONTACT RESISTIVITY OF SELF-ALIGNED CONTACTS IN INTEGRATED CIRCUITS
4899055 THIN FILM THICKNESS MEASURING METHOD Arnol Adams assigned to Tencor Instruments
William T Lynch, K w o k K Ng assigned to American Telephone and Telegraph C o m p a n y A T & T Bell Laboratories A test circuit is described for measuring the specific contact resistivity rc of self-aligned electrodes contacting underlying diffused regions at a major surface of an underlying semiconductor wafer, as well as the sheet (lateral) resistance rs of the underlying diffused regions in some embodiments. The test circuit illustratively includes a pair of test MOS or other type of transistors advantageously made by a self-aligned
A method of measuring thin film thickness, especially on semiconductor substrates, in which the substrate is illuminated with ultraviolet light of a fixed wavelength corresponding to a persistent spectral line and the amount of light reflected from the substrate is detected and measured. The ultraviolet light preferably has a wavelength in the range from 240 nm to 300 nm, and the 253.6 nm spectral line of mercury is considered best. Comparing the measured amount of light from the substrate to a known amount of light detected from a standard calibration substrate