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A 1024-element bulk-micromachined thermopile infrared imaging array
Sensors and Actuators 73 Ž1999. 222–231
A 1024-element bulk-micromachined thermopile infrared imaging array Andrew D. Oliver ) , Kensall D. Wise Center for Integrated Sensors and Circuits, Department of Electrical Engineering and Computer Science, The UniÕersity of Michigan, Ann Arbor, MI 48109-2122, USA Received 21 July 1998; revised 26 October 1998; accepted 29 October 1998
Abstract This paper reports on a bulk-micromachined silicon uncooled thermal imager intended for use in automated semiconductor process control. The device has a responsivity of 15 VrW, a thermal time constant of 1 ms, and a D) of 1.6 = 10 7 cm Hz 1r2rW. It is organized as a 32 = 32-element area array with on-chip address generation, multiplexing, and self-test circuitry. The overall chip size is 16 mm = 16 mm, with a 12 mm = 12 mm imaging area. Each detector consists of 32 n–p polysilicon thermocouples supported on a dielectric window and is micromachined using a novel combined front-undercut and back-etched process. An infrared camera system using the imager is also described. q 1999 Elsevier Science S.A. All rights reserved. Keywords: Thermopile; Micromachining Žbulk.; Infrared imager; Infrared camera; Thermal imaging
1. Introduction During the past few years, a number of very promising uncooled silicon infrared imagers have been reported w1–5x. These devices have used both surface- and bulk micromachining, and among the latter, both front-undercut and back-etched devices have been discussed. Surface-micromachined approaches have achieved high pixel counts Ž80,640 w2x and 16,384 elements w3x. and high responsivities, but generally require vacuum packaging because of the small distance between the detector and the substrate. However, for process control applications involving thermal imaging, vacuum packaging can be difficult to implement due to the wide spectral bandwidth Ž) 10 mm. required in the package window; in night vision applications, where many of the previous imagers have been targeted, sensitivity in the short to medium infrared range Ž- 5 mm. has usually been adequate w6x. In contrast, bulk-micromachined devices do not require vacuum packaging but generally exhibit lower pixel counts and responsivities. The performance of the bulk devices is nonetheless adequate for applications in process control, where
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Corresponding author. Electromechanical Engineering Department, Sandia National Laboratories, PO Box 5800, MS 0329 Albuquerque, NM 87185-0329, USA. Tel.: q1-505-845-7931; fax: q1-505-844-9554; E-mail: [email protected]
high accuracy in determining target temperature over a very wide dynamic range is more important than high spatial resolution. The primary application explored in this work is the monitoring of temperature uniformity over wafers in either rapid thermal processing ŽRTP. or reactive ion etching ŽRIE. systems. Initial work was focused on demonstrating that a silicon uncooled imager could resolve temperature variations to within the "28C level required by advanced process control. A linear bulk-micromachined NMOS imager w1,7x was used in an infrared camera that was interfaced to a personal computer for data acquisition and storage. This system was used on an Applied Materials 8300 hexode RIE at the University of Michigan and on a RTP system at North Carolina State University. Fig. 1 shows the output of a single array element viewing a 100-mm wafer during a polysilicon etch in the AM8300. Much of the data scatter may be due to noise induced in the system by the plasma and by the reactor pumps; however, temperature resolution is still within "0.68C. Fig. 2 shows a map of wafer temperature in RTP as a function of position w8x. To obtain the absolute temperature, special calibration runs were done and independent wafer temperature measurements were made using thermocouples. In this case, the temperature is measured to within "1.58C. These results demonstrated the usefulness of silicon infrared imagers in monitoring wafer temperature uniformity; however, two-dimensional imaging is needed
0924-4247r99r$ - see front matter q 1999 Elsevier Science S.A. All rights reserved. PII: S 0 9 2 4 - 4 2 4 7 Ž 9 8 . 0 0 2 7 6 - 3
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and not the absolute temperature itself. Bulk-micromachined thermopile detectors have the added advantage of not requiring vacuum packaging and can be batch fabricated using semi-custom or standard CMOS fabrication techniques. Thermopiles are inherently large, however, and the thermal isolation achievable is limited by the large number of leads involved. In this application, the pixels should be large enough to average the signal such that local differences in emissivity Že.g., due to oxidermetal patterning on the wafer. are unimportant.
2. Imager design Fig. 1. Output of a single detector on a 32-element array viewing a wafer during reactive ion etching.
for use in next-generation wafer processing at 0.25 mm feature sizes and beyond. This work sought to develop such an imager. In moving to an area array, the various transducer options were again examined. All thermally based infrared detectors convert incident infrared radiation into heat and then into an electrical signal. Both thermopiles and bolometers have been used recently as transducers w1,2x, and read-out options including the use chopping and selftest were also considered. Chopping is useful in moving the signal of interest away from the very low frequencies where 1rf noise is important w9x. However, because it consumes power and is mechanically more complex, it is accordingly less reliable. Self-test can be included in a thermal device relatively easily and is useful both for rapid testing after fabrication and for autocalibrationrautocompensation in the field w10x. It is an important means for reducing the test component of imager cost. In our application, the emphasis was on a low-cost uncooled design operating unchopped and insensitive to changes in ambient temperature. High reliability is especially important in semiconductor applications, where unscheduled downtime can cost thousands of dollars per minute. Thermopiles are attractive since they measure the temperature difference between the hot and cold junctions
Fig. 2. Wafer temperature as a function of position in an RTP system at North Carolina State University as viewed with a thermopile-based linear imager.
Previous effects on thermopile infrared imagers have mostly been limited to single-element detectors or to onedimensional linear arrays w1,4,5,11,12x. One of the two previously reported works concerning a two-dimensional thermopile array used a charge-coupled device ŽCCD. read-out w3x. The other used the gold bumps from a tape-automated bonding technology as an inter-element heat sink w5x. The two-dimensional area imager reported here is composed of an array of 32 rows and 32 columns of infrared detectors with a total of 1024 elements. Each detector has an active area of 300 mm = 300 mm and a total area of 375 mm = 375 mm. The imager is internally x–y organized like a DRAM with a per-pixel switch to gate the output of the individual detectors onto the column lines. The output signal is multiplexed from the 32-column lines onto one output line by an analog 32 to 1 column multiplexer. A three-stage CMOS opamp is available onchip via a bonding option to provide 10 = signal amplification. The digital portion of the device accepts a serial clock input that is used by an on-chip counter to generate a parallel 10-bit address. The address is then decoded by the row and column decoders in the same manner as in a static or dynamic memory. The organization of the imager is shown in Fig. 3.
Fig. 3. Organization of the 1024-element infrared imager.
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The imager also contains an on-chip bandgap temperature sensor formed using the parasitic substrate npn bipolar transistor that arises naturally in the CMOS structure w13x. This circuit provides a measured output sensitivity of 2.3 mVr8C and provides ambient temperature measurement to an accuracy better than 18C, which is sufficient for digital compensation of the imager in the infrared camera system. Each pixel is also provided with a polysilicon heating resistor that allows a known amount of power to be gated into the pixel from a test bus that runs parallel to the column lines. This allows the sensitivity of the detector to be checked at any time, simplifying device testing during manufacture and permitting self-test when in use. One important consideration in designing the infrared imagers was the fabrication of the per-pixel access switches that connect the thermopiles to the column lines. This architecture greatly reduces the amount of routing internal to the array of thermopiles. The design was complicated by initial uncertainty of how to fabricate these per-pixel access switches in silicon while still forming an etch stop on the silicon ribs that support the dielectric windows that form the detectors. The options for fabricating the switches and the etch stop were the following: Ž1. depositing lightly doped epitaxial silicon on top of a p q q diffusion defining the ribs, Ž2. integrating a thin-film transistor ŽTFT. on top of a p q q diffusion, Ž3. using an electrochemical etch-stop and placing the switch transistors in the monocrystalline epitaxial silicon, or Ž4. developing a process that did not depend on a p q q etch stop or an electrochemical etch stop. The choice of an etch stop will be discussed further in Section 3 but it was decided to also examine various methods for creating the switches that could be formed in or on a p q q etch-stop layer. The epitaxial switch option was discarded because of the increased process complexity and the difficulties of depositing monocrystalline silicon on top of p q q silicon. The TFT option, after some experimentation, was also discarded for the same reasons. 3. Micromachining Four micromachining options Žshown in Fig. 4. were considered for constructing the infrared imager. The structure in Fig. 4A is surface-micromachined. The infrared detector here is fabricated on top of a sacrificial layer of silicon dioxide or polysilicon. At the end of the fabrication sequence, the sacrificial layer is removed using a wet etchant, which leaves the infrared detector elevated above the substrate by the thickness of the sacrificial layer Žusually 1–2 mm.. These devices must generally be operated under vacuum to decrease the thermal conduction from the detector to the substrate. This technique has been used by Kanno et al. w3x to produce a 128 = 128 element infrared array . Surface micromachining has also been used to produce micromachined Golay cells w14x and infrared bolometers w2x.
Fig. 4. Five possible micromachined infrared imager structures.
Bulk micromachining Žshown in Fig. 4B–E. can also be used to thermally isolate an infrared detector w4,11,12,15x. In this technique, the bulk silicon itself is used as a sacrificial layer. The wide detector-to-substrate gap that results allows these imagers to be used at atmospheric pressure and simplifies packaging. The structure in Fig. 5B is similar to the ErD NMOS 32-element line imager reported by Baer et al. w1x. In these detectors, the micromachining is performed as a through-wafer back etch. There are two disadvantages to this structure. First, there is no simple way to put circuitry in the p q q etch-stop regions because of their high doping levels, and second, the heat sinks are only 15 mm thick Žthe practical diffusion limit., making the structure vulnerable to thermal cross-talk between pixels. Fig. 4C shows the bulk undercut structure that has been implemented successfully at ETH Zurich w4x, Stanford w15x, and at Michigan by Liu and Mastrangelo w16x and Oliver w17x et al. These detectors are micromachined from the front with an anisotropic etchant that produces a pyramidal etch pit beneath the infrared detector. An advantage of this technique is that it is done with standard CMOS fabrication technology and provides easy implementation of perpixel access switches as well as immunity from cold-junction heating using the bulk ²100: silicon as a heat sink. A disadvantage is that the imager has less thermal isolation at
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Fig. 5. Cross-section of a double-etched infrared imager. The pixel switches are integrated in the single-crystal ²100: silicon support ribs which act as heat sinks.
atmospheric pressure between the thermopile hot junctions and the bulk silicon than the back etched structure. Fig. 4D is an electrochemically etched infrared imager w17,18x. This method uses a lightly doped epitaxial layer for the support ribs and permits the formation of the active pixel switches. The epitaxial silicon is not typically thick enough to prevent some heating of the cold junctions, however. An advantage of this process is that it produces a device that can be illuminated and have a conductive infrared-absorbing layer applied from the back. The design that was eventually chosen is a combination of the front-undercut and the back-etched structures and is shown in Fig. 4E. The resulting structure has excellent thermal isolation at atmospheric pressure, can be illuminated from the back, has lightly doped single-crystal silicon where per-pixel switches are located, and has large heat sinks to reduce thermal cross-talk. A detailed crosssection of the device is shown in Fig. 5. This device has greater thermal isolation than the front-etched structure and greater immunity to cold-junction heating than the back-etched structure because the cold junctions are heat sunk with 60 mm of single-crystal silicon. It has the
simplicity of the front-etched structure and does not require an electrochemical etch-stop or a deep boron diffusion. The structure has two minor disadvantages: Ž1. the conductive heat losses through the gas surrounding the detector are slightly larger than the back-etched structure; and Ž2. the detector loses some area to the slits which provide the etchant access to the silicon on the front side.
4. Cold-junction heating One factor that can influence the output of an thermopile-based infrared detector is cold-junction heating w9,19x. Cold-junction heating occurs when a sudden change in the incident radiation causes the cold-junction temperatures to rise, thus also heating the hot junctions of the thermopiles and reducing the magnitude of the thermal gradients across the thermopiles. The thermopile’s hot junctions cannot change temperature instantaneously due to their thermal time constant and thus the temperature rise of the hot junctions lags the temperature rise of the cold
Fig. 6. Cold-junction heating. This figure shows the simulated output of the center pixel of an imager as it stares at a fixed 5008C target. All of the neighboring pixels stare at areas on the target that change from 5008C to 10008C in 5 s, starting at 0.1 s. The output of the center pixel, which should remain constant, is shown on the left axis while the target temperature viewed by the neighboring pixels is given on the right axis. The increase in the radiant flux absorbed by the neighboring pixels causes the cold junction temperature to rise, decreasing the center pixel output.
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junctions. Fig. 6 shows the simulated response of a single pixel imaging a target wafer in an RTP system which is experiencing cold junction heating due to a rapid increase in the radiant flux incident on the neighboring pixels. The transient error here is about 0.68C for 60 mm-thick support ribs but more than 2.58C for a 15 mm-thick support structure. Note that the effect disappears as soon as the temperature ramp is completed and the cold junction temperature stabilizes.
5. Fabrication In designing an integrated imager containing on-chip readout circuitry, it is important to optimize the fabrication steps for both the circuitry and the transducers. Circuit processes are complex and are typically not designed to allow easy modification. For this reason, and to facilitate technology transfer, the additional steps for forming the transducers are usually added at the beginning or end of the circuit process flow w20x, leaving the circuit process as undisturbed as possible. The imager reported here was fabricated using the standard University of Michigan 3 mm bulk CMOS process with modifications to accommodate dielectric window deposition and thermopile formation. The dielectric window is composed of the LOCOS field oxide, a silicon nitride layer, and the final passivation oxide. The thermopiles are formed using the second polysilicon layer in the Michigan CMOS process. They are doped either with a custom implant or with the same implant used to form the sources and drains of the transistors. In the first case, the Seebeck coefficients can be arbitrarily set; the second results in y200 mVr8C for the n-type polysilicon and q200 mVr8C for the p-type polysilicon. The passivation oxide protects both the circuitry and the thermopiles from the EDP. Contacts are etched through this layer to expose both the thermopiles and the circuitry, and the wafer is metalized with an EDP resistant layer of chromium and gold. The contact etch also opens slits in the pixel regions to permit the 300 mm = 300 mm pixel area to be undercut during the subsequent micromachining. To micromachine and separate the imagers, the wafer is dipped in a dilute HF–nitric–acetic acid mixture for 10 s and subsequently in buffered hydrofluoric acid for 30 s. It is then rinsed and placed vertically in EDP for 10 to 11 hours where the devices etch simultaneously from both sides. The wafer cross-section is shown as a function of time in Fig. 7. As the silicon etches from the front side Žat 40 mmrh., it starts to form a pyramidal pit underneath the thermopile detectors. The pit is bounded by the slow-etching ²111: planes on the sides and by the fast etching ²110: planes on the bottom. On the back, a large pit is also forming, bounded by the ²111: planes on the sides and the ²110: planes on the bottom. This is in accordance with Lee w21x, who states that on ‘concave’ surfaces, the
Fig. 7. Micromachining of the double-etched infrared imager as a function of time.
‘limiting shape’ is formed by the slowest etching planes. The heat sink beams are isolated when the front- and back-side pits meet. The isolated beams are a ‘convex’ structure, and the fast-etching ²311: planes start appearing at the corners and edges of the heat sinks. The etch is terminated when the heat sink beams are approximately 60 mm thick, trading-off thermal isolation of the hot junctions against susceptibility to cold-junction heating. A process window of between 40 mm and 80 mm in beam thickness has been found acceptable, resulting in a 30-min margin for overrunder etching. This process window requires a "1.4% control of etch rate or etch depth. In terms of temperature, the etch temperature must be maintained within 1.48C. The etchant used for this device is the type ‘S’ EDP reported by Reisman et al. w22x in 1979. Initially, type ‘F’ EDP was used for this device instead of type ‘S’ because ‘F’ etches ²100: silicon at 81 mmrh at 1128C instead of ‘S’, which etches at 54 mmrh at the same temperature. It was discovered, however, that type ‘F’ EDP did not have sufficient selectivity between the ²100: and ²111: planes and caused the sidewalls of the silicon heat sinks to be severely attacked. For a successful etch, the ratio between the etch rates of the ²100: to the ²111: planes must be at
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least 25:1. Examples of support ribs etched in type ‘F’ and type ‘S’ EDP are shown in Fig. 8. The EDP etch is done in a double boiler setup with the beaker containing EDP sitting in a glycerin bath. This
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procedure helps keeps the etchant at a uniform temperature and the etch rate consistent throughout the beaker. The uniform etch rate helps ensure that all the imagers are completed at the same time. The double boiler also de-
Fig. 8. The silicon support ribs Žheat sinks. on the double-etched infrared imagers etched in type ‘F’ EDP Žabove. and in type ‘S’ EDP Žbelow.. The imagers are viewed with the back side of the imager at the top of the picture.
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Fig. 9. Top view of a completed double-etched 1024-pixel infrared imager.
creases the amount and the vigor of the circulation of etchant in the beaker. Fig. 9 shows a portion of a completed infrared imager.
rear, although the single-crystal heat sinks tend to reduce the responsivity by slightly shading the thermopiles when the device is illuminated from the rear. To measure the amount of thermal cross-talk, the self-test function was
6. Experimental results The imagers were fabricated using the double-etched pixel design as shown in Fig. 5. All of the major circuit blocks were fully functional. The output of the on-chip bandgap temperature sensor is shown in Fig. 10 as a function of ambient temperature. The output slope is 2.7 mVr8C between 308C and 2008C, with a linear correlation coefficient of 0.9997. The temperature sensor occupies an area of 0.53 mm2 with 50% of the area consumed by the two common-collector bipolar transistors. The preamplifier is an analog three-stage CMOS opamp with n-channel MOSFET inputs w23,24x. The preamplifier has 12 transistors and uses a 5.8pF polyrpoly capacitor to ensure stability. Fig. 11 shows the input and corresponding output of the on-chip preamplifier. The closed-loop gain is 30. The preamplifier occupies an area of 0.16 mm2 and consumes 1.6 mW. This circuit is connected to the output of the column analog multiplexer by a removable link so that an optional external preamplifier can be used instead if desired. The pixels have a measured responsivity of 15 VrW, a thermal time constant of 7 ms, a resistance of 50–70 k V, and a D) of 1.6 = 10 7 cm Hz 1r2rW. The responsivity is aided by a smoked carbon black applied to the rear of the dielectric windows. Without the black, the responsivity is 10 VrW and the time constant is 1.6 ms. The devices can be illuminated from either the front or the
Fig. 10. Measured output of the on-chip bandgap temperature sensor as a function of ambient temperature and a photograph of the integrated sensor. The large structure on the left of the photograph is a common collector bipolar junction transistor.
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output of 220 mV from the primary pixel. is less than 1 mV; calculations predict thermal cross-talk of only 2 ppm, corresponding to about 440 nV.
7. Infrared camera system
Fig. 11. Input Žtop trace 20 mVrdiv. and correspond output Ž500 mVrdiv. from the on-chip closed-loop preamplifier on the imager and a photograph of the preamplifier. The serpentine structure at the bottom of the photograph is one of the feedback resistors.
used. The measured response of the nearest neighbor cell due to a 5-V input to the self-test resistor Žproducing an
The infrared camera system developed for use with the area imager can also be used with single-point w11x and 32-element linear w1x devices. It was designed to resolve small temperature differences over very high temperature scenes, to cope with scenes where the temperature is changing rapidly, and to compensate for electrical drift in the amplifiers. The camera, whose schematic is shown in Fig. 12, is based on a Motorola 68HC11 microcontroller and uses a 12-bit analog-to-digital converter ŽADC., a variable gain amplifier, and a 12-bit digital-to-analog converter ŽDAC.. The DAC is used to lower the dc level of the signal so that higher gain can be used in succeeding amplifier stages. This allows the resolution of small temperature differences on very hot targets. If the amplified signal from the infrared imager is outside the input range of the ADC Ž"5 V., the output of the DAC is automatically adjusted to bring the final value of the amplified signal back within range. The data is then transferred to a personal computer running ‘LabVIEW,’ which records and displays the data. The camera initialization and data acquisition routine is illustrated in Fig. 13. The camera starts by amplifying the signal from one pixel at low gain with the DAC set at 0 V. The ADC converts the analog voltage to a 12-bit number, and the value is recorded in the memory of the microcontroller. The next step is to measure the offset of the amplifier chain at high gain. This value is stored and digitally subtracted from the final value of each imager element. The camera then reads each pixel with the amplifier gain at its maximum value and the output of the DAC at a value calculated to bring the output of the last amplifier stage within the input range of the ADC without remeasuring the pixel at low gain. This amplification
Fig. 12. Schematic of the infrared camera.
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Lockheed Martin Company, for the United States Department of Energy under contract DE-AC04-94AL85000.
References
Fig. 13. Photograph showing the initialization and data acquisition routine used in the infrared camera system. The top trace is the output of the DAC, performing offset subtraction, and the lower trace is the input to the ADC for a constant input.
scheme minimizes the quantization error associated with the LSB, which is often important in semiconductor manufacturing applications where small temperature non-uniformities, e.g., "18C, must be resolved across wafers that are quite hot Že.g., 10008C..
8. Conclusion A broadband thermopile-based 1024-element infrared imager has been successfully fabricated using a conventional silicon CMOS process and micromachining technology. The array is aimed at applications in infrared thermometry for RTP systems. It has a millisecond time response with moderate responsivity and is sensitive across a broad range of infrared wavelengths. The array is formed with a process that requires only standard integrated processing steps and does not require silicon epitaxy, electrochemical etching, or deep boron diffusions. When combined with the infrared camera system, it provides a temperature resolution of "18C on target scenes up to at least 10008C.
Acknowledgements This work was supported by the Semiconductor Research under contract 96-FC-085. The authors would also like to thank Prof. K. Najafi, Dr. R.S. Toth, Mr. W.G. Baer, and Mr. Z. Cao for their many contributions. The work of Prof. F.Y. Sorrell and his students at North Carolina State University in applying these devices to RTP is also gratefully acknowledged. One of the authors is now with Sandia National Laboratories which is a multi-program laboratory operated by the Sandia Corporation, a
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A.D. OliÕer, K.D. Wise r Sensors and Actuators 73 (1999) 222–231 w19x S. in’t Hout, Analysis of a 1024-element thermal imager, Internal Report, University of Michigan Ž1991.. w20x H. Baltes, Future of IC microtransducers, Sensors and Actuators A 56 Ž1996. pp. 179–192. w21x D.B. Lee, Anisotropic etching of silicon, Journal of Applied Physics 40 Ž11. Ž1969. pp. 4569–4574. w22x A. Reisman, M. Berkenblit, S.A. Chan, F.B. Kaufman, D.C. Green, The controlled etching of silicon in catalyzed ethylenediamine–pyrocatechol–water solutions, Journal of the Electrochemical Society 126 Ž8. Ž1979. pp. 1406–1415. w23x S.T. Cho, An ultrasensitive silicon-based microflow sensor, PhD thesis, University of Michigan ŽApril 1991.. w24x P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Holt, Rinehart and Winston, Orlando, FL, USA Ž1987.. Andrew D. Oliver received the BSEE degree from Iowa State University, Ames, IA, in 1991, and the MSEE and PhD degrees in electrical engineering from the University of Michigan in 1993 and 1997, respectively. In 1997, he joined the Electromechanical Engineering Department at Sandia National Laboratories, Albuquerque, NM, where he is a senior member of the technical staff.
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Kensall D. Wise received the BSEE degree from Purdue University, West Lafayette, IN, in 1963, and the MSEE and PhD degrees in electrical engineering from Stanford University, Stanford, CA, in 1964 and 1969, respectively. From 1963 to 1965 and from 1972 to 1974, he was a Member of Technical Staff at Bell Telephone Laboratories. In 1974, he joined the Department of Electrical Engineering and Computer Science at the University of Michigan, where he is now the J. Reid and Polly Anderson Professor of Manufacturing Technology and Director of the Center for Integrated Sensors and Circuits. He is a fellow of the IEEE and the AIMBE and a member of the United States National Academy of Engineering.
A 1024-element bulk-micromachined thermopile infrared imaging array Andrew D. Oliver ) , Kensall D. Wise Center for Integrated Sensors and Circuits, Department of Electrical Engineering and Computer Science, The UniÕersity of Michigan, Ann Arbor, MI 48109-2122, USA Received 21 July 1998; revised 26 October 1998; accepted 29 October 1998
Abstract This paper reports on a bulk-micromachined silicon uncooled thermal imager intended for use in automated semiconductor process control. The device has a responsivity of 15 VrW, a thermal time constant of 1 ms, and a D) of 1.6 = 10 7 cm Hz 1r2rW. It is organized as a 32 = 32-element area array with on-chip address generation, multiplexing, and self-test circuitry. The overall chip size is 16 mm = 16 mm, with a 12 mm = 12 mm imaging area. Each detector consists of 32 n–p polysilicon thermocouples supported on a dielectric window and is micromachined using a novel combined front-undercut and back-etched process. An infrared camera system using the imager is also described. q 1999 Elsevier Science S.A. All rights reserved. Keywords: Thermopile; Micromachining Žbulk.; Infrared imager; Infrared camera; Thermal imaging
1. Introduction During the past few years, a number of very promising uncooled silicon infrared imagers have been reported w1–5x. These devices have used both surface- and bulk micromachining, and among the latter, both front-undercut and back-etched devices have been discussed. Surface-micromachined approaches have achieved high pixel counts Ž80,640 w2x and 16,384 elements w3x. and high responsivities, but generally require vacuum packaging because of the small distance between the detector and the substrate. However, for process control applications involving thermal imaging, vacuum packaging can be difficult to implement due to the wide spectral bandwidth Ž) 10 mm. required in the package window; in night vision applications, where many of the previous imagers have been targeted, sensitivity in the short to medium infrared range Ž- 5 mm. has usually been adequate w6x. In contrast, bulk-micromachined devices do not require vacuum packaging but generally exhibit lower pixel counts and responsivities. The performance of the bulk devices is nonetheless adequate for applications in process control, where
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Corresponding author. Electromechanical Engineering Department, Sandia National Laboratories, PO Box 5800, MS 0329 Albuquerque, NM 87185-0329, USA. Tel.: q1-505-845-7931; fax: q1-505-844-9554; E-mail: [email protected]
high accuracy in determining target temperature over a very wide dynamic range is more important than high spatial resolution. The primary application explored in this work is the monitoring of temperature uniformity over wafers in either rapid thermal processing ŽRTP. or reactive ion etching ŽRIE. systems. Initial work was focused on demonstrating that a silicon uncooled imager could resolve temperature variations to within the "28C level required by advanced process control. A linear bulk-micromachined NMOS imager w1,7x was used in an infrared camera that was interfaced to a personal computer for data acquisition and storage. This system was used on an Applied Materials 8300 hexode RIE at the University of Michigan and on a RTP system at North Carolina State University. Fig. 1 shows the output of a single array element viewing a 100-mm wafer during a polysilicon etch in the AM8300. Much of the data scatter may be due to noise induced in the system by the plasma and by the reactor pumps; however, temperature resolution is still within "0.68C. Fig. 2 shows a map of wafer temperature in RTP as a function of position w8x. To obtain the absolute temperature, special calibration runs were done and independent wafer temperature measurements were made using thermocouples. In this case, the temperature is measured to within "1.58C. These results demonstrated the usefulness of silicon infrared imagers in monitoring wafer temperature uniformity; however, two-dimensional imaging is needed
0924-4247r99r$ - see front matter q 1999 Elsevier Science S.A. All rights reserved. PII: S 0 9 2 4 - 4 2 4 7 Ž 9 8 . 0 0 2 7 6 - 3
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and not the absolute temperature itself. Bulk-micromachined thermopile detectors have the added advantage of not requiring vacuum packaging and can be batch fabricated using semi-custom or standard CMOS fabrication techniques. Thermopiles are inherently large, however, and the thermal isolation achievable is limited by the large number of leads involved. In this application, the pixels should be large enough to average the signal such that local differences in emissivity Že.g., due to oxidermetal patterning on the wafer. are unimportant.
2. Imager design Fig. 1. Output of a single detector on a 32-element array viewing a wafer during reactive ion etching.
for use in next-generation wafer processing at 0.25 mm feature sizes and beyond. This work sought to develop such an imager. In moving to an area array, the various transducer options were again examined. All thermally based infrared detectors convert incident infrared radiation into heat and then into an electrical signal. Both thermopiles and bolometers have been used recently as transducers w1,2x, and read-out options including the use chopping and selftest were also considered. Chopping is useful in moving the signal of interest away from the very low frequencies where 1rf noise is important w9x. However, because it consumes power and is mechanically more complex, it is accordingly less reliable. Self-test can be included in a thermal device relatively easily and is useful both for rapid testing after fabrication and for autocalibrationrautocompensation in the field w10x. It is an important means for reducing the test component of imager cost. In our application, the emphasis was on a low-cost uncooled design operating unchopped and insensitive to changes in ambient temperature. High reliability is especially important in semiconductor applications, where unscheduled downtime can cost thousands of dollars per minute. Thermopiles are attractive since they measure the temperature difference between the hot and cold junctions
Fig. 2. Wafer temperature as a function of position in an RTP system at North Carolina State University as viewed with a thermopile-based linear imager.
Previous effects on thermopile infrared imagers have mostly been limited to single-element detectors or to onedimensional linear arrays w1,4,5,11,12x. One of the two previously reported works concerning a two-dimensional thermopile array used a charge-coupled device ŽCCD. read-out w3x. The other used the gold bumps from a tape-automated bonding technology as an inter-element heat sink w5x. The two-dimensional area imager reported here is composed of an array of 32 rows and 32 columns of infrared detectors with a total of 1024 elements. Each detector has an active area of 300 mm = 300 mm and a total area of 375 mm = 375 mm. The imager is internally x–y organized like a DRAM with a per-pixel switch to gate the output of the individual detectors onto the column lines. The output signal is multiplexed from the 32-column lines onto one output line by an analog 32 to 1 column multiplexer. A three-stage CMOS opamp is available onchip via a bonding option to provide 10 = signal amplification. The digital portion of the device accepts a serial clock input that is used by an on-chip counter to generate a parallel 10-bit address. The address is then decoded by the row and column decoders in the same manner as in a static or dynamic memory. The organization of the imager is shown in Fig. 3.
Fig. 3. Organization of the 1024-element infrared imager.
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The imager also contains an on-chip bandgap temperature sensor formed using the parasitic substrate npn bipolar transistor that arises naturally in the CMOS structure w13x. This circuit provides a measured output sensitivity of 2.3 mVr8C and provides ambient temperature measurement to an accuracy better than 18C, which is sufficient for digital compensation of the imager in the infrared camera system. Each pixel is also provided with a polysilicon heating resistor that allows a known amount of power to be gated into the pixel from a test bus that runs parallel to the column lines. This allows the sensitivity of the detector to be checked at any time, simplifying device testing during manufacture and permitting self-test when in use. One important consideration in designing the infrared imagers was the fabrication of the per-pixel access switches that connect the thermopiles to the column lines. This architecture greatly reduces the amount of routing internal to the array of thermopiles. The design was complicated by initial uncertainty of how to fabricate these per-pixel access switches in silicon while still forming an etch stop on the silicon ribs that support the dielectric windows that form the detectors. The options for fabricating the switches and the etch stop were the following: Ž1. depositing lightly doped epitaxial silicon on top of a p q q diffusion defining the ribs, Ž2. integrating a thin-film transistor ŽTFT. on top of a p q q diffusion, Ž3. using an electrochemical etch-stop and placing the switch transistors in the monocrystalline epitaxial silicon, or Ž4. developing a process that did not depend on a p q q etch stop or an electrochemical etch stop. The choice of an etch stop will be discussed further in Section 3 but it was decided to also examine various methods for creating the switches that could be formed in or on a p q q etch-stop layer. The epitaxial switch option was discarded because of the increased process complexity and the difficulties of depositing monocrystalline silicon on top of p q q silicon. The TFT option, after some experimentation, was also discarded for the same reasons. 3. Micromachining Four micromachining options Žshown in Fig. 4. were considered for constructing the infrared imager. The structure in Fig. 4A is surface-micromachined. The infrared detector here is fabricated on top of a sacrificial layer of silicon dioxide or polysilicon. At the end of the fabrication sequence, the sacrificial layer is removed using a wet etchant, which leaves the infrared detector elevated above the substrate by the thickness of the sacrificial layer Žusually 1–2 mm.. These devices must generally be operated under vacuum to decrease the thermal conduction from the detector to the substrate. This technique has been used by Kanno et al. w3x to produce a 128 = 128 element infrared array . Surface micromachining has also been used to produce micromachined Golay cells w14x and infrared bolometers w2x.
Fig. 4. Five possible micromachined infrared imager structures.
Bulk micromachining Žshown in Fig. 4B–E. can also be used to thermally isolate an infrared detector w4,11,12,15x. In this technique, the bulk silicon itself is used as a sacrificial layer. The wide detector-to-substrate gap that results allows these imagers to be used at atmospheric pressure and simplifies packaging. The structure in Fig. 5B is similar to the ErD NMOS 32-element line imager reported by Baer et al. w1x. In these detectors, the micromachining is performed as a through-wafer back etch. There are two disadvantages to this structure. First, there is no simple way to put circuitry in the p q q etch-stop regions because of their high doping levels, and second, the heat sinks are only 15 mm thick Žthe practical diffusion limit., making the structure vulnerable to thermal cross-talk between pixels. Fig. 4C shows the bulk undercut structure that has been implemented successfully at ETH Zurich w4x, Stanford w15x, and at Michigan by Liu and Mastrangelo w16x and Oliver w17x et al. These detectors are micromachined from the front with an anisotropic etchant that produces a pyramidal etch pit beneath the infrared detector. An advantage of this technique is that it is done with standard CMOS fabrication technology and provides easy implementation of perpixel access switches as well as immunity from cold-junction heating using the bulk ²100: silicon as a heat sink. A disadvantage is that the imager has less thermal isolation at
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Fig. 5. Cross-section of a double-etched infrared imager. The pixel switches are integrated in the single-crystal ²100: silicon support ribs which act as heat sinks.
atmospheric pressure between the thermopile hot junctions and the bulk silicon than the back etched structure. Fig. 4D is an electrochemically etched infrared imager w17,18x. This method uses a lightly doped epitaxial layer for the support ribs and permits the formation of the active pixel switches. The epitaxial silicon is not typically thick enough to prevent some heating of the cold junctions, however. An advantage of this process is that it produces a device that can be illuminated and have a conductive infrared-absorbing layer applied from the back. The design that was eventually chosen is a combination of the front-undercut and the back-etched structures and is shown in Fig. 4E. The resulting structure has excellent thermal isolation at atmospheric pressure, can be illuminated from the back, has lightly doped single-crystal silicon where per-pixel switches are located, and has large heat sinks to reduce thermal cross-talk. A detailed crosssection of the device is shown in Fig. 5. This device has greater thermal isolation than the front-etched structure and greater immunity to cold-junction heating than the back-etched structure because the cold junctions are heat sunk with 60 mm of single-crystal silicon. It has the
simplicity of the front-etched structure and does not require an electrochemical etch-stop or a deep boron diffusion. The structure has two minor disadvantages: Ž1. the conductive heat losses through the gas surrounding the detector are slightly larger than the back-etched structure; and Ž2. the detector loses some area to the slits which provide the etchant access to the silicon on the front side.
4. Cold-junction heating One factor that can influence the output of an thermopile-based infrared detector is cold-junction heating w9,19x. Cold-junction heating occurs when a sudden change in the incident radiation causes the cold-junction temperatures to rise, thus also heating the hot junctions of the thermopiles and reducing the magnitude of the thermal gradients across the thermopiles. The thermopile’s hot junctions cannot change temperature instantaneously due to their thermal time constant and thus the temperature rise of the hot junctions lags the temperature rise of the cold
Fig. 6. Cold-junction heating. This figure shows the simulated output of the center pixel of an imager as it stares at a fixed 5008C target. All of the neighboring pixels stare at areas on the target that change from 5008C to 10008C in 5 s, starting at 0.1 s. The output of the center pixel, which should remain constant, is shown on the left axis while the target temperature viewed by the neighboring pixels is given on the right axis. The increase in the radiant flux absorbed by the neighboring pixels causes the cold junction temperature to rise, decreasing the center pixel output.
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junctions. Fig. 6 shows the simulated response of a single pixel imaging a target wafer in an RTP system which is experiencing cold junction heating due to a rapid increase in the radiant flux incident on the neighboring pixels. The transient error here is about 0.68C for 60 mm-thick support ribs but more than 2.58C for a 15 mm-thick support structure. Note that the effect disappears as soon as the temperature ramp is completed and the cold junction temperature stabilizes.
5. Fabrication In designing an integrated imager containing on-chip readout circuitry, it is important to optimize the fabrication steps for both the circuitry and the transducers. Circuit processes are complex and are typically not designed to allow easy modification. For this reason, and to facilitate technology transfer, the additional steps for forming the transducers are usually added at the beginning or end of the circuit process flow w20x, leaving the circuit process as undisturbed as possible. The imager reported here was fabricated using the standard University of Michigan 3 mm bulk CMOS process with modifications to accommodate dielectric window deposition and thermopile formation. The dielectric window is composed of the LOCOS field oxide, a silicon nitride layer, and the final passivation oxide. The thermopiles are formed using the second polysilicon layer in the Michigan CMOS process. They are doped either with a custom implant or with the same implant used to form the sources and drains of the transistors. In the first case, the Seebeck coefficients can be arbitrarily set; the second results in y200 mVr8C for the n-type polysilicon and q200 mVr8C for the p-type polysilicon. The passivation oxide protects both the circuitry and the thermopiles from the EDP. Contacts are etched through this layer to expose both the thermopiles and the circuitry, and the wafer is metalized with an EDP resistant layer of chromium and gold. The contact etch also opens slits in the pixel regions to permit the 300 mm = 300 mm pixel area to be undercut during the subsequent micromachining. To micromachine and separate the imagers, the wafer is dipped in a dilute HF–nitric–acetic acid mixture for 10 s and subsequently in buffered hydrofluoric acid for 30 s. It is then rinsed and placed vertically in EDP for 10 to 11 hours where the devices etch simultaneously from both sides. The wafer cross-section is shown as a function of time in Fig. 7. As the silicon etches from the front side Žat 40 mmrh., it starts to form a pyramidal pit underneath the thermopile detectors. The pit is bounded by the slow-etching ²111: planes on the sides and by the fast etching ²110: planes on the bottom. On the back, a large pit is also forming, bounded by the ²111: planes on the sides and the ²110: planes on the bottom. This is in accordance with Lee w21x, who states that on ‘concave’ surfaces, the
Fig. 7. Micromachining of the double-etched infrared imager as a function of time.
‘limiting shape’ is formed by the slowest etching planes. The heat sink beams are isolated when the front- and back-side pits meet. The isolated beams are a ‘convex’ structure, and the fast-etching ²311: planes start appearing at the corners and edges of the heat sinks. The etch is terminated when the heat sink beams are approximately 60 mm thick, trading-off thermal isolation of the hot junctions against susceptibility to cold-junction heating. A process window of between 40 mm and 80 mm in beam thickness has been found acceptable, resulting in a 30-min margin for overrunder etching. This process window requires a "1.4% control of etch rate or etch depth. In terms of temperature, the etch temperature must be maintained within 1.48C. The etchant used for this device is the type ‘S’ EDP reported by Reisman et al. w22x in 1979. Initially, type ‘F’ EDP was used for this device instead of type ‘S’ because ‘F’ etches ²100: silicon at 81 mmrh at 1128C instead of ‘S’, which etches at 54 mmrh at the same temperature. It was discovered, however, that type ‘F’ EDP did not have sufficient selectivity between the ²100: and ²111: planes and caused the sidewalls of the silicon heat sinks to be severely attacked. For a successful etch, the ratio between the etch rates of the ²100: to the ²111: planes must be at
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least 25:1. Examples of support ribs etched in type ‘F’ and type ‘S’ EDP are shown in Fig. 8. The EDP etch is done in a double boiler setup with the beaker containing EDP sitting in a glycerin bath. This
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procedure helps keeps the etchant at a uniform temperature and the etch rate consistent throughout the beaker. The uniform etch rate helps ensure that all the imagers are completed at the same time. The double boiler also de-
Fig. 8. The silicon support ribs Žheat sinks. on the double-etched infrared imagers etched in type ‘F’ EDP Žabove. and in type ‘S’ EDP Žbelow.. The imagers are viewed with the back side of the imager at the top of the picture.
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Fig. 9. Top view of a completed double-etched 1024-pixel infrared imager.
creases the amount and the vigor of the circulation of etchant in the beaker. Fig. 9 shows a portion of a completed infrared imager.
rear, although the single-crystal heat sinks tend to reduce the responsivity by slightly shading the thermopiles when the device is illuminated from the rear. To measure the amount of thermal cross-talk, the self-test function was
6. Experimental results The imagers were fabricated using the double-etched pixel design as shown in Fig. 5. All of the major circuit blocks were fully functional. The output of the on-chip bandgap temperature sensor is shown in Fig. 10 as a function of ambient temperature. The output slope is 2.7 mVr8C between 308C and 2008C, with a linear correlation coefficient of 0.9997. The temperature sensor occupies an area of 0.53 mm2 with 50% of the area consumed by the two common-collector bipolar transistors. The preamplifier is an analog three-stage CMOS opamp with n-channel MOSFET inputs w23,24x. The preamplifier has 12 transistors and uses a 5.8pF polyrpoly capacitor to ensure stability. Fig. 11 shows the input and corresponding output of the on-chip preamplifier. The closed-loop gain is 30. The preamplifier occupies an area of 0.16 mm2 and consumes 1.6 mW. This circuit is connected to the output of the column analog multiplexer by a removable link so that an optional external preamplifier can be used instead if desired. The pixels have a measured responsivity of 15 VrW, a thermal time constant of 7 ms, a resistance of 50–70 k V, and a D) of 1.6 = 10 7 cm Hz 1r2rW. The responsivity is aided by a smoked carbon black applied to the rear of the dielectric windows. Without the black, the responsivity is 10 VrW and the time constant is 1.6 ms. The devices can be illuminated from either the front or the
Fig. 10. Measured output of the on-chip bandgap temperature sensor as a function of ambient temperature and a photograph of the integrated sensor. The large structure on the left of the photograph is a common collector bipolar junction transistor.
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output of 220 mV from the primary pixel. is less than 1 mV; calculations predict thermal cross-talk of only 2 ppm, corresponding to about 440 nV.
7. Infrared camera system
Fig. 11. Input Žtop trace 20 mVrdiv. and correspond output Ž500 mVrdiv. from the on-chip closed-loop preamplifier on the imager and a photograph of the preamplifier. The serpentine structure at the bottom of the photograph is one of the feedback resistors.
used. The measured response of the nearest neighbor cell due to a 5-V input to the self-test resistor Žproducing an
The infrared camera system developed for use with the area imager can also be used with single-point w11x and 32-element linear w1x devices. It was designed to resolve small temperature differences over very high temperature scenes, to cope with scenes where the temperature is changing rapidly, and to compensate for electrical drift in the amplifiers. The camera, whose schematic is shown in Fig. 12, is based on a Motorola 68HC11 microcontroller and uses a 12-bit analog-to-digital converter ŽADC., a variable gain amplifier, and a 12-bit digital-to-analog converter ŽDAC.. The DAC is used to lower the dc level of the signal so that higher gain can be used in succeeding amplifier stages. This allows the resolution of small temperature differences on very hot targets. If the amplified signal from the infrared imager is outside the input range of the ADC Ž"5 V., the output of the DAC is automatically adjusted to bring the final value of the amplified signal back within range. The data is then transferred to a personal computer running ‘LabVIEW,’ which records and displays the data. The camera initialization and data acquisition routine is illustrated in Fig. 13. The camera starts by amplifying the signal from one pixel at low gain with the DAC set at 0 V. The ADC converts the analog voltage to a 12-bit number, and the value is recorded in the memory of the microcontroller. The next step is to measure the offset of the amplifier chain at high gain. This value is stored and digitally subtracted from the final value of each imager element. The camera then reads each pixel with the amplifier gain at its maximum value and the output of the DAC at a value calculated to bring the output of the last amplifier stage within the input range of the ADC without remeasuring the pixel at low gain. This amplification
Fig. 12. Schematic of the infrared camera.
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Lockheed Martin Company, for the United States Department of Energy under contract DE-AC04-94AL85000.
References
Fig. 13. Photograph showing the initialization and data acquisition routine used in the infrared camera system. The top trace is the output of the DAC, performing offset subtraction, and the lower trace is the input to the ADC for a constant input.
scheme minimizes the quantization error associated with the LSB, which is often important in semiconductor manufacturing applications where small temperature non-uniformities, e.g., "18C, must be resolved across wafers that are quite hot Že.g., 10008C..
8. Conclusion A broadband thermopile-based 1024-element infrared imager has been successfully fabricated using a conventional silicon CMOS process and micromachining technology. The array is aimed at applications in infrared thermometry for RTP systems. It has a millisecond time response with moderate responsivity and is sensitive across a broad range of infrared wavelengths. The array is formed with a process that requires only standard integrated processing steps and does not require silicon epitaxy, electrochemical etching, or deep boron diffusions. When combined with the infrared camera system, it provides a temperature resolution of "18C on target scenes up to at least 10008C.
Acknowledgements This work was supported by the Semiconductor Research under contract 96-FC-085. The authors would also like to thank Prof. K. Najafi, Dr. R.S. Toth, Mr. W.G. Baer, and Mr. Z. Cao for their many contributions. The work of Prof. F.Y. Sorrell and his students at North Carolina State University in applying these devices to RTP is also gratefully acknowledged. One of the authors is now with Sandia National Laboratories which is a multi-program laboratory operated by the Sandia Corporation, a
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A.D. OliÕer, K.D. Wise r Sensors and Actuators 73 (1999) 222–231 w19x S. in’t Hout, Analysis of a 1024-element thermal imager, Internal Report, University of Michigan Ž1991.. w20x H. Baltes, Future of IC microtransducers, Sensors and Actuators A 56 Ž1996. pp. 179–192. w21x D.B. Lee, Anisotropic etching of silicon, Journal of Applied Physics 40 Ž11. Ž1969. pp. 4569–4574. w22x A. Reisman, M. Berkenblit, S.A. Chan, F.B. Kaufman, D.C. Green, The controlled etching of silicon in catalyzed ethylenediamine–pyrocatechol–water solutions, Journal of the Electrochemical Society 126 Ž8. Ž1979. pp. 1406–1415. w23x S.T. Cho, An ultrasensitive silicon-based microflow sensor, PhD thesis, University of Michigan ŽApril 1991.. w24x P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Holt, Rinehart and Winston, Orlando, FL, USA Ž1987.. Andrew D. Oliver received the BSEE degree from Iowa State University, Ames, IA, in 1991, and the MSEE and PhD degrees in electrical engineering from the University of Michigan in 1993 and 1997, respectively. In 1997, he joined the Electromechanical Engineering Department at Sandia National Laboratories, Albuquerque, NM, where he is a senior member of the technical staff.
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Kensall D. Wise received the BSEE degree from Purdue University, West Lafayette, IN, in 1963, and the MSEE and PhD degrees in electrical engineering from Stanford University, Stanford, CA, in 1964 and 1969, respectively. From 1963 to 1965 and from 1972 to 1974, he was a Member of Technical Staff at Bell Telephone Laboratories. In 1974, he joined the Department of Electrical Engineering and Computer Science at the University of Michigan, where he is now the J. Reid and Polly Anderson Professor of Manufacturing Technology and Director of the Center for Integrated Sensors and Circuits. He is a fellow of the IEEE and the AIMBE and a member of the United States National Academy of Engineering.