A charge-based small-signal model for the bipolar junction transistor

0038-I101/91 $3.00+ 0.00 Copyright0 1991Perpmon Pressplc

Solid-State Electronics Vol. 34, No. 8, pp. 89PlO1, 1991

Printedin Great Britain.All rightsreserved

A CHARGE-BASED BIPOLAR

SMALL-SIGNAL MODEL JUNCTION TRANSISTOR

FOR THE

MWNGSUK Jo, HANJINCHO and DOROTHEAE. BURK Department of Electrical Engineering, University of Florida, Gainesville, FL 3261 l-2030, U.S.A. (Received

25 August 1990; in revised form 2 February

1991)

Abstract-A small-signal model for the bipolar junction transistor (BJT) is proposed which is derived directly from a very physical charge-based large-signal model. Because the large-signal model accurately accounts for the peripheral and intrinsic transistor current and charge partitions as well as the distributed base resistances and collector-base junction capacitances, the small-signal elements derived from this model accurately reflect the high-frequency and high-current operation of advanced BJTs. d.c. Verification of the large-signal model and preliminary a.c. verification of the small-signal model are achieved through comparisons of simulations and experimental (de-embedded s-parameter) data taken on advanced BJT test structures over a range of operating conditions and emitter areas. Because agreement between the measured and simulated data is good, it is concluded that this model is generally valid for advanced BJT simulation.

1. INTRODUCTION One figure of merit for the advanced bipolar junction transistor (BJT) is its unity gain frequency_& which is derived from small-signal s-parameter measurements[l]. The goodness of fit between the simulated and the experimental value for fT also reflects the certainty with which the different internal delays consisting of carrier transit times, lifetimes, surface recombination velocities (at polysilicon and metal contacts) and nonquasi-static effects, are known for the small-signal (as well as the large-signal) BJT model[2]. The small-signal model, for which the basic elements are derivatives from a large-scale model, often has to be enhanced with the addition of nonphysical (empirical) elements or the reoptimization of the derived elements from the large-signal model to account for some of these delays more accurately[3,4]. Recently, a one-dimensional charge-based largesignal model for the BJT has been developed and installed in user-defined-control-sources in SLICE by Jeong and Fossum[S]. This large-signal model for the intrinsic transistor, which is more physical than the Gummel-Poon model, includes an accurate representation of all the charges and currents in the BJT as a function of bias including the quasi-saturation region. It is derived from a one-dimensional regional analysis of the ambipolar carrier transport and the key model parameters (there are 27 model parameters in all) are taken primarily from layout and dopant profile (processing) information with minimal empiricism. One-dimensional quasi-static effects can be accounted for in the model by implementing two partition parameters for base charge in low and high injection. The emitter, base and collector recombination times are the only explicit time constants needed.

The other delays are implicitly taken into account in the charge dynamics. In this paper, we demonstrate the utility of a modified version of this charge-based model in the interpretation of small-signal measurements for contemporary npn VLSI test transistors[6]. The modified version represents the multi-regional nature of advanced BJT by including charge-based models for the peripheral transistor and extrinsic base-collector junction as well as the intrinsic transistor. We demonstrate that the charge-based small-signal model, which is derived from this “multi-regional” chargebased large-signal model, can adequately simulate the small-signal characteristics including fT at high frequencies (l-20 GHz) for a range of operating conditions and device sizes of interest to the device engineer without the need for additional circuit elements or modifications to existing circuit elements to account for discrepancies between the simulated and experimental data. In order to accomplish this, we extend the onedimensional large-signal model for the intrinsic BJT to include the peripheral parasitic BJT formed in the link region between the emitter-base junction and the extrinsic base-region, and the extrinsic base-collector junction. The peripheral and extrinsic BJT charges and currents are related to the equivalent intrinsic transistor terms by seven (additional) parameters taken from the layout geometry, dopant profile, or measurements. Three empirical parameters define the relationship between the peripheral and intrinsic region collector and base currents and charges as a function of bias and are taken from an approach by Rein[q. The model for the intrinsic base resistance, which separates the peripheral from the intrinsic base region, is taken from an extension of Hauser’s model[l], and includes high-injection effects in the 893

MYIJNGSUK Jo et al.

894

base and collector, and base pushout[9]. A fourth (empirical) parameter defines the relationship between this intrinsic base resistance and the peripheral base resistance[lO]. A technique for separating the junction capacitances between the intrinsic and peripheral transistor elements is utilized[l l] and the method for measuring the parasitic emitter, collector, and extrinsic base resistances are taken from[l2]. The last three parameters are the emitter time constant and the electron (base) diffusivity of the peripheral transistor and the ratio between the base-collector junction capacitance of the peripheral transistor to that of the extrinsic diode. We verify this multi-regional large-signal model by simulating the d.c. BJT measurements for different emitter areas over a range of bias conditions with above parameters. We then extract a charge-based small-signal model from this multi-regional large-signal model. Some of the large-signal input parameters, such as the peripheral emitter time constant and electron (base) diffusivity and the factor defining the proportionality between intrinsic and peripheral base resistance, may be fine tuned by fitting the small-signal responses, but this is not attempted here in order to strengthen the support for this small-signal modeling approach. Preliminary model verification is performed by comparing simulations with s-parameter data taken on advanced npn bipolar test devices[6]. The small-signal model is shown to be scalable and accurate over a range of device sizes and operating conditions of interest to VSLI device designers. Nonquasi-static effects in the vertical transisitor dimensions (emitter-to-collector) are accounted for by partitioning the base charge between the emitter-base and base-collector junctions in the one dimensional intrinsic and peripheral transistor models, while separation of the transistor elements into three (i.e. intrinsic, peripheral and extrinsic regions, or more if needed) discrete regions has a similar effect in the lateral dimension[l3]. With no additional optimization, simulations using this charge-based small-signal model are shown to be in good agreement with the (emitter-base) input port and (collector-emitter) output port y-parameters. The calibration of the s-parameter measurements and their conversion to y-parameters is discussed briefly. More extensive verification of the small-signal model over a larger range of device geometries is left for future work.

currents and charges, the extrinsic p +/n junction, and the parasitic resistances will be discussed in the next section. In Fig. 1, the geometric and equivalent circuit representations emphasize the differences between the intrinsic and peripheral transistors. In the multi-regional model, these transistors have a common emitter and collector terminal, but the potential at the base of the peripheral transistor is offset from the intrinsic transistor base by the potential drop across the intrinsic base resistance, R,, . The edge of the polysilicon contact, fabricated in the emitter window opening, marks the boundary between the intrinsic and peripheral transistor regions. The extrinsic base resistance Rsx, the emitter resistance R, and the collector resistance R, are assumed constant. The intrinsic model parameters and the procedures for their extraction have already been given in Ref.[S]. However, the seven additional parameters needed to build the multi-regional model and the procedure for their extraction are presented next.

B

0

2. THE MULTI-REGIONAL MODEL AND PARAMETER DEFINITION

The multi-regional large-signal model (as is the case for the Jeong and Fossum model[5]) is at present incorporated into SLICE (SPICE) in user-definedcontrol-sources and will in the future be directly incorporated into SPICE source code. The relationships between the intrinsic and peripheral transistor

Fig. 1. The geometric and circuit representations

for the intrinsic (subscript I) and peripheral (subscript P) transistors. The intrinsic transistor’s lateral boundaries are defined at the edges of the polysilicon contact to the emitter.

Small-signal model for the bipolar transistor A. The collector and base currents

1.0

895

l-

The complete definition of the collector current for low and high injection and for normal, quasi-saturation, and inverse mode operation for the intrinsic transistor is given in eqns (8)-(10) in Ref.[S]. To show the relationship between the intrinsic and peripheral transistor currents, the approach by Rein[q is used, but more generally valid expressions for the intrinsic and peripheral collector currents Zcr and Zcr are: ZC,~ACI[exp(~)

- exp($)]

Zc.APCr[exp(F)

-exp(F)]

(1)

Cr. &JP GI -=-WE,. C, & GP This ratio is the product of the ratio of average diffusivities &, and &, and of the Gummel numbers G, and GP for the intrinsic and peripheral base regions, respectively; WE, is the length of the emitter junction at the sidewall in the peripheral transistor (see Fig. 1); Vas, I/Bsr, V,, and V,,, are the respective quasi-Fermi-level separations across the emitter-base and base-collector space-charge-regions (SCR) as in Ref.[S]. Using the Rein approach, the intrinsic and peripheral current components are redefined to have explicit dependencies on the emitter window area A and the total emitter window peripheral length P, resepectively. The peripheral collector current can be rewritten as[7]: (21

where Cr kh-E_exp I

VRBI I/ . (3) T) Vm, is the potential drop across R,,, and yc is a function of bias and defines the current ratio at the emitter-base junction. This latter parameter is extracted from the slope of the collector current as a function of the ratio P/A. Collector spreading which might effect yc is accounted for independently in the intrinsic transistor model[5]. The functional dependence of yc on collector current density as measured using the Rein approach above is given in Fig. 2. The functional form of yc is: yc =yco+ac

0.7

0.8

0.9

I

I

1.0

1.1

V,,(Volts)

Fig. 2. The experimentally derived yc compared with simulation using eqn (4). Although the data is taken for V, = -2 V, we use the same fit for simulations at v,=ov.

where

ZCP= Ycf Zc,

i.6

bination currents. The last two components of base current in eqn (23) of Ref.[S] are typically negligible in advanced BITS. The base-emitter space-chargeregion recombination current is also negligible at intermediate and high current levels. Then, the base currents are: Zs,~ABr[exp(!$)

Z~,dPBr[exp(~)

This is used directly in the modeling herein, but can be further fine-tuned by fitting the measured d.c. data. The intrinsic and peripheral base currents Zs, and Zr,r.are assumed to be predominantly emitter-recom-

- exp(F)]

(5)

where

BP JEOP -_=-w 4 JEOI EP’ JEOIand JEOP are the emitter recombination

current densities at zero bias, Using the Rein approach, the peripheral base current is simplified to:

(

02 .

- exp(F)]

ZBP =

Ye f

ZB,.

(6)

We assume yBis not a function of bias. This is a rough approximation and its value is fixed during the simulation of the d.c. and a.c. data[l4]. B. The charges

In general, this quasi-neutral represented as:

emitter charge can be

QEE,=

?E lB1

(71

QEEP =

%PzBP

63)

where rs is the emitter time constant which governs the hole transport and recombination in the monocrystalline emitter and polysilicon contact. rE and rep are constant because low injection conditions prevail in the heavily doped emitter. Values for rE are given in Ref.[ 151for polysilicon contacted emitters with and without interfacial layers. (In this reference, the

MYLJNGSUK Jo et al.

896

quasi-static emitter delay r, for majority carriers has to be multiplied by the current gain fi to get ?E here.) 7E has little effect on the d.c. simulations but its extraction is especially important for the small-signal model. zEP can be assessed from profile information of the peripheral region or zEP can be assumed to equal 7E initially and then optimized from the smallsignal measurements. The quasi-neutral base charges are the sum of the respective electron Q, and ionized dopant Q, charges at the edges of the space-charge-region or:

QBB=QN+QJE-QK~

(9)

From Refs[S] and [7], the final simplifying relationship in our model is:

Qeel

(10)

where the ratio of the diffusivities can be assessed from dopant profile information with a similar procedure as suggested in Ref.[9]. Unlike the previous treatment for one-dimensional model[5], the junction capacitance charges Q,z,, Q,ar, QJCI 7 QJCP are derived from low frequency ac. measurements of the junction capacitances. A new technique has been developed to separate the peripheral and extrinsic region capacitances from the intrinsic region capacitances and is described in Ref.[ll]. The base-collector junction capacitance is further separated between the peripheral transistor and the extrinsic p +/n junction by assuming some fixed ratio for the extrinsic to peripheral region. This may be taken to be -4 after Rein and Schroder[l4]; or this ratio may be taken from layout information as done here; or this ratio could be a fitting parameter taken from small-signal measurement optimization; or the extrinsic region capacitance may be obtained from the slope of (~~~1as a function of frequency[ 161. The ratio of the peripheral to intrinsic charges QscR,, QscRP, QQNR, ,QQNRPin high injection is taken to be the ratio of the respective collector currents. QSCRI and QscRP are the excess electron charges in the space-charge-region of the collector for the intrinsic and peripheral BJT, respectively. QscR, and Q SCRPare the excess electron charges in the quasineutral epitaxial collector. The partitioned base and collector charges QeE,, Q,,,, Q,,, , QecP are defined as[ 171: QBE = QEE + QB~ + QJE + Qqmfc Qec = Qee(l -_A) + QJC + QQNR(~ -fc)

(11)

where & and fc are the charge partitions between the emitter-base and base-collector junctions. They account for nonquasi-static effects in the one dimension and are assumed to be 0.5. The smallsignal response is not extremely sensitive to the specific value of fe and fc for the transistors under investigation[ 181.

C. The resistances The model for intrinsic base resistance is an extension of Hauser’s model for emitter crowding. It includes the high injection effects and base pushout implemented in the intrinsic transistor model and the details are given in Ref.[9]. The peripheral transisitor base resistance is: R,, = FR RB, +

(12)

CP

where FR is one of the seven additional model parameters. FR can be extracted from small-signal measurement of the base impedance as described in Ref.[ lo]. The accurate distribution of base resistance between the intrinsic, peripheral and extrinsic regions (R,, > RBp and RBx, respectively) is important in modeling the effect of the frequency-dependence of a.c. crowding[lO]. We assume the parasitic resistances R,, R, and Rc are independent of applied bias, but they are scalable. They are measured using the techniques of Park and Neugroschel[l2] and [19]. Only the parasitic collector resistance Rc is needed for this model. The epitaxial collector resistance is included in the currents and charges in the intrinsic transistor model[5]. D. The small-signal elements The small-signal elements, taken from derivatives of the large-signal charges and currents are given in Table 1 and Fig. 3. The small-signal elements have been derived after considerable rearrangement of the derivatives between the nodes as discussed in Refs[20] and [17]. Because the charges and currents depend on the independent variables VeE, V,,,, Vsc and VBCpr the derivatives of these terms are capacitances, resistances, transcapacitances and transconductances. The transcapacitances appear in the imaginary parts of the transimmittances Y,,,~and y,,. A special circuit simulator has been written which takes the output derivatives of the large-signal model including the transcapacitances and computes the small-signal circuit response. 3. RESULTS AND DISCUSSION

A. d.c. Verljication of the multi-regional large-signal model The test devices have self-aligned polysilicon contacts to the emitter and base with a boot-shaped in between. The drawn sidewall spacer -0.4pm2 emitter areas vary from 1 x 4pm* to 2 x 12 pm*. Data for yc, ye, C,, and C,, have been measured on all these devices. The experimental data was taken using an HP 4145 network analyzer with the parameter extraction software (TECAP). Simulations of I,, ZB, p vs VBEusing the multi-regional large-signal model are given in Fig. 4 for a representative device. All the model input parameters are given in Table 2.

897

Small-signal model for the bipolar transistor Table 1. Small-signal model parameters*

ah,

gti=av, _.$-~_~

go=

Bc

av,,

ak

aQsE? dQscP

aQaE, aeac,

+=dY,,,+dY,,,

Cm=K+K

aesw 8QscP

c =de,,,+de,, av,

r

-aem

co=----

cflp = av,,+av,,

av,

--8QBcx cscx-avscx

aQaEP --aQscK,aQsm ah ak

avsc av,,

Y,; = gmi+jbmi ak a*, b

_aQeEl aerIc, aQsca,+aQsca, avsE avsE ah :

ml av,

Y,, = g,,

+.ik,

=dlsp+al, av,, av,,,

gmp b

dQsw aem

_

mpak

:

aesm aQscRP +

a~,,, a~,,, a~,,

‘These are approximate small-signal elements in that some of the smaller terms have been left out. Also the derivation of these elements has required the rerouting of some of the voltage-controlkd current sources in our model via a technique given in Ref.[lS].

measurements taken on each device. The definitions of the intrinsic transistor parameters are taken from Ref.[S].

The profile information for these transistors is taken from Ref.[6]. All the parasitic resistances and junction capacitances have been determined by independent

Collector

rc ’

bcx

I

r” 0

II

rPP

Base :: r bx

‘,!%I 7.

r

LA .1

AL VV

%i

rbi

r bx

._

L. .

__ rap

caP

: rxi

%I Y mi*“bp

Y mp’ “bep

1

ro

co

Emitter Fig. 3. The network representation of the multi-regional elements appear similar to Gummel-Poon (SPICE) elements, different. Their relationship to the charges and currents of The transmittances y, and y,,

charge-based small-signal model. Although their magnitude and physical origins are very the large-signal model are given in Table 1. are imaginary.

MYUNGSUKJo er al.

898

80

20

0.5

0.8

0.7

0.8

1.0

0.9

0i

1.1

0.5

0.8

0.7

0.8

0.9

1.0

1.1

Fig. 4. Simulations using the multi-regional large-signal model of d.c. measurements for an advanced BJT structure having emitter window dimensions 0.7 x 3.2 pm*. The plot of j vs Vs, depends on V, = 0 V (-_O-) and V, = -2 V (- - 0 - -). The model input parameters for the simulations are given in Table 2.

The goodness of the fits between the simulated and experimental data in Fig. 4 exemplifies the accuracy of the multi-regional model for varying transistor size and in high-current operation. These fits can be obtained for all the transistors. The input parameters which depend on the emitter area are the only parameters varied during the fitting process. These parameters are the emitter length L, and width We and the parasitic emitter and collector resisitance

Ra and Rc. (These parameters are given for three different emitter areas in Table 2.) At high currents, the simulation of /I vs Vs, at Vat = 0 V is not as accurate as at Vet = - 2 V. We attribute this discrepancy to error in yc (V,,,). We use the yc taken from fits to the Vat = -2 V data, but yc is also to second order a function of Vs,. By more careful fitting of yc at V, = 0 V better d.c. fits can be obtained at this bias.

Table 2. Model input parameters

Pmvmterscomma"toall transktors~ W,, = 1.24 x IO-‘cm

N,, = 8.0 x 10”cm-’ wa,, = 0.375 x IO-km

NEP, = 2.5 x 10’6cm-’ M, = 0.4 luc = 0.43 wc, = 0.22 x IO-‘cm y,=O.l27fim n ss = 2.2 rE = 1.0 x 10-9s

PE= 1.1 PC= 0.75 D,, = 7.5 cm* s-’ cc=20 x 10esA/cm’ JsEo= 1.43 rc = 1o-5 c, = 0.5 C ,aO, = 2.60 fF/pml C JcoP = 1.25 fF/pm M, = -0.34 C JCCNR-537fF -

c ,=o, fs = .#+ = Mc = rEP = 6,, =

0.441 o.5 fF/pm’ 0.822 V -0.342 0.8 x W9 s 6.5 cm’ s-’

Size-dependent 4 RC

L&m) WEtim)

R." ‘Most of these parameters

70 18.5 3.2 0.7

100

are defined in Ref.[S].

Ws, wjg

I ;I:, $O;:cm

yco = JEo = ‘Is= c, =

6.5 x 10-2pm 9.14 x IO-“A/cm* 1.0 x 10-6s 0.5

c ,aoP fc=o.5 = 1.40 fF/pm c JECNR -- 157 fF Qk=o.66v C,=54fF

parameters

60 16.5 3.2 0.95 95

q=2.6 = 1.5 x 10-6cm

50 11.2 7.3 0.7 80

Small-signal model for the bipolar transistor

899

1o-2

4 .Z

SJ

E

1o-3 ----_HN

i

1o-4

108

108

10'

IO9

Frequency

10'0

I:::

IO"

(Hz)

106

107

108

109

Frequency

r

10'0

IO"

(Hz)

10-l

5

r

30

.E B 1o-2 ----_--__ E

\) i

2 _i 1o-3 108

10'

108

108

Frequency 10-2

10'0

,

,

10"

(Hz)

100

10'

108

109

Frequency

r

101:

10"

(Hz)

-30

s

H

-60

z

-90

%

-120

t

: -150 -190

ro-81 106

I 107

I

I

108

109

Frequency

I

I 10'0

IO"

lo6

10'

(Hz)

106

10s

Frequency

(Hz)

IO-'r

106

10'

108

Frequency

109

10'0

(Hz)

Fig. 5. Simulations of the phase and (at V, = -2 V). V,, = 0.85 V (-) and at [sE = 0.85 V (0) and Vs, = 0.95 V (A), m fT. Only one set of data is provided

10"

108

10'

106

Frequency

109

10'0

(Hz)

magnitude of y-parameter for the 0.7 x 3.2fim2 device Vs, = 0.95 V (- ---) are compared with experimental data respectively. These values of V,, are chosen near the peak if both sets overlap on the plot for the sake of clarity.

10"

MYUNGSUK Jo

900

B. a.c. Vertjication

et al. (a)

20

High-frequency measurements (45 MHz-265 GHz) were taken using an HP 8510 Network Analyzer. Cascade Microtech probes were mounted on a probe station which was enclosed in a screen room. The s-parameter measurements were calibrated up to the probe tips using an 1% (Cascade Microwave) calibration substrate. Then the device-under-test (DUT) was measured and the y-parameters of the on-wafer calibration patterns were subtracted from the embedded-device measurement.? In Fig. 5, the simulations of the high-frequency experimental data are given for a 0.7 x 3.2 pm* transistor in the commonemitter configuration. (The simulations for the larger emitter-area 0.7 x 7.2 pm* are similar to these, but not included for the sake of brevity.) The simulations using the charge-based model are in good agreement with the extracted y-parameters for the bias conditions near peak fT. The largest disagreement (- 15-25”) between measurement and simulation occurs in the phase of y2*. The admittance of the output port of the advanced BJT is much smaller than the contact pad and interconnected parasitics in the s-parameter test pattern. Therefore, when the s-parameter measurements are interpreted by de-embedding the transistor from these parasitics, there is considerable experimental error. In addition, in our model, we have not considered the distribution of the collector-substrate capacitance Cc, with collector resistor Rc. If both discrepancies are accounted for the simulation and data should be in better agreement. In Fig. 6, simulated and experimental data for fr vs I,(V,,) are given for the two transistors. The agreement between these data is good at peak values off, and within the experimental error. Although the overall shape of the simulated data is dependent on the model and its parameters (Table 2), the peak values infr are very sensitive to the intrinsic emittertime constant rE . We use 7E = lo-’ s which is a value in agreement with our earlier predicted values of the emitter delay (74/l) for the polysilicon-contacted emitters[ 151. 4. CONCLUSIONS

The charges and current in the peripheral and extrinsic regions of the bipolar junction transistor have been delineated using the approach of Rein[7] and with reference to the charge-based intrinsic transistor model of Jeong and Fossum[S]. The resulting multi-regional large-signal transistor model has seven new parameters in addition to the original 27 parameters for the intrinsic transistor model and is verified with fits to d.c. data taken on contemporary bipolar test structures. tRay Vaitkus at Corporate Headquarters, Motorola, Tempe, AZ, helped us interpret these s-parameter measurements.

r

01 1 o-5

1o-4

1o-3

1 o-2

1o-3

1o-2

IC F-w4

20

r

01 10-S

(W

1o-4 1 c Ww)

Fig. 6. Simulations of the experimental data for fr vs I, (Pa,) for (a) the 0.7 x 3.2 pm2, and(b) 0.7 x 7.2 pm2 devices at V,, = -2V for Vss = 0.85 V (-,O) and for vs,=o.95v (~~~-,o).

A small-signal equivalent model is derived directly from this large-signal model and data for the deembedded device-under-test is extracted from s-parameter measurements. Preliminary verification of this small-signal model has been presented by accurately simulating this experimental data for the (commonemitter) y-parameters of an advanced bipolar junction transistor without any optimization of any parameters relative to the small-signal characteristics. The simulation of the experimental data of fT as a function Ic( V,,) demonstrate that a zE = lo-’ s in agreement with previous work on polysiliconcontacted transistors and charge-based BJT modeling. It is also shown that the inclusion of peripheral transistor in the model is essential to accurate smallsignal modeling of the advanced BJT. Model verification over a more extensive range in device size is left for future work. Acknowledgements-The authors would like to acknowledge H. Jeong, J.-S. Park, M. Choi, and Professors J. G. Fossum and A. Neugroschel for helpful discussions. They would like to thank Dr Ray Vaitkus and Doug Scheiltin for their help with the s-parameter measurements, and Dr P. J. Zdebel at the Motorola Inc., Mesa, AZ for the test devices and pertinent information. They especially would like to acknowledge the many discussions they have had over the interpretation of the measurement with Dr Ray Vaitkus and the interpretation of the simulation with Dr.Peter Zdebel and John Prentice at Harris, in Melbourne, FL. This work was supported by Semiconductor Research Corp., grant no. 90-SP-087.

Small-signal model for the bipolar transistor REFERENCES

1. G. W. Taylor and J. G. Simmons, Solid-St. Electron. 29, 941 (1986). 2. J. van der Biesen, Solid-St. Electron. 29, 529 (1986). 3. J. van der Biesen and T. Toyabe, IEEE Trans. Computer-Aided Design CAD-7, 855 (1988). 4. S. W. I.aux, IEEE Trans. Electron Devices ED-32,2028 (1985). 5. H. Jeong and J. C. Fossum, IEEE Trans. Electron Devices ED-36, 124 (1989). B-L Jeong, Ph.D. dissertation, University of Florida (1989).] 6. P. J. Zdebel, R. J. Balda, B.-Y. Hwang, V. de la Torre and A. Wagner, Proc. IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN (1987). 7. H. M. Rein. Solid-St. Electron. 27. 625 (1984). 8. J. R. Hauser, IEEE Trans. Electron’Devices Ed-H, 238 (1964). 9. M. Jo and D. E. Burk, IEEE Trans. Electron Devices ED-37, 202 (1990). 10. H. Cho and D. E. Burk, Proc. IEEE Bipolar Circuits and Technology Meeting, Minneapolis (1990).

901

11. M. Jo and D. E. Burk, IEEE Trans. Electron Devices ED-37, 317 (1990). 12. J. S. Park and A. Neugroschel, IEEE Trans. Electron Devices ED-36, 88 (1989). 13. M. A. Green and J. Shewchun, Solid-St. Electron. 17, 941 (1974). 14. H. M. Rein and M. Schroter, IEEE Trans. Electron Devices ED-34, 1752 (1987). 15. S.-Y. Yung and D. E. Burk, Solid-St. Electron. 31, 1139 (1988). 16. P. J. van Wijnen and L. C. Smith, Proc. IEEE Bipolar Circuits and Technology __ Meeting. -. Minneanolis. MN. 91 (1988). 17. M. Jo and D. E. Burk, Proc. IEEE Bipolar Circuits and Technology Meeting, Minneapolis MN, 111 (1988). 18. J. G. Fossum, H. Jeong, D. E. Burk and M. Jo, Proc. IEEE Bipolar Circuits and Technology Meeting, Minneapolis MN, 10 (1987). 19. Discussions with V. de la Torre from SPICE modeling, Advanced Technology Center of Motorola Semiconductor Sector, Mesa, AZ (1988). 20. R. S. Mutter and T. Kamin, Device Electronics for Integrated Circuits, p. 278. Wiley, New York (1977). L