A critical look at modular adders using residue number system

Solid State Electronics Letters 1 (2019) 84–91

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Solid State Electronics Letters journal homepage: http://www.keaipublishing.com/en/journals/solid-state-electronics-letters/

Research paper

A critical look at modular adders using residue number system K. Vijaya Vardhan a, K.M. Santhoshini a, Sarada Musala b, Avireni Srinivasulu c,∗ a

Dept. of Electronics & Communication Engineering, Vignan’s LARA Institute of Technology & Science, Vadlamudi, A.P, India Dept. of Electronics & Communication Engineering, Vignan’s Foundation for Science, Technology & Research, Vadlamudi, A.P, India c Dept. of Electronics & Communication Engineering, JECRC University, Jaipur - 303905, Rajasthan, India b

a r t i c l e

i n f o

Article history: Received 17 November 2018 Revised 26 October 2019 Accepted 13 November 2019

Keywords: Forward conversion Reverse conversion Chinese remainder theorem Mixed radix conversion Modulo adders

a b s t r a c t Presently, computer scientists and researchers show greater interest in one of the ancient techniques, namely, Residue Number System (RNS) to use in different fields. In this paper, an introduction to RNS and Modular adders, their overview and detailed explanation are presented. In the RNS system, conventional data is encoded to RNS data in the first stage referred to as forward conversion. Later the reverse conversion is needed which decodes RNS data to conventional data. Among the conversions, the reverse conversion is more complex over the forward conversion. The decoding process can however be performed by availing the Chinese Remainder Theorem (CRT) or Mixed Radix Conversion (MRC) technique. In RNS applications such as modular multipliers, digital signal processing (DSP) applications, residue to binary converters, etc. The crucial component was modular adders, so that some of the modular adders are presented at the end of this paper. © 2019 KeAi Communications Co., Ltd. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license. (http://creativecommons.org/licenses/by-nc-nd/4.0/)

1. Introduction Nowadays, Residue Number System (RNS) plays a vital role in a number of applications. The development of RNS has been considered as long as electronic digital PCs exist and is therefore drawing noteworthy attention from the research community. This technique was invented by the Chinese mathematician namely, Sun Tzu in the 3rd century. He had proposed riddle; as we have things, suppose the remainder is two if the things are counted by three or seven. Similarly, the remainder is three if the things are counted by five, then how many things would be there? In the recent terminology the residues and moduli are represented as 2, 3, 2 and 3, 5, 7 respectively. Sun Tzu had suggested Tai-Yen (Great generalization) solution for this riddle. In 1247, Qin Jiushau redefined this Great generalization as the Chinese Remainder Theorem (CRT) which is considered a mathematical jewel. In the year 1950s, some of the computer scientists have reintroduced RNS for the fast arithmetic and error-free calculations. RNS therefore has three properties that are well-suited for different applications. Those are; 1. The carry propagation was a speed limiting factor mainly in addition and multiplication. In RNS, the carry propagation was ignored. 2. Since there is no propagation of carry in RNS, the digit positions are not affected even if there is an error in that position. 3. In RNS, there is no significance of ordering the digits, which suggests that the malfunctioning digit-positions can be denied with no impact other than a decrease in a unique range. Because of the following reasons, RNS was not being familiar; i. The computer arithmetic unit at least has to perform addition, multiplication, division, square-root, and comparison. In RNS, addition and multiplication are easier than division, square-root, and comparison. ii. Presently, computer technology has been more trustworthy. iii. The reverse conversion, i.e., RNS to Conventional notation is more difficult for human perception. Due to several reasons, in modern period, there has been a revived curiosity in RNS. Some of them are, in RNS, there is an ignorance of carry propagation expedites, the design of low power arithmetic and high speed which is used in mobile devices and so on. PC chips ∗

Corresponding author. E-mail address: [email protected] (A. Srinivasulu).

https://doi.org/10.1016/j.ssel.2019.11.001 2589-2088/© 2019 KeAi Communications Co., Ltd. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license. (http://creativecommons.org/licenses/by-nc-nd/4.0/)

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are right now advancing to be truly thick that full testing won’t be conceivable; along these lines adaptation to internal failure and furthermore, the general space of computational honesty have extra turned out to be increasingly vital. Due to technology advancement, there has been huge progress in designing of the arduous arithmetic operations such as division, square-root, and comparison, etc. Due to enhancement in RNS, these are mostly made use of in many applications such as, DSP, DIP, Speech Processing, Communication Engineering, Cryptography (Computer Security) and transforms in which multiplication and addition operations are critical arithmetic operations [1,2,5,6]. The addition is the basic arithmetic operation in arithmetic circuits. An addition can be performed by different adders. The implementation of an efficient RNS adder is an important task in designing different RNS based applications. Modular Adder plays a vital role in the implementation of residue-based DSP applications and it is therefore an essential component in RNS multipliers and residue to binary converters. This paper is structured into different sections. Section I provides the RNS fundamentals. Forward and reverse conversions are discussed in Sections II and III respectively. Section IV presents different modular adders. Finally, Section V provides Conclusions. 2. Fundamentals of RNS Residue Number System (RNS) is an ancient and devoid of weight in number system. The implicit property of RNS is that it can perform activities like multiplication, addition, and subtraction, the result of any digit position depends on the digits present in that position only. An RNS can be defined by moduli set {m1 , m2 …, mn } where mi is the ith modulus value, and these values are relatively prime integers. In RNS, an integer ‘Y’ is denoted as a group of compact integers known as residues and the residue set is defined as {r1 , r2 … rn } where ri is the ith residue value. The residue ri is defined as the minimal possible remainder when Y is divided by the modulus value mi . Technically, the affinity can be defined in regards to the congruence as,

Y mod mi = ri

(1)

The above congruence can also be rewritten as,

|Y|mi = ri

(2)

All integers ‘Y’ uniquely represented in RNS that lie in its “dynamic range”. The dynamic range is given by the moduli set {m1 , m2 …, mn } which is notated as ‘M’ where

M = ni−1 mi

(3)

In RNS, all the integers in the range 0 to M-1 are peculiarly depicted. Thereafter, more than one integer might be having the same residue depiction. The prime moduli set are relatively chosen so that the RNS is necessary to provide a peculiarly depicted position, that exists in the dynamic range i.e., 0 to M-1. Very few applications require the representation of signed numbers. To acquire that, we can split the entire range (0 to M-1) to almost two equivalent parts. In this the first half and second half depicts positive and negative numbers respectively. Integer ‘Y’ is defined in eqns (4) and (5) with respect to odd and even.

M−1 M−1 ≤Y≤ 2 2 −

M M ≤Y≤ −1 2 2

if M is odd if M is even

(4) (5)

If Y= {r1 , r2 …, rn } represents a positive number in the approximate range, -Y can be indicated as {r¯ 1 , r¯ 2 , . . . , r¯ n } where r¯ i is the mi ’s complement of ri i.e., r¯ i satisfies the relation (r¯ i + ri ) mod mi = 0. Different arithmetic operations are performed on numbers represented by RNS. Consider the moduli-set S = {m1 , m2, …, mn }, and ‘A’ and ‘B’ are two RNS integers and indicate as follows: A = {a1 , a2 , …, an } and B = {b1 , b2 , …, bn }, then the addition operation between A and B is

C = A + B = {c1 , c2 , . . . , cn } where ci = (ai + bi) mod mi The same is applied for subtraction also. The modulo operation for addition and subtraction can be written as;

  |A ± B|mi = |A|mi ± |B|mi m

i

Multiplication operation in RNS is similar to addition and subtraction operations. In multiplication operation simply multiply the independent residues with respect to the co-relate moduli. It can be represented as follows;

A = {a1 , a2 , . . . , an } and B = {b1 , b2 , . . . , bn } Then the multiplication operation between A and B is denoted by

C = A ∗ B = {c 1 , c 2 , . . . , c n } ci = (ai ∗ bi )modmi The modulo operation is distributive over multiplication;





|A × B|mi = |A|mi × |B|mi 

mi

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K.V. Vardhan, K.M. Santhoshini and S. Musala et al. / Solid State Electronics Letters 1 (2019) 84–91 Table 1 Residue representation of integers with two moduli sets. Y

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

{2, 3, 5}

{2, 3, 4}

2

3

5

2

3

4

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0

0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0

0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2

The real downside of the modular multiplication structures is their extensive areas in light of the fact that every arithmetic operation is trailed by a modular reduction. In cryptography algorithms, such as elliptic curve cryptography (ECC) and Rivest-Shamir-Adleman (RSA), modular multiplication are the most difficult operations. Montgomery multiplication uses 3 or 5 co-prime numbers in moduli set for the majority of modular multiplier designs [28]. In RNS most difficult operation is Division. The division in conventional representation is as follows: a/b = k, which can be rewritten as a = k × b, where k is the quotient. In RNS, the analogous congruence is: b × k = a mod m While the multiplicative inverse of b was applied on both sides, and then the above expression is rewritten as

k = a × b−1 mod m 3. Forward conversion The inputs to and outputs from any residue system are in the same conventional form. The procedure for converting the conventional data which is in decimal or binary form into RNS form is called forward conversion. This conversion is simpler than the reverse conversion. Based on the input conventional data (Decimal or Binary) form, the forward conversions are of two types- Decimal to RNS, and Binary to RNS respectively. 3.1. Decimal to RNS conversion In the forward conversion process, the input conventional data (decimal) is divided with each modulus value in the selected moduli set and then collects the remainders for each division. This operation is costly when the number was represented in arbitrary base or radix and with an arbitrary modulus. For example, representation of integers in the residue format in two distinct residue systems defined by two different moduli sets {2, 3, 5} and {2, 3, 4}, which is shown in Table 1. From the example in the 1st residue system, the moduli set {2, 3, 5} are relatively prime, then the system’s dynamic range is 0 to 29. The integer’s representation in this range is unique. Whereas in system 2, the moduli set {2, 3, 4} are not relatively prime, because ‘2 is the common divisor for 2 and 4. Due to this, the representation of integers is unique only in the range 0 to 11. Therefore, the modulus values in the moduli set must be a relative prime to get a higher dynamic range. 3.2. Binary to RNS conversion Input conventional data is binary, the forward converters are classified into two different types, that depends upon moduli set used, and those are forward converters based on arbitrary moduli set and the other type is forward converters based on special moduli set. First type converters are designed to availing look-up tables (LUT) and other types are designed by using combinational logic circuits. The later

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simplifies the conversion architectures and algorithms. For forward conversion, the hardware designs are depending on combinational logic circuits, look-up tables, or a combination of both. In some specific applications, the conversion difficulty depends on the selected moduli set. An application like signal processing attain a large dynamic range, for this purpose moduli set consist of either a few numbers of large relatively-prime integers or more number of compact relatively-prime integers. In normal course the first case is preferable. The memory requirement for these converters needs both the number of modulus values in the moduli set and the magnitude of the modulus numbers [5]. 3.2.1. Forward converter for special moduli set The design of forward converters based on special moduli sets contains large modulus values are easy for large dynamic ranges which needs the use of compound processing units. Usually, special moduli are generally referred to as low-cost moduli, because the conversions to and from their residues can be implemented relatively easy, due to difficult operations like calculation of multiplicative inverses, multiplication, etc. not involved [20]. Generally availed special moduli set in forward converters are {2n − 1, 2n , 2n + 1}. Residues can be calculated by dividing the input number ‘A’ by 2n −1, 2n , and 2n +1 separately. Let’s define m1 = 2n − 1, m2 = 2n , m3 = 2n + 1. The input binary number ‘A’ is represented in three n – bit partitions of P1 , P2 , and P3 as

A = P1 22n + P2 2n + P3

(6)

Residue w.r.t moduli {2n − 1, 2n , 2n + 1} is given as [5].

Residue ‘r2 ’ with respect to 2n = P3

(7)

Residue ‘r1 ’ with respect to

2 − 1 = |P1 + P2 + P3 |2n −1 n

(8)

Residue ‘r3 ’ with respect to

2 + 1 = |P1 − P2 + P3 |2n +1 n

(9)

The values of P1 , P2 , and P3 are calculated by using the following relations [3,4]:

P1 =

3n −1 

2j−2n a1j

(10)

2j−n a1j

(11)

j=2n

P2 =

2n −1  j=n

P3 =

n−1 

2j a1j

(12)

j=0

Applications like digital signal processing (DSP) require wider dynamic range produced special moduli sets. Generally such moduli sets are denoted as extended special moduli set, like {2n − 1, 2n , 2n + 1, 2n + 1 − 1} for ‘n’ is odd and {2n − 1, 2n , 2n + 1, 2n + 1 + 1} for ‘n’ even [21]. 3.2.2. Forward converters for arbitrary moduli set Arbitrary moduli sets are used for applications where a wider dynamic range is needed and a special moduli set to put some constraints. The implementation of fewer complex processing devices in subsequent processing of small magnitude arbitrary numbers are chosen for such a moduli set. Still, the forward conversion is not simple, as in special cases, since it cannot be fulfilled by an effortless partitioning of input data [22,23]. In this case, the forward converters for arbitrary moduli set are designed by using look-up table (LUT). All possible residues of modulus numbers are available in the look-up table (LUT). The amount of memory required for this is very large [24]. If the input number ‘A’ is indicated with n- bits, as an-1 an-2 … a0 , then

A=

n−1 

2j a1j

(13)

j=0

and

    n−1   | A| m =  2j a1j   j=0  m     n−1   j 1   = 2 aj  m  j=0

(14)

(15)

m

are provided in a look-up table (LUT). The values are enabled or disabled depends upon whether ‘aj ’ is 0 or 1 respectively. A modulo addition of all enabled values in the LUT can be obtained by using modulo – m adder with the use of a collector [10].

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4. Reverse conversion Basically, after the completion of the residue-arithmetic operation, the reverse conversion process is used. The decoding of RNS data to conventional data which is in the binary or decimal format is referred to as Reverse Conversion. This process is more complex compared to forward conversion. Most of the used techniques in this conversion process depends on the CRT [7,8], MRC [9] and new CRT [27]. Piestrak has proposed high-speed residue to binary converter for the moduli set {2n , 2n – 1, 2n + 1} is based on New CRT [25]. The converter comprises of two stages of full adders and one stage of 2n –bit one’s complement adder. Carry Save Adder – End Around Carry (CSA – EAC) is used for the realization of full adders in the converters. Piotr Patronik, Stanislaw J. Piestrak have proposed reverse converters for a new flexible RNS Five – Moduli set {2k , 2n – 1, 2n + 1, 2n+1 – 1, 2n-1 −1} with n is even, by using Adders and Multiplexers [26]. 4.1. Chinese Remainder Theorem (CRT) A residue system has moduli set {m1 , m2, …, mn } with dynamic range,

M=

n 

mi

(16)

i−1

A residue number can be indicated as {a1 , a2, …, an } and can be converted into decimal number B. By availing Chinese Remainder Theorem (CRT), the conversion process is as followed [5]: Firstly, by availing Eq. (3) calculates the dynamic range M of the residue system. Later, find the values of Mi ’s and their inverses by using the following Eqs. (17) and (19):

Mi =

M mi

(17)

The multiplicative inverse |a−1 |m of a number a, w .r .t modulus ‘m’ is defined by

 −1    a  a = 1 m m

(18)

Then by the definition

 −1   M1 



m1

M1 

m1

=1

(19)



As m j s are relatively–prime in pair-wise, Eq. (19) is valid Then finally the decimal equivalent of B is

B=

n 





 Mi ai M−1 i

(20)

mi

i=1

The B defined in Eq. (20) is not present in the dynamic range of given RNS, and then a reduction modulo M defined in Eq. (21) will generate the number which presents in the given range [5].

    n  −1    |B|M =  ai Mi mi Mi   i=1 

(21)

M

Example. Assume the moduli set {2, 3, 5} and the residue representation of B is {1, 2, 4} then find the decimal equivalent of B using a CRT. [29] The dynamic range of a residue system M = 2 × 3 × 5 = 30, Then find Mi’s and their inverses:

M1 =

M 30 M 30 M 30 = = 15, M2 = = = 10, M3 = = =6 m1 2 m2 3 m3 5

Hence

    −1  −1 M1 M−1   1 = 1 ⇒ 15M1 3 = 1 ⇒ M1 = 1 Also, M−1 = 1 and M−1 =1 2 3

Then, according to CRT, B =| Where Bi = Mi M−1 i

3 i=1

bi Bi |30

B = |(1 × 15 × 1 ) + (2 × 10 × 1 ) + (4 × 6 × 1 ) |30 = |59 |30 = 29 In case of CRT based reverse converters, the conversion process can directly be mapped to Carry Save Adder (CSA) with End Around Carry (EAC), Ripple Carry Adders (RCA), Carry Propagate Adders (CPA) and Parallel Prefix Adders.

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4.2. Mixed Radix Conversion (MRC) Another method of conversion of RNS number to conventional data is MRC. In this calculation of large modulo M (Dynamic Range) does not exist and also yields a lesser complexity of 0 (n) as compared to the CRT whose computation complexity of order 0 (n3). RNS number A is given as {a1 , a2 , …, an } for the RNS based system with moduli set of {m1 , m2 , …, mn } then the number A was representing uniquely in mixed-radix form as [9]:

A = {z1 ,z2 ,...zn } Where A = z1 + z2 m1 + ... + zn mn−1 mn−2 ...m1 Where 0 ≤ zi < ri

(22)

Then find the values of ‘z’ using Eq. (22) |A|m1 = z1 = a1 . To get the value of z2 rewrite the Eq. (22) A-z1 = z2 m1 + … + zn mn-1 mn-2 …m1 , then applies modulo m2 on both sides: |A − z1 |m2 = |z2 m1 |m2 , then |m−1 | multiplies on both sides 1 m2

 −1   m1  (A − z1 )m2 = |z2 |m2 = z2 since z2 < m2 m2

But: |A − z1 |m2 =||A|m2 − |z1 |m2 |m2 = |a2 − z1 |m2 Therefore, z2 = ||m−1 | (a − z1 )|m2 1 m2 2 Similarly, the value of z3 was obtained z3 = ||(m2 m1 )−1 |m3 (a3 − (z2 m1 + z1 ))|m3 In general





zn = (mn−1 . . . m2 m1 )−1 

mn

 (an − (zn−1 mn−2 . . . z2 m1 + z1 ) )mn

Based on the above equations, the MRC is an implicitly a serial technique. The major disadvantage of using the MRC technique is to getting zi required of generating of zi − 1 at first. The CRT faster conversion technique compared to MRC because in CRT simultaneous computation of the partial sums Ai’s is seen. Example. Find the conventional representation of residue – set {2, 3, 1}, for the moduli set {3, 4, 5} using Mixed Radix Conversion (MRC) method. Step 1: First, find the required inverse values, starting with |m−1 | 1 m2

 −1  m1 

m2

 × m1 

m2

   = 1 ⇒ m−1 1

as follows:

    =3 × 3 = 1 ⇒ m−1 1 m2 m2 4

Similarly, we have to find another inverse|(m2 m1 )−1 |m3

      (m2 m1 )−1  × (m2 m1 ) = 1 ⇒ (m2 m1 )−1  × 12 m3 m3 m3 5   = 1 ⇒ (m2 m1 )−1  = 3 m3 Step 2: Find the z1 , z2 , and z3 values by using the above equations:

z1 = a1 = 2





 z2 = m−1 1



× ( a 2 − z 1 )

  z3 = (m2 m1 )−1  m2

m3

m2

= |3 × (3 − 2 )|4 = 3



× ( a 3 − ( z 2 m 1 + z 1 ) )

= |3 × (1(3 × 3 + 2 ) )|5 = 0

m3

Step 3: Find the conventional number A by using Eq. (22)

A =z1 +z2 m1 +z3 m2 m1 = 2+(3 × 3 ) + (0 × 4 × 3 ) = 11 5. Modular adders Modular adder is the primary element in the implementation of RNS based applications such as digital signal processing, reverse converters, multipliers, etc. Basically, modular adders are of two types: generic modular adders and special modular adders. The moduli set used for modulo adders are of two types: those are specific moduli set and arbitrary moduli set. A lot of research has been going on in the field of implementation of general modular adders, which are nothing but modular adders with the specific moduli set. The moduli set consist of 3, 4 or 5 modulus values. The modular adders are designed by using three different design methods, those are 1. Purely combinational logic circuit method, 2 look-up table method and 3. hybrid implementation. A good number of researchers have discussed modular addition, which is given in the following paragraphs. Dilip and Banerji have proposed modular addition, by using look–up tables. In this addition process, all modulo m residues from 0 to m-1, are hold in a storage element. In the modulo m sum table, the pth component of line q relates to the total │q + p│m . For information of sources A and B, the contents of the storage element are circular and shifted to left by A positions; B picks the right part of the storage element to be ported into the total storage element. The adder circuit consists of a decoder and rotating logic circuits [11]. Modular adders for the moduli in the form (2n + 1) based on binary adders were presented by Agarwal and Rao. In their proposal first they have defined a representation of numbers in modulo 2n +1, and they would be using carry look-ahead adder (CLA) for fast addition and modular complementation is also presented [12].

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Taylor has proposed modulo ‘p’ adder that can do both addition and subtraction. The subtraction operation can however be done by negating one of the operands. The proposed modulo ‘p’ adder will map the sum of two operands in Zp to their modulo ‘p’ sum. A few methodologies to this issue have been propelled which include either reaching a counterbalance to aggregate or utilizing a combinational rationale to outline radix - 2 whole into it’s modulo p esteem. The authors have created a design for a programmable modulo 2n , 2n ± 1 adder utilizing this guideline [13]. Magdy A. Bayoumi and G. A. Jullien have presented Very Large Scale Integrated design of modular adders using the above said three different design methods, and those implemented methods are analyzed in the view of VLSI criteria, the time and area are the critical measures. In the end, they have concluded that there is no method that was suitable in all aspects; individually each one is the best for particular types and magnitudes of moduli. They have presented further that a modular adder contains two CLA binary adders along with multiplexer. In this, the addition can be done as follows:

b = |a1 + a2 |m = a1 + a2 if a1 + a2 < m = a1 + a2 −m if a1 + a2 ≥ m

(23)

The first CLA adder performs addition between ‘a1 ’ and ‘a2 ’, then the second one performs a1 + a2 − m. Carry is produced from the 2nd adder, represents whether or not a1 + a2 is greater than ‘m’. The carry from 2nd adder controls the mux for the correct output [14]. Dugdale has proposed the designing of modulo ‘m’ adder using sequential circuit latches, binary (CLA) adder, two inputs MUXs and one output MUX. The first input MUX has two inputs ‘a’ and 2n − m where 2n − m is the correcting factor. The second MUX has inputs ‘b’ and ‘sum’ of the first cycle, which is (a + b), the two inputs MUXs are controlled by add control signal, similarly the output MUX has two inputs those are sum outputs of two cycles and this MUX was controlled by the output of an OR-gate. It has two inputs and those are carry outputs of two cycles. Modular addition was performed in two successive cycles with the same binary adder. The output MUX is used to select the result may be from the first cycle or from the second cycle [15]. Piestrak S. J. Fast-track have described a multi operand modular adder. In residue to conventional conversion, modulo ‘m’ adder is placed in the last stage. This adder operates using a CSA. The modular adder comprises a couple of binary Carry Save Adders (CSA) and an output MUX; both adders are operated in parallel to each other. The CSA computes (A + B – m) as a sum ‘S’ and a carry ‘C’ vectors. The first binary adder performs A + B and the second adder performs S + C. The output MUX selects one of the two adder outputs as result [16]. Reto Zimmermann has presented new Very Large Scale Integration architectures for modulo (2n ± 1) adders based on parallel-prefix adder architecture. Most effective adder designs for the complete range of area-delay trade-offs are presented in prefix adders. These are from the least ripple-carry adder to the quickest carry look-ahead adder. To carry out fast end-around carry adders, the parallel-prefix adder design is appropriate [17]. Hiasat presented modulo ‘m’ adder, which depends on carry propagate and carry generate functions of (A + B) and producing the generation and propagation functions of (A + B – m). A Carry Look Ahead (CLA) produces the output carry based on carry generate and propagate functions of (A + B) or (A + B – m). The chosen functions are performed with binary adder [18]. Vergos and Efstathiou have presented a modulo ‘m’ adder with 2 binary adders and an output multiplexer. The 1st binary adder performs (A + B). The 2nd adder internally consists of CSA, due to this reduction in 3 operands to 2 with n half-adders (HA) or n pseudohalf-adder (HA) circuits. The adder 2 performs the addition of the sum and carries vectors produced by CSA. The output MUX has two inputs which are the outputs of the two adders, it will select one of the adder output as the result based on the output carry. R. A. Patel, M. Benaissa, and S. Boussakta have designed Modulo-specific modular adder. They have presented a modular adder with specific modulo2n − (2n − 2 + 1), it was different from the modular adder with modulo (2n ± 1). The presented adder was used in fast multiplier architectures and also in Digital Signal Processing (DSP). Jaberipur, G., Parhami, B., Nejati, S. have presented a modular adder uses a δ representation, which is a special type of representation. The presented addition circuit is efficient in terms of time & area. It requires extra hardware when converting the δ depiction into RNS. Shang Ma, Jian-Hao hu have presented modulo adder with the moduli in the form of 2n − 2k − 1(1 ≤ k ≤ n − 2) can provide a better match among the RNS channels for multi-channels RNS handling. In their proposal, a novel algorithm and its usage structure in VLSI was discussed. The simultaneous prefix operation and carry correction methods are availed to overcome the carry re-calculation in the proposed algorithm. Once the presented modular adder was compared with the same type of conventional structures, the presented modular adder gives better outcomes as far as area and delay are concerned. Most of the above said modular adders consists of a couple of n – bit binary adders: 1st adder to perform A + B and the other one is to perform A + B – m. In addition to these adders a gate-based multiplexer is used to select any of the two outputs from the binary adders subsequently. For this purpose, different alternates are used to decrease the time, area, or both. Ahmed Hiasat has presented a modulo (2n ± K) adder. In the proposed adder consists combination of two adders into one, this allows the sharing of components, especially in the preprocessing and sum-computation stages. In addition to this merged adder, a tri-state based multiplexer stage was used instead of utilizing conventional gate based multiplexer stage [19].

6. Conclusion This paper gives the presentation of the Residue Number System. In this, translation of conventional data which is in decimal or binary form to RNS form and vice versa is presented with an example. Some of the algorithms like CRT and MRC are carried out while decoding of RNS data to conventional data. The reverse conversion is complex compared to forward conversion. Along with these, different modulo adders are also discussed. When compared to all modular adders discussed above the last modular adder presented by Ahmed Hiasat provides better results in terms of speed, power consumption, and area. These RNS adders are availed in different applications of RNS such as RNS multipliers, computer security (cryptography), speech processing, image processing, embedded applications and so on.

K.V. Vardhan, K.M. Santhoshini and S. Musala et al. / Solid State Electronics Letters 1 (2019) 84–91

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Declaration of Competing Interest The authors confirm that the content of “A Critical Look at Modular Adders using Residue Number System”, article has no conflict of interest. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29]

S.S. Nicholas, I.T. Richard, Residue Arithmetic and Its Applications to Computer Technology, McGraw-hill, New York, 1967. A.S. Michael, J. W Kenneth, J. Graham A, T. Fred J, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, 1986. G. Bi, E.V. Jones, Fast conversion between binary and residue numbers, Electron. Lett. 24 (9) (1988) 1195–1197. B. Vinnakota, V.V. Bapeswara Rao, Fast conversion techniques for binary-residue number systems, Inst. Electr. Electron. Eng. Trans. Circuit. Syst. 14 (12) (1994) 927–929. B. Premkumar, A. Omondi, Residue Number systems: Theory and Implementation (Vol. 2), World Scientific, 2007. A. Svoboda, The numerical system of residual classes in mathematical machines, in: International Federation for Information Processing Congress, 1959, pp. 419–421. K.A. Gbolagade, G.R. Voicu, S.D. Cotofana, An efficient FPGA design of residue-to-binary converter for the moduli set {2n + 1, 2n, 2n – 1}, IEEE Trans. on Very Large Scale Integr. Syst. 19 (8) (2011) 1500–1503. K.A. Gbolagade, R. Chaves, L. Sousa, S.D. Cotofana, An improved RNS reverse converter for the {2 2n + 1 – 1, 2n, 2n – 1} moduli set”, in: In Circuits and Systems (ISCAS), Proceedings of Institute of Electrical and Electronics Engineers, International Symposium, 2010, pp. 2103–2106. K.A. Gbolagade, S.D. Cotofana, An O9n0 residue number system to mixed radix conversion technique, in: Circuits and Systems (ISCAS), Proceedings of Institute of Electrical and Electronics Engineers International Symposium, 2009, pp. 521–524. U.N. Thakur, S. Mallick, R.M. Moitra, S. Zakaria, A. Chakraborty, C. Mukherjee, FPGA based DEfficient architecture for conversion of binary to residue number system, in: 8th Institute of Electrical and Electronics Engineers, Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), 2017, pp. 700–704. K. Banerji D., A novel implementation method for addition and subtraction in residue number systems, Inst. Electr. Electron. Eng. Trans. Comput. 23 (1) (1974) 106–109. D.P. Agarwal, T.R.N. Rao, Modulo (22 + 1) arithmetic logic, Inst. Electr. Eng. J. Electron. Circu. Syst. 2 (6) (1978) 186–188. F. Taylor, “S single modulus complex ALU for signal processing”, in: IEEE Trans. Acoustics Speech and Signal Processing, 33, 1985, pp. 315–325. G. Jullien, M. Bayoumi W. Miller, A VLSI implementation of residue adders, IEEE Trans. Circu. Syst. 34 (3) (1987) 284–288. M. Dugdale, VLSI implementation of residue adders based on binary adders, IEEE Trans. Circu. Syst. II Analog Digit. Signal Process 39 (5) (1992) 325–329. S.J. Piestrak, Design of residue generators and multioperand modular adders using carry-save adders, IEEE Trans. Comput. 43 (1) (1994) 68–77. R. Zimmermann, Efficient VLSI implementation of modulo (2n ± 1) addition and multiplication, in: Proc.14th Institute of Electrical and Electronics Engineers Symp. Computational Arithmetic, 1999, pp. 158–167. A. Hiasat, High-speed and reduced-area modular adder structures for RNS, IEEE Trans. Comput. 51 (1) (2002) 84–89. A. Hiasat, General modular adder designs for residue number system applications, Inst. Eng. Technol. Circu. Dev. Syst. 12 (4) (2018) 424–431 Iss.. F. Barsi, Mod m arithmetic in binary systems, Infor. Proce. Letters. 40 (1991) 303–309. P.V. Ananda Mohan, Residue Number System: Algorithms and Architectures, Kluwer Academic Publishers, Dordrecht, 2002. G. Alia, E. Martinelli, ‘A VLSI algorithm for direct and reverse conversion from weighted binary number to residue number system’, IEEE Trans. Circ. and Syst. 31 (12) (1984) 1425–1431. G. Alia, E. Martinelli, VLSI binary-residue converters for pipelined processing, Comput. J. 33 (5) (1990) 473–475. B. Parhami, C.Y Hung, Optimal Lookup Schemes For VLSI Implementation of Input/Output Conversions and Other Residue Number Operations, VLSI Signal Processing VII, Institute of Electrical and Electronics Engineers press, New York, 1994. J. Stanislaw Piestrak, A high-speed realization of residue to binary converter, IEEE Trans. Circu. Syst. II Analog. Digit. Signal Process. 42 (10) (Oct 1995) 661–663. S.J. Piestrak, P. Patronik, Design of reverse converters for a new flexible rns five-moduli set {2k , 2n − 1, 2n + 1, 2n+1 − 1, 2n-1 − 1} (n even), Circu. Syst. Signal Process. (2017). Y. Wang, ‘Residue-to-binary converters based on new Chinese remainder theorem, IEEE Trans. Circu. Syst. I 47 (3) (20 0 0) 197–205. M. Vesterbacka, S. Asif, An rns based modular multiplier with reduced complexity, Institute of Electrical and Electronics Engineers Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SOC), 2017. P.V. Ananda Mohan, Residue Number Systems Theory and Applications, Birkhauser publisher, 2016, doi:10.1007/978- 3- 319- 41385- 3.