A high level synthesis algorithm including control constraints

Microprocessing and Micmprogrammi,!g35 (1992) 271-278 North-Holland

27 t

A High Level Synthesis Algorithm Including Control Constraints F r a a q o i s V e r d i e r , A b d e l h a k l n t Safir, B e r t r a n d Z a v i d o v i q u c ETCA/CREA/SP 16his. A v e m t e p r i e u r de l a C b t e d ' o r , 9 4 1 1 4 A r c u e i l C o d e x , F R A N C E E m a i l : verdier~Getca.fr, safiri-"etca.fr, z a v i d o ' ( ~ e t c a . f r

Dala path ~vnthesqs ;rod routru] i)~tt s)'ulhe~is ate, strongly interdependent. This [act vindicates a nt~vel apllrt)at h for early con~l'ol optilnization in terms o[ tile numl)Ln" o[ COFlil~landB,while data path is slill al Ih~ very heghulh,g singe uf its synthesis. The scheduling algorithm is base([ on stochastic searching guided by a co~l ['unction to be mininfized. In urder to take into account the control aspect op~hnizafion, a slm!,lc u.tm i, ah:hd to the cost I'unction used in the scheduling process. This term is mewly a statisticM measme of tile Control Data Flow Graph regularity, since our conjecture is Ihal lira mort: regular the ('I)FG. tin" simpler the Control Part..Mork, over, this simple extra measure ol" reguhui U during scheduling permits to perform scheduling and binding, in sequence, without decreasing l h e solution (lua[ily.

1

Introduction

Th,, claxslcal 1~14k5ill ]limb llwP[ ~yllt hesis are : • h)r dala

pat]l synlhesi~ : scheduling, operator Mloca~ion and operator assignment (or [)perator binding).

* for rontro[ l)at't s)'ntheslw : irtstruclion schednling, slatfy ilssigllliii i11 illld boolettn optimization. In lastly syslt,nis l]lesc two tasks (data path and coal to[ synthesis)

;ire

perforn~ed in two successive stl,ps

([tl].[l:l].[19]). The first step provides a data path layout from a behavioral description of the Mgorilhm to he imlfle;nenled. The second step provides a control part description from the data path and assoclattwl ('DF(; using a control state graph. Since these two slops a]'(' sLiOtlgI)" interdependent, as will be shown afterwards, such artilicia[ splitting hamper~ the quality of Ihe solul ion. ),hwh work has he+!n dolle on data path synthesis alm~e [l;I i and control part synthesis once the data path is srl f(11,[5],[81,[10],[1ll,[t2]). The technique,s used for c~)ntl'o] pilll ~ylllh(,si5 ;11"~1has,,d lllainly oi1 nlicrocode optltnlzali,,,t Ior nllcrl~programmed conlrollers and 0II bo~*h,an Ol,qmizal hm for [ilfit e slat4, machine controllers. faking irllo accounl earlier control cormtraints oll the high level syrltlwsis [n'ocess {such as co[flrol part area. mnttber of c011trol signals) wouhl mal,:e possible a ~reater uptimizatio!l of the contr,-:l part. Integrating

contlol considerations into data path synthesis comes hack tn ELF [6]. In this system, the optimization alg()rlthm, which is based on graph grammar, uses a cost fimction with a control signals complexity measure to estimate control overhead, but only in terms of control inter(:onnectiort contplexity alld estimate too toughly the real cost of the final control part design [ie surt'ace, perth)finance). In Yorkstown Silicon Compiler ([:1].[4]), structural synthesis is mainly oriented towards minimizing control states, but it is not, clear how the data path constraints are handled. On++ of the most recent systems is CHIPPE ([2]), which takes into account a nnrnber of constraints. Its underlying method is based ~v iterativ,- refinement of an architecture not targeted (unlike t L.VI'HEDttAL II [7] or SYCO [21]) to a specific type of applications. Some control aspects are taken into account during scheduling, but they are limited t.o delay consideratiom. Wr therefore present a method enabling the integration of global control aspects (for example the total area of the hardware lnodnle~ Jtee(led to implement the control part) by using the notion of regular~ly of the CDFG during scheduling. This measure is horrowed from a slatlsticaI estimalion of the complexity (the diversity) of dala tranfers in the final design. The philosophy for attempting to provide a g ~ba solution to tile whole process of syntimsis is a contimlation of SOlll(.previous work that we will mention brielly in the next section ([16],[18]). The purpose of this paper is twofohl :

272

F. Verdier et ~t

The next *col, ion describes the sys;em whic}i we include control constraints ~n. In Section .3. we give the needed definitions and represenl;ations of the ptoblcm, and explain in detail (in ,qeclion 4) the solution implemenled through a simple example. In Section 5 we give the results obtained with the flftt~ order wave fill,m>example and c¢mclnde by plesenLing filtilre works in tile last st?orion.

S y s t e m Description

2

Previous work (Fig.

1) ai our labor;fiery led to lhe

dm'<,M ........ t o t two algorithms ( [ t q . [ltll, [17]. [18]) : [ sltlliiltaneollsly [)(!rfol-itlS schedtlling, operator allocMion and In(idule soll!ctiOli using tile shnul;iit.d ;mncalhlg lefhlllqtie I h a i WI' t'llllatl(t?(] hy ;I ps('lldO doli;rntinist](: control t(,cilniqlJp Ih~t st'lkI'l'ti<~s in a "lcalislic" design si)~t-i,,

• :\]~olilhili

Ing ] Optzmtzatlo~l Sysh ~, Ot¢rlxlu I. I:iI'sl ~o volif 3 i,ur initial conjecture : " l l w Iil(tl'l. reTulla I hc ('I)F(T i*. I h,' simpler is i he toni re] pail "" nl,,ailill~ thai Ib,. lllol,' I<'!~pll ir lho ( ' l ) l : G is. th,' less exp,'n-iv,' Iln l!,llli o[ lllll'{ inpuls, illlOI'C!nlllit,l>h.i1 i,'Ti>l+'r <,) is l]ll' ,ll>laily<'~l ~(llulion.

i A l g o l i l l n l i II i.s a glottal clpthiligation a I g o r i l h m whictl SililllltallOOllSly pof[Orll]S opel-atop binding aild ll,gisl(,i' nil!riling, while takilig, l i l l e account illl~.rcollli(.cl, hig i-()sl allil tloorl)billllili ~, The >Olil'lTh I]H a l~OC)d solilfi<)ll whh'h &CI'OIIIIIN for I.w level pii):i,d mnleMinl~ lochniqtle agaill Ilut !lore hilpio~vd tJ~ R ~tls('illlSti(" tccllllillUl: Iml'r, Jwod l¥Otll (h'ciS]Oll t hliory.

~. ~¢'1,lll/[ ?41 iJlt'-i'lll ;I i1'¢ ]llliqllV ft>r lllOa<-Iilillg "'( '1)!"(; ll'e/lli~lii3". ;i;l3. tltv s, il(,t]li]ill~ I,I,wv~- i!~ ]-,,~,;~li,,li i- <,,i il~ ll,rlli~ of d.> iiiiii]ll(.I iJr ,,]u'iah,i- ,niul~il~li,,i a,l,h'r . ) !]~i ;li,'il i'l*lili)lll;lli,)li /llid iH il'l'll/- 111 !hr" tluIid,l'l of m , c l m w c,,-~l~,+ fl,] [Joi't})l NI;lllCl, ¢'o111],111;tl ]1>Ii. %it' ..].,'a" ; . l h i . ],i,p('i llial ~x+.,)Dlsdl/ <,'w'r,d s,J]illlOllS

r:hh lit,. s,,,,,l. ,osl t]llWlillll in ]Ullll': of i11,.ii illld p~'il~)llllglnl'p. }1111 l]ll'sl' ~<)luiioliS. dosl)ito lilt" [/i(l thai (11!'$ ~+'I I(i I Iw qalllip ilI'(';l ~tllfl level (if p(,i fqtl'llNIllC('. ;Iro >l ill ,liir,.r,..~ h,.,.;,,,.,, i~ i..,,~ i'~, it( I Iy 11w s;lmo schvduh,. ~1). ~ h ,~I tl(ll's l]lllk,- /h(, diff,'lcnr,. ,' I he ,liff(,r.u<'~, is iv~U]alily ! of a ~,.i o[ ,q.'~al,)rs. nqlnl~or ot machhw. , ych. s ;trill il~ tlm_ularily Illf'iiSllrl'. In fa*t. ~t hl'n ltlO scho,hllill~ [ilil# ['~ i~ p¢'rfol'lliOd, il acl~ ¢[]rt'r't]~." till I Ill >i'[?~llial il} (if i ] ~ giaph. \Vc ll;,~ i' I }loi't,foro found th,' ll.ll,Valll l].alurl,s of a ('l)l"(; it, -qualify- what we ,a]I "w,,4ulaiily" ;in+l l,, comilill(, this ild'ornuiliilll in?(~ ;i stillisiical ~;,i'i;11)1¢, ('Oli~Ollly'llrt'5 of l a k i n g illlO ll('clJllrll such ilifl'lllNIlil)ll aiJOIll I(lll{l'O] ll)llill]OXlty will tie drawn in I it" ( onl luSlOlL

r h . search in ~he design q)ace is 14ui(l('d hy Ihe global Illild IBIZIll itJn or a <'<)st full('[ ioll ltl/it, i11(']1[(]1~7iippll(.iLt i<)l i collTIlaiill:~ aild s w;IOlii characll~risli(-s a~> fiJllmvs : • For alp>lirithln I : ( "o~i .r{ mn,fatx~. [p(H]ol-ll}Tin(.c+ pOWel~ . . . ) • 14,r aJgulii}llii il : 'osl = f( IIoarplannll~g m l r f a c e , mlmbcr of rogislcrs. i!lh'l'/Ollll('('l }lHlg th, llUlliiJt'l >t)f Illllh il)]('×or ]llplltS)

I h+" ,',,~,

Ae~dn. h sho~dd I,v
by
,ulJtr,,I part of a dosigii d u l h l ~ Ih,' s('hvdulin,_i pr,,e(,~s. f~l:,' _~pl. a tJf-ttel +l ;is foll.ws :

i'aldnl4 illlO iiCCOlliil 11(.~7 (oii~ll'~iilllS is illadt, possil)h. shnl)ly I~)' adding lheni h l l u llil, ci)sl [unelioll I>(.inl n~hlitiilzl!d (as it ~i!l I,( show in the ni!xi s,!cliOil).

3 3,1

Problem Defiifitions

Representation

Tile ()ptimization

and

Algorithm

%.V~lai'~'s('llt Imrq' 1]w o[fl imization alg~wilhm us(,d by the ~c]~,',lulh~g process. T h e reader nol [hnfiliar with 1he Ninnulated AnlwMing plo~ess can refer to [2()!. Fis~,m. 2 dt,scn'ib(.s s,h,'maficaHy the Simulaeed

A h;gh level synthesis a~orithm AiHl,,alhig algorlt hni. Parllcul;u'it~es of o)rl ~imulalod ann<,alhig algoril hnl are

(h n, tic Simulal¢,d ,\nn,':dillg ,\lg,)rilhnl 13~gin 5; : hfitinl Solution "I : lllitial l'~'mt),'ratltre ~'~:hill,(~l.tll)ltitl~,erit,,rloll is ilol salisfi,'d) do B('gin Wild. 01,~13<'* in (quiliLrium) d,) B~'gln ~;t)lll~ r;llldl)tII ti¢~igll~iOriltg 5f,l)lti,~ll of S ,11; := ,',)~t(S') - ,'.~1{5;) S' =

Proh :- Inin(l><'xp(-d[;f I )) il'r:~n4<,i]t(ll l) i Prod Ih,>tl S := S' Ih.i

273

area of tile architecture (the uumher of m o d u l ~ multiplied by their area) aud the total performance (the number of steps in the graph multiply by the delay of the operators). Weighting of the various parameters allows the optimization to be biased in a particular dlrPction of the design space (area or performance). • The schedule of the temperature, determined empirically, is a.~ follows : T~ T,=it × a k. Where the parameter a depends on the size of the problem and k is the number of moves performed from the heginning.

I I,,I.t,' I"

I'.nd (}l~il>,ll lit,st S<,l,di,,n S

Eu,I

It., ~ or, , rt, ~t' of Ill, 9' .'

re,

,s'tmuhd, d .In~, attn9 Alg,,rtthm

;,~ f.,lh,w~ : • Th(' ~).(hiteclnl'e ,ll/(Ior processin?~ is rel)r,?senh'd l)3' ;I ('oillrol [)al, i"l.w (;l'aph (('I)I:G) which is t h . initial ~,,].?i,m to the algorithm. The raNd.m neighb(,li))~4 sohll i.n is ohlnitu,(] by al)piymg ;t I';llhl(HII

IIIOV+ + { l r i l r l S f ( i l l l l l k l l O l l ) ' i l n

Iht. ciirl'ent

soINlion. *

t'l,,.>t, ll'dh~l])tlll311fHIq i'¢HIc¢'rn '
)he ~41'iillh. rl'h~,y ;ll'¢. : ]. Isolal(.(I

iI,~d~,~.

2. Ib'~lll.']l('~ willc]l alp se(lllell('t's o f sIICC¢'Sslve N,,,l.s siren Ih;it ,.acil no,lo is di~(,('lly ,hrpPndent Oll Ihv lU'evilm~ oily I).,l.mgin~ l o an adjacent slop (m:li'Ilhll'-,'3i I,' ), ;lnd h;is ill illost 011(!child in,el,. •

[lilll~I]ll'nlilliilliS

;~1'o t~[ hvo lyp(" :

I..Node or bt'<~i~,h lllow.s : A ,,~ildomly ~elected no,[(' (~r Iwan
inodillv i~ s,qetted ill tim (httaba~,: to illlph.nlenl ;ill ilpol-.3tlon (this nlodldl2 dllfers I'lTiln Ihe pl'l>cl'dill,t~ IJnl" by its porilorlllancl!, an,i~, elc..,). 'l'h(' diilaha~' eotlt,'liliS terhnolog3"hlili.l~i,iuh,lil di.~ci'lptlolis of operators.

• l']i(, c(isl tif it sl)llllilili iS ;l llleasiIr(' c+f its quality. I'ho ~<)si £11111"liliil it4 ;i weil~hted Stllil of the total

As indiC atcd in [20], the simulated annealing method is well stilled for this problem (the transformation from :t high lcw:l hehavioural description to a structural one) because of the very large amount of data when image processing algorithms are consktered {our system is mainly oriented towards this kited of applications) in one hand, and of complex engineering kiiowledge needed to explore the design space on the other hand (the stochastic search performs a good optimization withont coiuph,× rules or heuristics). 3.2

Definitions

D e f i n i t i o n 1 A .~cheduled graph is art acvclic, directed and multi,~ta9e graph where ~ach node is assiqned to a specific timv Mot. A C'ontrol Dora Flow Graph ( C D F G ) i.~ a scheduled graph+ The only representation of the architecture we have is a CDFG. Presently the graph has to be connected (if lhe graph is not connected, we consider each sub-graph independently). Definition boofi'on or m . n y hnk~ operation. ore vttlion.

2 Any itode o f the C:DFG repr~sertts a arithmetic operation. Such node has as a., the number of ope)'ands in the underb.iin 9 Tbe node tgl, e i~ identical to the one o f the

l)ul lug sNwduling, ea(h node is temporarily assigned to it 'q~ocilh" machine cycle or step (Figure 3). D e f i n i t i o n -3 .,In arc (or link) of the CDFG r~pl~'scnts an inletv~nnvelion network (bu~, rnult*plezors,...) allowi#g data transfers between different operators. The are length between two nodes ir~ the C D F G is defined as th~ nrtmber o f machine-cycles between these two lieder. D e f i n i t i o n 4 A m o t i f in the tjtrtph i.~ an item rep)', s('ntin 9 both the length of an are and il~ a.~ocialed two states (the soulve and the deMinntiou ~'apeetivcly)

274

F. Verdier et aL

Io a simple clock distribution. Examples in Figure 3 d e p i d the hnpact of increased regularity on (:oiH,rol complexity and on d a l a path part as well. The increase of )he interconnectivity {bus, registers, multiplexors) in the irregular e x a m p l e of Figure 3 (the less regular graph) leads to an increase of the conlrot complexii, y (more cantrol signals) and arieL1.. N,~tlce that : R e m a r k 1 .,Is mct~lio~cd in [I.~], the co11]igur~Ltion wit!, the lowv,~t 9lob(tl cost i,s not l~ece.~sarily the one wilh the m i n i m u m number of rt~islers. Thereforr, itl Ih~ .schcdu[in 9 process, measur2n 9 onl~l the ~t)tmbcr of i,r!ti.st~)w is irrrlevanl for ha.i*rrj a~ indication on em~h'.'d complc.dlg. .,I~M it seems d~S'jlculg, to sang the h a d . to hindu, lh~: . ~ m b c r of muttlph:rors prior to the bitMio,I process (l~efm'c the tls,slgnmcnl o f rt!tislers and apt ra/or*). li~3 R,,**,I.) It, fit ,:#d ,r,,q,d.,~ (rqtb U ,p,',,bs ~,etb Ib~. ,,.Vb ,., ,re, t,,,,, ,..,~ a~ ,.ramph ~. t-q!,,', ./on Iht ,',.quire' !pwpb). (tier dcd,~ !ruth mod~ I ;~ ,~ r, fli.*I, r-.~ ur-op~ vntm' rood, ! s~* , aeh m,,Qf .~ [lt .'t~ n ,l,Ha tra.
] Iw m,)*il, ale da~%ili,'d accord!n,., n, I}l,'il" t)pp arid vahu' [he type of a nlolif i- given by Iho u n . of llm ~ . l u n . and ,h,~fin;,li(m lll,¢h,s [or all ;tssoclillet} ;11"¢', ]IS ',illll{' i> l]]' ) (]iSlal],(.(,,t I,iI*~.! h irl l~,rrns ,,f 1]1,. IUlIll]nYr -i mm hh.' C,'¢h'-! l.,twv,,n lhe two n~,des. We will .s," ~he Miowin- m~l;iTioli : I.i.,, is ~h,' I,.ued~ .f d.' modf ;. whei-,, t. is ihe source 15 l)(' m)d t i I}),' ,l,,xllna@m lypm It) du, n,gnb, i e x a m p l e ,,I lh,' l-'J~rlt ," 3. lh(' h,n,zt I> of lhe ) ~.,-., m,)~ if.', >,hovo ira. /~.=I

L';

D e f i n i t i o n 5 ]1,,

I'h,. lm,lAem is to lind a way to quarzllfy the regularity of a sc}U,dlah,d graph, The solution we htwe selecled ¢'onslsls ()f deC~)lllposillg a grltph irllo a s::! motifs, alld to make a sial{st!ca] analysis of these motifs. l'llc ~ld'¢alllagps of stlch all approach are as follows : 1. :% mulif gives an indication about t h e number of rla[a J lalisfers belween two nodes - tlttlS between two ctn'/esponding operators (dal,a tr~/llSfer8 are the IIlost cosily in ternls of needed contm[ signals). 2. The use of stallstics inherently compresses data; W]lOltce easier llandIillg o1' a large a[llOUTit of characherlstics needed in these processes and coiIIptttatlon speed up.

r,9,h~riQ/ ~,.[ t~ *,h~d,!td 9rapb ~s

]11¢" g()lllplllil!i()[I lar,'r.

'JI till' n'gulatily ~xiI] by d,'>clib(xl

4

solutions

Proposed

l l e m a r k 2 Tb,: poh ,#ial rtgularibJ o f # scheduled !lmph Chl*t t~ds on lhe lopolO!l!l or nalurc o f the ahJoritkm to be *mphmce#~d. Tblzs the: r~!lularilg lhal can be ohio!ned mith ~ p.rli~,i¢lr 9roph i.~ hounded to some fized value.

H e u r i a t l c TI,~ t o o * . . , l u l n r a .~hrdultd flrald~. (in h rms ,~f it~ dzh~ hw,,.ft ~. ,~,,d tb~ .umb, ~ ¢~f opc ratiom~ i~ a 9,,'~ It mrI¢llillr-c~lr't~ ) t,% .impl~r its associalld co~trol !trl t r i m . ¢,] rt~rct. .~lmb, r of coutr,ol..itln#L ) (["i!tttr~. .7). One ,:an fimi an illus~ralion r,f this conjecture with *3"stollr al<:hil~?cl ql.t,s where Ihe conll'd parl is reduced

'l'hcso "'motifs" are being typed and any type is taken from a bounded set (ntunher of different operalions = f l so we haw- I 'a lyp(!s of motifs where the s[~llidatd d,'viallon has to be expressed..MOleOVer, the Iota[ number of arcs ill the graph is well known and coTis* till[ (it dal a I latlst(,r ll~'v('r appears or disappears dnning uh~ scheduling process) so it is possible to use classical statistical measures (such as llloarl arid standard d~:vlatlon) in order to e~Muate the graph legula~itv. For each type-set of motif, we compute a standard deviation of Ihe values of each motif th;tt indicates the global regularity of the graph. (X~.,,~ indicates the number of nodes of type G and hi. h'~,t,, indicates the length of motif i between a

A high level

stlllrco ilodo alld a destination node of types t., and td respectively) : • Mean of motifs length of type lst~ : v,,

E,=;

Pt'td

'

t,', ....

synthesis algorithm

275

One can note that there is another difference between the two graphs than regularity, the number of machine cycle is quite different. We will show in the next section another example giving the same kind of resnlts with two graphs with the same performance.

~Vt.Gt

,~' • a

~,ta =

?

5.1

lVt.t--

,

.* Gtobal diversity of the motifs (The graph rcgularity is the inverse of the dix~rsity) : D~c=

aljl~P~

~

Results

5

• Standard deviation of motifs length o1" type t,la :

ict,.jEz~ wlun'e P, and [~ are tile numbers of operators o[ type i and j . These weights (P, mid 1~) increase the nfinimization of tho di'.'evsity of data transfers between lhe more fi'equunl ly used operalions in the graph. The colnpul ation for the examples in Figure 3 gives :

Scheduling

Process

One can find here some results we have obtained when applying the method on the fifth order wave filter example. Starting with the same constraints concerning data path area and performance, we obtained two different solutions with the same number of operators and machine cycles but with different regularities; indeed, one of these solutions was found by a scheduling process taking into acceunt the regularity constraint while the other one was found without any regularity constraint. So. the scheduled graphs (Fig. 4) have the same basic characteristics : • Number of adders : 3, Number of multipliers : 2, Number of machine cycles : 16

• l'bu lhe regular gn'aph : - F:,r fin, motif~ or type + + :

{L~+, t ~ + , 1,3++ } -

While the respectives computed regularities are :

{i,l.i} ~/*++ =1, a++=O v o , tt ........ ,it:~,,r typ,, + × ; { t ~ , {1.1,1} ~ / * + x = 1, m~-x = 0

L~,

t~

} =

• ["or the other graph : Regularity = I]67.3

- For Ihe ,notlrsof type x + : {L~+.L~+, L'.'+} = {l,I,l} ~p×+ - 1, o'×+ = 0 {L~°~, Lt',,Lt~}

- Vo, tl....... titsof ty I. . . . . . {I,l,l}~it×~

• Fur the nlore regular : Regularity = 1/33

=

The CPU time required for the schedulht~ process was about 1 rain 50 sec. on a Sun SparcStation 2 with or without regularity computation.

=1, ax~-O

- Graph regularity : 5.2 Dn: - 0 ~

Binding Process

R e g = co

For this example, our target atructure for the contro 1 part of the architecture is a simple microprogrammed

• For tim irregular graph : - For the leugth set of motil~ of type + + : tt'++.L~+.L~+} = { 2 . ~ . t } ~,++ 1.66, er++ = 0.21 - "

Fo["thp lllO~ifs Of ly'pe + x : {/.~s, L~×, t~× } {2.1,1} ~ ! l l . --1.33, a+, = 0 . 2 3

- FoL'tile nloti[, ollYl)e -z+ : {Lr~+. LSx+, L~+} = {1.2.2} ~ / l : < , - 1.66, crx+ - 0 . 2 1 - Vo,..., {1.I.2}

.,,,,,il:. ~lt.,

or t y p e × ~ : {L~o . t " ~ . L ' ~ } = -

[.33.

ce~× -

[).23

- (;lapil I'egulallty :

I)iv = [5.{11

~ h'~g

(}.0(i6

["ig 4: The trrcynlar scbrlhded graph (on ~h¢ I~ft) and the regrllar one (right)

276

F, Verdict et al.

Reg,ularit~; Control part complcxi~,y Implantation Very high Few actions iterated Clock signals many times distribution high Iterated sequences of actions [ State counter low ~]aiiv various act ons ] Cl~sica[ __ ! implementation Very low Candiliona] branches (PLA or ~t-p.) FigS: Basso ~t~,ctnre of a microprogremmed controller controller as shown in Fig,,re 5. The c o h m n s in the instruction memory represent contru[ signals for each modtde in the data path (adders and multipliers if needed, r{%isters, multiplexors) while each line represents a machine cycle. The estimation of the control complexity (control cost) is nothing but the instruction memory area (total tmmher of hits in the memory). We choose this control structure because of its simplicity since the ~cope of this paper is not to implement the actual control part synthesis but to take into account control conslraints during the data-path synthesis. Including control structures such as hranchilig and ~equenee breaks do ,,oi alter tile method since in lids case only the mmlber of motifs is modified. ~\-e present here the results after binding tile two graphs. These results were obtained by applying Ihe binding process several time, the wdues reported are merages conlpuled from 20 executions.

i L_regular I irrcg,d;t_r [gain

control area #mux inputs #registers [ time 728 I 43.2 !9 I 4l~ec 934 51.8 11 455 ~c 22~ [ 16.6'h [ 18% ] 10%

It is clear that taldng into account the regularity of the data-flow graph during scheduling Mlows thc binding process to com~,Ne toward a better solution (in term of number of multiplexor inputs, number of register5 and control areal.

6

Conclusion and Perspectives

The relevance of our proposed method is anticipation : Indeed. with this method, the impact of scheduling on c,mtro] part synthesis is taken into account even befine ihe binding process for data path synthesis is perfi,rmed. T]ds anticipation h~s heen made possible through lhe ,is(, of stmistics lhat lll{'aSllI'e the global characteristics ot ro,:.,,larity I;r~t ;, schvd,,h.d graph, i.,:., the CI)FG.

Fig.5: L:zample of translatlo~z between regld~rity and control nnpleme;Oalio~t models.

On a realistic enough exantple such as the fifth order wave digital filter, we have obtained a significant difference between the regularity of the two scheduled graphs (for exactly the same number of operators : 3 adde,s, 2 multipliers) and a decrease of 2;2 per cent of the control part area. Therefore, we have shown that at this level of ~ynthesls (the scheduling phase}, we can not neglect bhls regularity measnre. The loss of "distinguishability" due to the use of statistics presents no drawbacks, since at this level of the synthesis only global characteristics a ~ needed. In fact, handling more precise information related to control complexity (for instance doing the binding and the scheduling process sinmltaneonsly) woub[ he tedious and would not improve design quality. This is especially true when one thhtks of the other issues such as partitioning, optimal number of clock phases, multicyclit~g and chaining of operators, ere . . . n o t to mentiol, testability, fault tolerance and correctness (formal methods, s i m u l a t i o n , . . . ). Our goal is not to design the control part while I)erforming the data path part, but to try to subject the data path to tim control constraints. In doing s,., we think we have found a way for a better solution to the actual design of the control part. One possible ':xtension of this proposed method is to facilitate tbe selection of a control implementation model (see Figure 6) based on regularity characteristics determi.ed from the w~ry beginning (i.e. the scheduled graph or CDFG). These rules may define the controller type, and thTs can be done before the run of algorithm II (binding process and floorplanning) for data path synthesis. Other clues indicated in [9J about the performance and testability of many ditl~renl controller implementations can be added. We have re,rod a way, in addition to avoid sim,lllaneously performing the I)inding proccs.~ with s:h,:,hdlng, by adding a "regularity measure" to the cost fllllCtlon, t o obtain a schednhM graph ~tN good as the o n e w e w o u l d have obtained while performing sirnll]lallellusly thl" hillding pl'~)ci'~:~and the scheduling.

A high level synthesisa~orithm We achieved a better understanding of what improves a given scheduled graph in terms of control complexity arid how the binding process affects scheduling. In sum, the added term of regularity measure minimizes tile control complexity (through data transfer dispersion) ,~ much as the binding process does, but with far less computational complexity. References [1] C. Bieh[, W. Grass, anti S. Hall. Optimization of lhe influence of problem modifications on given microprogrammcd controllers. In Proc. of the lTlh Design Aulonlatzon Conference, pages 309 :IlL 1!180. [2] I"orrest Bi'e',,~or and Daniel G~jski. Chippe: A ~ystcm fi~r co,)~lrainl driven behavioral synthesis. In IEEE trans, oJz CAD, vohtme CAD-9 No 7, pages 681-695, 1990, [3] R. Camposano. Structural synthesis in the yorktown silicon compiler. In Proceedings o, 1/LS1'87, Vancouver. 1987. [t] R. Camposano and J.T..I. Eijndlloven. Combined ~ynthesis of control h)gh: and data path. In Proc. oflEEE I('CAD, pages 327 329, 19S7. [5] S. Davidson, Landskov D., Bruce D. Shriver, and Mallett Patrick W. Some experiments in total nficrncode compaction tbr horizontal machines. In IEEE tran.~, on Comyu:eJ.v, vohtme C-3O No 7, pages 460 .177. 198l. [6] E.F. C,h'czyc and .l.P. Knight. An ads to standard coil ]tm'(hvare cotnpiler based on graph grammars ;rod scheduling. In P~v~c. of ICCD. pages 726 731. 198I. [7] C,. (?,oosse]ls. D. Lamieer, d. Vanhoof, J. Rabaey, .I. Van Mcerbergen, and 11. De Malt. Opthnisationhas~,d synthesis of multiprocessor drips for digital signal processing, with cathedral 2. In Proc. ol" lb~ l,drrn.tlomd ll'orbshop on Lagic and :lrchih:etur~ Synthesis for Silicon Compiler,~. G,~nobh,. FRANCI?. 1988.

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278

K Verdict et aL

[21] P. \hrinol. ('ompitaliol~ de silicium : Applic~dio~ 6 Ic~ compih~lio, dr. pottle col~Ir3h. PhD thesis, Insliltlt Nalional Polylechnique tie Grenoble, N'a nee. I987.