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A low-power low-offset dynamic comparator for analog to digital converters
Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
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A low-power low-offset dynamic comparator for analog to digital converters Mohsen Hassanpourghadi n, Milad Zamani, Mohammad Sharifkhani Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran
art ic l e i nf o
a b s t r a c t
Article history: Received 24 April 2013 Received in revised form 25 November 2013 Accepted 26 November 2013
A comparator comprises a cross coupled circuit which produces a positive feedback. In conventional comparators, the mismatch between the cross coupled circuits determines the trade-off between the speed, offset and the power consumption of the comparator. A new low-offset low-power dynamic comparator for analog-to-digital converters is introduced. The comparator benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch effect inside the positive feedback circuit. Rigorous statistical analysis yields the input referred offset voltage and the delay of the comparator based on the circuit random parameters. The derivations are verified with exhaustive MonteCarlo simulations at various corner cases of the process. A comparison between typical comparator and the proposed comparator in 180 nm and 90 nm has been made. The power consumption of the proposed comparator is about 44% of the conventional and its offset voltage is at least one-third of other mentioned conventional comparators. & 2013 Elsevier Ltd. All rights reserved.
Keywords: Comparator Low-offset Low-power Analog to digital Converters
1. Introduction The growth in portable battery operated communication devices increases the demand for low power and high speed ADC. Generally, moving toward the smaller feature size allows for the reduction in the power consumption and higher speed. However, the process variation and mismatch increases at finer processes and limits the performance of the ADCs. One of the critical parts of an ADC greatly influenced by the process variation and mismatch is the comparator [1]. In some ADCs, the offset voltage can be tolerated to some extent, thanks to the digital error correction (DEC) and over-range protection [2,3]. However, the INL and DNL characteristics of the ADC are still influenced by the comparators offset even in the DEC enabled ADCs. The characteristics of a comparator are defined by its input referred offset voltage for a given power dissipation, speed and the area [2]. Scaling CMOS technology shrinks the headroom voltage and the full scale range of input voltage. Therefore, the protection range of the offset voltage decreases. Moreover, CMOS device mismatch nearly doubles for every process generation below 100 nm. This effect gives a major thrust in recent comparator designs [4]. Hence, the design of a high performance comparator is one of the key challenges in an ADC design.
n
Corresponding author. E-mail addresses: [email protected] (M. Hassanpourghadi), [email protected] (M. Zamani), [email protected] (M. Sharifkhani).
In comparators, a lower offset comes at the expense of larger transistors hence higher power consumption and reduction in speed. In addition, the conventional comparators are complex to design and there are only few design methodologies to control the offset. To reduce the power consumption and the area of comparators, dynamic comparators are proposed [5]. However, such comparators usually suffer from relatively large offset voltage than static comparators [6,7]. Some architectures have been proposed for dynamic comparators in the literatures. The dynamic comparators are categorized into three groups: Resistor divider [5], Differential pair and Capacitive–differential pair dynamic comparator [2]. Other structures are mainly derived from these architectures [8–12]. A typical single phase comparator is shown in Fig. 1 that was introduced in [5] to show the trade-offs between the offset and the speed and power. The structure is called “Lewis–Gray” comparator, and is widely used in ADC architectures [9]. Hence, it is taken as the reference conventional comparator in this paper. The core of this comparator is the same among all single phase comparators comprising a preamplifier stage and a cross couple latch. The two stages operate asynchronously and simultaneously when the comparator enters the evaluation phase. Therefore, in the ideal case where the cross-coupled latch does not have a mismatch, it operates only when the preamplifier induced a sufficiently large differential voltage at the internal nodes of the latch. Practically, the offset due to the mismatch of the cross-coupled latch kicks in as soon as the entire amplifier begins to operate. Recently, an analysis was made to estimate the input referred offset voltage of the conventional comparator [13]. It was shown
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Please cite this article as: M. Hassanpourghadi, et al., A low-power low-offset dynamic comparator for analog to digital converters, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.11.012i
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2
VDD
VDD
Vref+
Vref-
Preamp
Vlatch M9
M10
M11
M12
Vlatch
M7
CL
CL
Vref-
M1
M2
M3
M8 M4
M6
Vout+
M6 Vin+ Vin-
M11
M5
Iin+ 1
Preamp
M3
M8
M5
2
M7
Vin+
Vout+ Vout-
1
Latch
M9
CL
1
Vin-
I in-
VoutCL
M1
M10
M2
1
Latch
M4
Fig. 2. Proposed comparator.
Vref+
Preamplifier
Pre-discharge
how the comparator input referred offset can be reduced at the expense of a high power dissipation. That is because, at the comparison phase the regeneration process in the cross coupled pairs and the amplification of the input voltage occur simultaneously. Hence, the amplification by the input transistors must be fast and large enough to fight against the offset of the cross coupled pairs. A large and fast amplification leads to a higher power consumption. It was concluded that the mismatch between M7 and M8 alone can lead to 0.3 V offset voltage in 45 nm technology [13]. Moreover, the comparator itself has high sensitivity to the output capacitor mismatch [9]. The positive feedback at the output increases the effect of the capacitor mismatch on the overall input referred offset which again demands a more powerful input stage. In order to break the deadlock between the offset and the power consumption, a new architecture is proposed. The double phase architecture takes the advantage of a cascade of amplifying stage and a usual latch stage. More importantly, it involves a significantly smaller input offset voltage without a significant power and area penalty. The rest of this paper is organized as follows: In Section 2 the new comparator architecture is presented along with the analysis of its offset voltage. In Section 3 the simulation results are presented while Section 4 concludes the paper.
2. Proposed comparator 2.1. Circuit architecture The proposed comparator is shown in Fig. 2. The latch circuit is separated from the amplification branches. Each stage operates independently with different clock pulses, ϕ1 and ϕ2. This separation helps the input transistors to overcome the mismatch effect inside the latch circuit before the offset of the latch circuitry is involved in the overall decision making process. Hence, it significantly reduces the input referred offset voltage of the comparator. Moreover, the comparison of the differential input voltage with the differential reference voltage takes effect at the gate source of the input transistors, M3 and M4, leading to fewer transistor count regarding to conventional architecture and therefore lesser offset from mismatch between these transistors. The proposed comparator works with a special three phase signaling. The signal waveform of the comparator is illustrated in Fig. 3. At the first phase or pre-charging phase both ϕ1 and ϕ2 are high. Therefore, the cross coupled inverter pairs are off and
Comparison
tamp
1
Fig. 1. Conventional fully differential dynamic comparator [5].
Amplification
2 Ttotal Vout+ Vout-
Vout time Fig. 3. Conceptual waveforms.
pre-charge transistors discharge the output nodes to the ground. The second phase or the amplification phase will occur when ϕ1 is low and ϕ2 is still high. Consequently, the path to the ground is cut while the reference voltages can feed the input branch and let the input cascade transistors conduct. The difference between the amount of the current produced in the input branches, I in þ I in , is related to the voltage difference between the input and the reference differential voltage. During the amplification phase, the currents set the differential voltage at the internal nodes of the cross-couple latch, V out þ and V out . In the third phase, the comparison phase, the latch circuit operates and the induced differential voltage is boosted in the regenerative loop of the cross-coupled inverters. 2.2. Analysis 2.2.1. Decision point A simple analysis shows that the comparator compares the voltage difference between the input differential voltage with the reference differential voltage, VREFDIFF. At the beginning of the amplification phase, the output nodes are discharged to the ground (V out þ ¼ 0; V out ¼ 0). The amplification phase starts with the activation of ϕ1. Transistors M8 and M7 operate as a small resistor at the source of the input transistors M3 and M4. Since, the voltage level at the inputs of the comparator at the decision point is more than zero, the drain–source voltage of the input transistors is more than their gate–source voltage. Hence, M3 and M4 operate in saturation
Please cite this article as: M. Hassanpourghadi, et al., A low-power low-offset dynamic comparator for analog to digital converters, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.11.012i
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equation:
region and the following equation holds: 2
I in þ ¼ kp3 ðV in þ V ref þ V thp3 Þ ; I in ¼ kp4 ðV in V ref V thp4 Þ2
ð1Þ
where kpi ¼ 12μp cox ðW=LÞi . These currents charge the output capacitors, so the output voltages rise linearly over time. Let CL be the load capacitor and tamp be the duration of the amplification phase. The initial voltage of the output nodes at the start of the third phase is V out þ 0 ¼ I in þ t amp =C L ; V out 0 ¼ I in t amp =C L :
2.2.2. Static offset By definition, the input referred offset voltage VOS of the comparator equals to the differential input voltage that establishes the condition V out þ ¼ V out at the end of the third phase. First, let us assume that the initial voltages at the internal nodes V out þ and V out at the start of the third phase (Eq. (2)) are less than V thn1;2 (threshold voltage of M1, M2). This condition occurs in the operation of the comparator for typical values of amplification time. We can also assume that the effective voltage of the input transistors, M1 and M2, is too small in comparison with the effective voltage of M5 and M6 when the cross-coupled inverters are activated in the third phase. Therefore, the effective current that charges the internal nodes of the inverters is provided through M5 and M6. Hence, CL
ð3Þ
The node which reaches V thn1;2 sooner makes a logic 1 and the other node creates a logic 0. Essentially, in the balanced state, both nodes charge to V thn1;2 at the same time. In that case, integrating over (3) yields Z V thn1 ðI in þ kp5 ðV out þ V DD V thp5 Þ2 Þ dV out þ V out þ 0
Z
¼
V thn2 V out 0
ðI in þ þ kp6 ðV out V DD V thp6 Þ2 Þ dV out
ð4Þ
In order to derive a closed form solution for the offset of the capacitor, it is instructive to analyze the behavior of the comparator in the balanced state where ΔV in ¼ ΔV os . The mismatch between the devices can be modeled using the following equations: I in þ ¼ I in þ ΔI in ; V in þ ¼ V in þ ΔV in ; kp5 ¼ kp6 þ Δkp5;6 ;
V thp5 ¼ V thp6 þ ΔV thp5;6 ; V thp3 ¼ V thp4 þ ΔV thpin ;
kp3 ¼ kp4 þ Δkpin ;
V thn2 ¼ V thn1 þ ΔV thn1;2
ð5Þ
and V thn1;2 is the threshold voltage of M1 where kp is μ and M2. On the other hand, ΔI in is related to Vin with the following 1 2 p cox ðW=LÞ
ΔIin ¼ ΔV in 2kpin ðV in V DD V thpin Þ ¼ ΔV in gmin
ð6Þ
Substituting (5) into (4) leads to extensive, yet straightforward derivations that is beyond the length of this paper. After simplification the overall comparator offset variance is s2V OS ¼ s2V thpin þ s2kpin K 2kpin þ s2V thn1;2 K 2V thn1;2 þ s2V thp5;6 K 2V thp5;6 þ s2kp5;6 :K 2kp5;6
ð2Þ
The sign of V out þ 0 V out 0 determines which way the comparator swings once the comparator enters the third phase, given the internal latch does not incur an offset of its own. Each of these two voltages is proportional to the amount of the input currents. The currents are controlled by V in þ V ref þ and V in V ref . Obviously, the trip point can be set by making a difference between the two reference voltages. In this work, the body of the input transistors is connected to the source terminal to avoid body effect, hence, V thp3 ¼ V thp4 . Therefore, the reference voltage is V REFDIFF ¼ V ref þ V ref .
dV out þ ¼ I in þ þkp6 ðV out V DD V thp6 Þ2 ; dt dV out ¼ I in þkp5 ðV out þ V DD V thp5 Þ2 : CL dt
3
ð7Þ
where K kpin ¼
ðV in V thpin V ref Þ2 ; gmin
¼
K V th
inv
K V thp5;6
I 5;6 ðV thinv Þ ; t amp I t amp I 5;6 in gmin V thinv þ C C
I t amp I 5;6 ðV thinv Þ I 5;6 in C ; ¼ t amp I t amp I 5;6 in gmin V thinv þ C C
K kp5;6
3 I in :t amp V DD V thp5;6 ðV thinv V DD V thp5;6 Þ3 C ; ¼ t amp I t amp I 5;6 in 3gmin V thinv þ C C
I 5;6 ðV Þ ¼ kp5;6 ðV V DD V thp5;6 Þ2 ; I in ¼ kpin ðV in V DD V ref Þ2
ð8Þ
A longer amplification time, tamp, or a larger differential current I in þ and I in reduces VOS because this increases V out þ 0 V out 0 at the beginning of the third phase. If each of these values reaches V thn1;2 , the amount of VOS is only influenced by the input transistors mismatch.
2.2.3. Delay The delay is defined as the time between the start of the amplification phase and the time where 50% of the latch final output is reached. Based on this definition, the inner latch delay can be calculated from derivations presented in [14]. For each inner latch short channel transistor a piecewise linear relation between the current and VGS that is equal to GM is derived. If the differential input of the latch is ΔV in the propagation delay is obtained from T total ¼ τinv lnð0:5ðV DD GNDÞ=ΔV in Þ in which τinv ¼ C L =ðGMPMOS þ GMNMOS Þ. CL is the load capacitance at each output node and GMPMOS and GMNMOS are GM of inner inverters linear transconductance. Depending on the length of tamp, three different scenarios take place with regards to the initial condition of the inner latch before it enters the third phase. This condition influence the equation that governs the delay of the third phase. The first scenario occurs when at the end of the amplification phase, M1 and M2 remain completely off. The second scenario takes place when either one of M1 or M2 is turned on at the end of the amplification phase, yet the differential voltage is small and the output is determined in comparison phase. And in the last scenario, M1 and M2 are both on, and the output is determined at the end of the third phase. If mean of input currents is Iin and τ1;2 ¼ C L =GM1;2 . Therefore the
Please cite this article as: M. Hassanpourghadi, et al., A low-power low-offset dynamic comparator for analog to digital converters, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.11.012i
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delay can be obtained from
0 1 8 > > > B 0:5V DD C > > B C > > > t amp þ τinv ln@ΔI in t amp A > > > > > CL > > 0 1 > > > > > > B C > 0:5V DD > C > t amp þ τinv lnB > @ΔI V A < in th1;2 ðt amp ðC L V th1;2 Þ=I in =τ 1;2 Þ e T total ¼ I in > > > > > > > > > > > 0 1 > > > > > > B > C V 0:5V DD C > L th1;2 þ τ lnB C > > 1;2 @ΔI V A > > I in in th1;2 > > : I in
t amp o
C L V th1;2 I in
C L V th1;2 o t amp o T total3 I in T total3 o t amp
ð9Þ where Ttotal3 is equal to last subfunction of Eq. (9). The equation indicates that the propagation delay is nonlinear to tamp and the sensitivity to the length of the amplification phase degrades when tamp increases. 2.2.4. Kickback noise In the CMOS latched comparators the output voltage variation which is coupled to the input transistors can spoil the input voltage. This effect, which is called kickback noise, should be reduced to gain a higher precision. Fig. 4 illustrates the peak disturbance over the input voltage for different input voltages at 100 MHz clock frequency. The comparator's input is modeled by Thevenin equivalent with a resistor equal to 8 kΩ. The proposed comparator suffers from a large kickback noise, since its structure is similar to the Class-AB comparators. Moreover, as concluded in [15], faster output settling in dynamic comparators brings about a larger disturbance at the input nodes. Consequently, kickback
Peak Input Voltage Error (mv)
103
Proposed dynamic comparator Proposed dynamic comparator with neutralization
102
noise is inevitable in the high speed comparators. Some kickback noise reduction techniques like neutralization suggested in [15] can significantly reduce this effect. The proposed comparator simulated under neutralization technique, and the results are shown in Fig. 4. The reference nodes are usually low impedance, thus, voltage disturbances are smaller on the reference voltages compared to the inputs. Moreover, the main disturbance occurs at the start of the amplification phase, which provides the reference voltages a time to settle to their normal level before the beginning of the comparison phase. In other words, the reference voltage buffers correct their error during the time of tamp. The low power source follower buffers introduced in [16] fulfill the low impedance required for such voltage settling.
3. Simulation results and comparison Fig. 5 demonstrates the layout of the proposed comparator and the output buffer in 0:18 μm technology. The load capacitance due to the output latch is about C L ¼ 10 fF. The comparator takes the area of 180 μm2 while the output latch needs 100 μm2 . The transistor sizing is reported in Table 1. The proposed comparator is simulated in 180 nm and 90 nm CMOS technologies to verify its operation and the consistency with the analytical derivations. Fig. 6 shows the response of the comparator to a 1 mV differential signal for two cases of t amp ¼ 0 s and t amp ¼ 500 ps. It is observed that the amplification time of 500 ps creates a delay overhead about 131 ps at the output. Overdrive recovery test is conducted to investigate the memory effect of the comparator. It was observed that the comparator can successfully detect a 1 mV after a comparison of 1 V. Based on the baseline MC simulations, Fig. 7 combines a number of comparisons between the proposed and conventional comparators in terms of the trade-off between the VOS and the average dynamic power consumption. The power consumption of three sources, including VDD, V ref þ and V ref , are considered as overall
101
Table 1 Transistor sizing for proposed comparator shown in Fig. 2.
100
10-1
10
-1
10
0
10
1
10
2
Input Voltage (mv)
10
3
MOSFET
Size
M1, M2 M5, M6 M11 M3, M4 M7, M8
0:22 μm=0:18 μm 0:66 μm=0:18 μm 0:22 μm=0:18 μm 4:5 μm=0:36 μm 4 μm=0:18 μm
Fig. 4. Peak input voltage error due to kickback noise.
Fig. 5. Layout of proposed comparator and the output latch.
Please cite this article as: M. Hassanpourghadi, et al., A low-power low-offset dynamic comparator for analog to digital converters, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.11.012i
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5
associated with the transistor pair mismatch. As the frequency raises, tamp decreases in proportion to the overall evaluation time. Therefore, the dependency of the overall offset to the offset associated with the latch increases. Therefore, the amount of VOS is increased. To overcome the effect of the internal latch offset, larger latch transistors must be used at the expense of more power. For a given sizing, the effect of the length of the amplification time, tamp, on the overall offset voltage is shown in Fig. 8. The figure includes both analytical derivations presented in (7) and Monte-Carlo simulation results. In the simulation curve, each
power consumption in the proposed architecture. All comparisons are made in two different technologies of 90 nm and 180 nm CMOS and for three sampling frequencies of 40 MHz, 100 MHz and 1 GHz. In each graph, a target frequency is considered for the design and simulation of the comparators. In each curve, each point represents the offset of a conventional or proposed comparator with different sizing that offer a target offset. In each point, the offset is derived based on the 3s of the histogram of the offsets with 1k sampled Monte-Carlo simulation for the given sizing in that point. Interesting results can be inferred from the simulations. For the same power consumption, the proposed comparator offers about an order of magnitude smaller offset voltage compared to the conventional comparator. In lower frequencies where a large tamp is possible, the offset voltage can be as small as the offset
50
T
Calculated Vos Simulated Vos
= 0.585ns
45 2
40
Vout (v)
1.5 1
Vos (mv)
0.5 ns
131 ps
T
35 30
T
25
0.5
= 0.683ns
= 0.779ns = 0.874ns T = 0.965ns T = 1.06ns T = 1.13ns T = 1.2ns T
T
20 15
0
= 1.21ns
T
= 1.21ns
10 0
-0.5 0
0.5
1
1.5
2
2.5
200
400
600
1000 1200 1400 1600 1800 2000 tamp (ps)
Time (ns)
Fig. 8. Trade-off between amplification time and offset. Simulated and calculated VOS as a function of tamp, printed data represent propagation delay (ns) (each point calculated with 1k Monte-Carlo simulation).
Fig. 6. The step response of proposed comparator to ΔV in ¼ 1 mV for t amp ¼ 0 s and t amp ¼ 500 ps in 180 nm technology.
90nm technology
180nm technology
300
200 Proposed Conventional
150 40MHz Vos(mv)
800
3
200 100 100 50 0
0
5
10
15
20
25
250
0
10
20
30
40
200
200 100MHz Vos(mv)
0
150
150 f 100 100 50
50 0
0
10
20
30
40
250
0 10
20
30
40
50
60
50
100
150
200
250
300
1GHz Vos(mv)
200 200
150 100
100
50 0
0
100
200 Power(µw)
300
400
0
0
Power(µw)
Fig. 7. A comparison between the conventional and proposed comparator in 180 nm and 90 nm CMOS technologies (each point represents the offset associated with 1k Monte-Carlo Baseline simulation on a differently sized comparator for a targeted offset).
Please cite this article as: M. Hassanpourghadi, et al., A low-power low-offset dynamic comparator for analog to digital converters, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.11.012i
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80 VOS (mv)
60 40 20 0 0.5
0.6
0.7
0.8
0.9
1
1.1
VCM (v)
Fig. 9. Offset voltage vs common mode voltage.
Power (µW)
40 30 20
frequency at supply voltage of 1 V and the capacitive load of 10 fF. The dynamic offset, VOS, is estimated, by adding an intentional 1 fF capacitive load mismatch at the output for all comparators in addition to the stochastic mismatch of the transistors. The comparators are designed such that they achieve similar delay at ΔV in ¼ 1 mV. The results are reported in Table 2. The tamp in the proposed comparator was set to 20 ps. The offset voltage of the proposed comparator is at least three times smaller than two other dynamic comparators. Moreover, the power consumption of the proposed comparator is about 44% of the conventional and 85% of the differential pair structure. The power consumption of proposed comparator is considered to be equal to power consumption in three sources: VDD, V ref þ and V ref . The area of the comparators is estimated based on the size of the transistors and the number of nodes for a given comparator. It must be noted that shortcircuit power dominates the dynamic power, therefore power consumption is not completely related to area consumption.
10 0 0.5
0.6
0.7
0.8
0.9
1
1.1
4. Conclusion
VCM (v)
Fig. 10. Power consumption vs common mode voltage.
Table 2 A comparison between comparators. Comparators
V OS ð3sOS Þ (mV)
Power ðμWÞ
Delay (ps)
Area ðμm2 Þ
Dynamic VOS (mV)
Resistor divider [5] Differential pair [2] Double-tail comparator [17] Proposed
192 102 23.4
116 60 82
170 550 130
1.55 3.84 3.5
Very large 55–65.1 20.1–24.1
33
51
152
3.3
15.1–17.9
The previously reported comparators are sized to achieve nearly the same delay in the simulations in 90 nm CMOS technology.
point represents a set of 1k samples Monte-Carlo Baseline simulations in 180 nm CMOS technology at the sampling frequency of 100 MHz. The VOS derived from the calculations is less than simulated by a mere 5 mV. The difference is due to the dynamic offset and the mismatch caused by kp5;6 and kpin. Interesting results can be concluded from Fig. 8. For a given size of the devices a trade-off exists between the total delay and comparator offset. As expected from the derivations presented in Eqs. (7) and (8), large enough amplification time offers an effective mismatch cancelation of the inner latch transistors. In that case, the offset voltage is only affected by the mismatch of the input transistors. In this simulation, the input referred offset voltage caused by the input transistors is 14 mV. The comparator offset reaches to this value when tamp is about 1 ns. The figure also suggests that for large enough amplification times (e.g., t amp 4 600 ps) the offset voltage has minor sensitivity to the tamp. It suggests that a relaxed timing circuitry (e.g., an inverter chain with determined minimum delay) can be used for the generation of the clock signals. Fig. 9 illustrates the sensitivity of the input referred offset to input common mode voltage (VCM) and Fig. 10 depicts the power consumption. Decreasing the amount of VCM increases Iin, and magnifies K kpin . Consequently, the input referred offset increases. On the other hand, increasing common mode voltages, decreases the current consumption in the pre-amp section (Iin), which brings about more sensitivity to the inner latch mismatch which highly augments the offset. To draw a comparison, the proposed and two other comparators were simulated in 90 nm CMOS technology at 1 GHz sampling
A new low power and low offset dynamic comparator was proposed. The structure benefits from two phase signaling to cancel the mismatch of the inner devices. The offset voltage was obtained using analytical derivations as a function of mismatch and delay. The derivations were verified with high precision exhaustive Monte-Carlo simulations. The propagation delay of the comparator was calculated and the trade-offs between the speed and offset were explained. The comparator was simulated in CMOS 180 nm and 90 nm technologies and a good agreement between simulation and equations was obtained. At 1 GHz clock frequency, the power consumption of the proposed comparator is reduced to 44% of the conventional comparator power consumption while the offset is 33 mV that is at least three times smaller than offset voltage of the conventional comparators.
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M. Hassanpourghadi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ [11] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, A 10-bit charge-redistribution adc consuming 1.9 w at 1 ms/s, IEEE J. Solid-State Circuits 45 (5) (2010) 1007–1015, http://dx.doi.org/10.1109/JSSC.2010.2043893. [12] M. Chahardori, M. Sharifkhani, S. Sadughi, A 4-bit, 1.6 gs/s low power flash adc, based on offset calibration and segmentation, IEEE Trans. Circuits Syst. I: Reg. Pap. 60 (9) (2013) 2285–2297, http://dx.doi.org/10.1109/TCSI.2013.2246206. [13] J. He, S. Zhan, D. Chen, R. Geiger, Analyses of static and dynamic random offset voltages in dynamic comparators, IEEE Trans. Circuits Syst. I: Reg. Pap. 56 (5) (2009) 911–919, http://dx.doi.org/10.1109/TCSI.2009.2015207. [14] A. Nikoozadeh, B. Murmann, An analysis of latch comparator offset due to load capacitor mismatch, IEEE Trans. Circuits Syst. II: Express Briefs 53 (12) (2006) 1398–1402, http://dx.doi.org/10.1109/TCSII.2006.883204.
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[15] P. Figueiredo, J. Vital, Kickback noise reduction techniques for cmos latched comparators, IEEE Trans. Circuits Syst. II: Express Briefs 53 (7) (2006) 541–545, http://dx.doi.org/10.1109/TCSII.2006.875308. [16] Z. Cao, S. Yan, Y. Li, A 32 mw 1.25 gs/s 6b 2b/step sar adc in 0:13 μm cmos, IEEE J. Solid-State Circuits 44 (3) (2009) 862–873, http://dx.doi.org/10.1109/ JSSC.2008.2012329. [17] S. Babayan-Mashhadi, R. Lotfi, Analysis and design of a low-voltage low-power double-tail comparator, 2013. http://dx.doi.org/10.1109/TVLSI.2013.2241799.
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A low-power low-offset dynamic comparator for analog to digital converters Mohsen Hassanpourghadi n, Milad Zamani, Mohammad Sharifkhani Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran
art ic l e i nf o
a b s t r a c t
Article history: Received 24 April 2013 Received in revised form 25 November 2013 Accepted 26 November 2013
A comparator comprises a cross coupled circuit which produces a positive feedback. In conventional comparators, the mismatch between the cross coupled circuits determines the trade-off between the speed, offset and the power consumption of the comparator. A new low-offset low-power dynamic comparator for analog-to-digital converters is introduced. The comparator benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch effect inside the positive feedback circuit. Rigorous statistical analysis yields the input referred offset voltage and the delay of the comparator based on the circuit random parameters. The derivations are verified with exhaustive MonteCarlo simulations at various corner cases of the process. A comparison between typical comparator and the proposed comparator in 180 nm and 90 nm has been made. The power consumption of the proposed comparator is about 44% of the conventional and its offset voltage is at least one-third of other mentioned conventional comparators. & 2013 Elsevier Ltd. All rights reserved.
Keywords: Comparator Low-offset Low-power Analog to digital Converters
1. Introduction The growth in portable battery operated communication devices increases the demand for low power and high speed ADC. Generally, moving toward the smaller feature size allows for the reduction in the power consumption and higher speed. However, the process variation and mismatch increases at finer processes and limits the performance of the ADCs. One of the critical parts of an ADC greatly influenced by the process variation and mismatch is the comparator [1]. In some ADCs, the offset voltage can be tolerated to some extent, thanks to the digital error correction (DEC) and over-range protection [2,3]. However, the INL and DNL characteristics of the ADC are still influenced by the comparators offset even in the DEC enabled ADCs. The characteristics of a comparator are defined by its input referred offset voltage for a given power dissipation, speed and the area [2]. Scaling CMOS technology shrinks the headroom voltage and the full scale range of input voltage. Therefore, the protection range of the offset voltage decreases. Moreover, CMOS device mismatch nearly doubles for every process generation below 100 nm. This effect gives a major thrust in recent comparator designs [4]. Hence, the design of a high performance comparator is one of the key challenges in an ADC design.
n
Corresponding author. E-mail addresses: [email protected] (M. Hassanpourghadi), [email protected] (M. Zamani), [email protected] (M. Sharifkhani).
In comparators, a lower offset comes at the expense of larger transistors hence higher power consumption and reduction in speed. In addition, the conventional comparators are complex to design and there are only few design methodologies to control the offset. To reduce the power consumption and the area of comparators, dynamic comparators are proposed [5]. However, such comparators usually suffer from relatively large offset voltage than static comparators [6,7]. Some architectures have been proposed for dynamic comparators in the literatures. The dynamic comparators are categorized into three groups: Resistor divider [5], Differential pair and Capacitive–differential pair dynamic comparator [2]. Other structures are mainly derived from these architectures [8–12]. A typical single phase comparator is shown in Fig. 1 that was introduced in [5] to show the trade-offs between the offset and the speed and power. The structure is called “Lewis–Gray” comparator, and is widely used in ADC architectures [9]. Hence, it is taken as the reference conventional comparator in this paper. The core of this comparator is the same among all single phase comparators comprising a preamplifier stage and a cross couple latch. The two stages operate asynchronously and simultaneously when the comparator enters the evaluation phase. Therefore, in the ideal case where the cross-coupled latch does not have a mismatch, it operates only when the preamplifier induced a sufficiently large differential voltage at the internal nodes of the latch. Practically, the offset due to the mismatch of the cross-coupled latch kicks in as soon as the entire amplifier begins to operate. Recently, an analysis was made to estimate the input referred offset voltage of the conventional comparator [13]. It was shown
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2
VDD
VDD
Vref+
Vref-
Preamp
Vlatch M9
M10
M11
M12
Vlatch
M7
CL
CL
Vref-
M1
M2
M3
M8 M4
M6
Vout+
M6 Vin+ Vin-
M11
M5
Iin+ 1
Preamp
M3
M8
M5
2
M7
Vin+
Vout+ Vout-
1
Latch
M9
CL
1
Vin-
I in-
VoutCL
M1
M10
M2
1
Latch
M4
Fig. 2. Proposed comparator.
Vref+
Preamplifier
Pre-discharge
how the comparator input referred offset can be reduced at the expense of a high power dissipation. That is because, at the comparison phase the regeneration process in the cross coupled pairs and the amplification of the input voltage occur simultaneously. Hence, the amplification by the input transistors must be fast and large enough to fight against the offset of the cross coupled pairs. A large and fast amplification leads to a higher power consumption. It was concluded that the mismatch between M7 and M8 alone can lead to 0.3 V offset voltage in 45 nm technology [13]. Moreover, the comparator itself has high sensitivity to the output capacitor mismatch [9]. The positive feedback at the output increases the effect of the capacitor mismatch on the overall input referred offset which again demands a more powerful input stage. In order to break the deadlock between the offset and the power consumption, a new architecture is proposed. The double phase architecture takes the advantage of a cascade of amplifying stage and a usual latch stage. More importantly, it involves a significantly smaller input offset voltage without a significant power and area penalty. The rest of this paper is organized as follows: In Section 2 the new comparator architecture is presented along with the analysis of its offset voltage. In Section 3 the simulation results are presented while Section 4 concludes the paper.
2. Proposed comparator 2.1. Circuit architecture The proposed comparator is shown in Fig. 2. The latch circuit is separated from the amplification branches. Each stage operates independently with different clock pulses, ϕ1 and ϕ2. This separation helps the input transistors to overcome the mismatch effect inside the latch circuit before the offset of the latch circuitry is involved in the overall decision making process. Hence, it significantly reduces the input referred offset voltage of the comparator. Moreover, the comparison of the differential input voltage with the differential reference voltage takes effect at the gate source of the input transistors, M3 and M4, leading to fewer transistor count regarding to conventional architecture and therefore lesser offset from mismatch between these transistors. The proposed comparator works with a special three phase signaling. The signal waveform of the comparator is illustrated in Fig. 3. At the first phase or pre-charging phase both ϕ1 and ϕ2 are high. Therefore, the cross coupled inverter pairs are off and
Comparison
tamp
1
Fig. 1. Conventional fully differential dynamic comparator [5].
Amplification
2 Ttotal Vout+ Vout-
Vout time Fig. 3. Conceptual waveforms.
pre-charge transistors discharge the output nodes to the ground. The second phase or the amplification phase will occur when ϕ1 is low and ϕ2 is still high. Consequently, the path to the ground is cut while the reference voltages can feed the input branch and let the input cascade transistors conduct. The difference between the amount of the current produced in the input branches, I in þ I in , is related to the voltage difference between the input and the reference differential voltage. During the amplification phase, the currents set the differential voltage at the internal nodes of the cross-couple latch, V out þ and V out . In the third phase, the comparison phase, the latch circuit operates and the induced differential voltage is boosted in the regenerative loop of the cross-coupled inverters. 2.2. Analysis 2.2.1. Decision point A simple analysis shows that the comparator compares the voltage difference between the input differential voltage with the reference differential voltage, VREFDIFF. At the beginning of the amplification phase, the output nodes are discharged to the ground (V out þ ¼ 0; V out ¼ 0). The amplification phase starts with the activation of ϕ1. Transistors M8 and M7 operate as a small resistor at the source of the input transistors M3 and M4. Since, the voltage level at the inputs of the comparator at the decision point is more than zero, the drain–source voltage of the input transistors is more than their gate–source voltage. Hence, M3 and M4 operate in saturation
Please cite this article as: M. Hassanpourghadi, et al., A low-power low-offset dynamic comparator for analog to digital converters, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.11.012i
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equation:
region and the following equation holds: 2
I in þ ¼ kp3 ðV in þ V ref þ V thp3 Þ ; I in ¼ kp4 ðV in V ref V thp4 Þ2
ð1Þ
where kpi ¼ 12μp cox ðW=LÞi . These currents charge the output capacitors, so the output voltages rise linearly over time. Let CL be the load capacitor and tamp be the duration of the amplification phase. The initial voltage of the output nodes at the start of the third phase is V out þ 0 ¼ I in þ t amp =C L ; V out 0 ¼ I in t amp =C L :
2.2.2. Static offset By definition, the input referred offset voltage VOS of the comparator equals to the differential input voltage that establishes the condition V out þ ¼ V out at the end of the third phase. First, let us assume that the initial voltages at the internal nodes V out þ and V out at the start of the third phase (Eq. (2)) are less than V thn1;2 (threshold voltage of M1, M2). This condition occurs in the operation of the comparator for typical values of amplification time. We can also assume that the effective voltage of the input transistors, M1 and M2, is too small in comparison with the effective voltage of M5 and M6 when the cross-coupled inverters are activated in the third phase. Therefore, the effective current that charges the internal nodes of the inverters is provided through M5 and M6. Hence, CL
ð3Þ
The node which reaches V thn1;2 sooner makes a logic 1 and the other node creates a logic 0. Essentially, in the balanced state, both nodes charge to V thn1;2 at the same time. In that case, integrating over (3) yields Z V thn1 ðI in þ kp5 ðV out þ V DD V thp5 Þ2 Þ dV out þ V out þ 0
Z
¼
V thn2 V out 0
ðI in þ þ kp6 ðV out V DD V thp6 Þ2 Þ dV out
ð4Þ
In order to derive a closed form solution for the offset of the capacitor, it is instructive to analyze the behavior of the comparator in the balanced state where ΔV in ¼ ΔV os . The mismatch between the devices can be modeled using the following equations: I in þ ¼ I in þ ΔI in ; V in þ ¼ V in þ ΔV in ; kp5 ¼ kp6 þ Δkp5;6 ;
V thp5 ¼ V thp6 þ ΔV thp5;6 ; V thp3 ¼ V thp4 þ ΔV thpin ;
kp3 ¼ kp4 þ Δkpin ;
V thn2 ¼ V thn1 þ ΔV thn1;2
ð5Þ
and V thn1;2 is the threshold voltage of M1 where kp is μ and M2. On the other hand, ΔI in is related to Vin with the following 1 2 p cox ðW=LÞ
ΔIin ¼ ΔV in 2kpin ðV in V DD V thpin Þ ¼ ΔV in gmin
ð6Þ
Substituting (5) into (4) leads to extensive, yet straightforward derivations that is beyond the length of this paper. After simplification the overall comparator offset variance is s2V OS ¼ s2V thpin þ s2kpin K 2kpin þ s2V thn1;2 K 2V thn1;2 þ s2V thp5;6 K 2V thp5;6 þ s2kp5;6 :K 2kp5;6
ð2Þ
The sign of V out þ 0 V out 0 determines which way the comparator swings once the comparator enters the third phase, given the internal latch does not incur an offset of its own. Each of these two voltages is proportional to the amount of the input currents. The currents are controlled by V in þ V ref þ and V in V ref . Obviously, the trip point can be set by making a difference between the two reference voltages. In this work, the body of the input transistors is connected to the source terminal to avoid body effect, hence, V thp3 ¼ V thp4 . Therefore, the reference voltage is V REFDIFF ¼ V ref þ V ref .
dV out þ ¼ I in þ þkp6 ðV out V DD V thp6 Þ2 ; dt dV out ¼ I in þkp5 ðV out þ V DD V thp5 Þ2 : CL dt
3
ð7Þ
where K kpin ¼
ðV in V thpin V ref Þ2 ; gmin
¼
K V th
inv
K V thp5;6
I 5;6 ðV thinv Þ ; t amp I t amp I 5;6 in gmin V thinv þ C C
I t amp I 5;6 ðV thinv Þ I 5;6 in C ; ¼ t amp I t amp I 5;6 in gmin V thinv þ C C
K kp5;6
3 I in :t amp V DD V thp5;6 ðV thinv V DD V thp5;6 Þ3 C ; ¼ t amp I t amp I 5;6 in 3gmin V thinv þ C C
I 5;6 ðV Þ ¼ kp5;6 ðV V DD V thp5;6 Þ2 ; I in ¼ kpin ðV in V DD V ref Þ2
ð8Þ
A longer amplification time, tamp, or a larger differential current I in þ and I in reduces VOS because this increases V out þ 0 V out 0 at the beginning of the third phase. If each of these values reaches V thn1;2 , the amount of VOS is only influenced by the input transistors mismatch.
2.2.3. Delay The delay is defined as the time between the start of the amplification phase and the time where 50% of the latch final output is reached. Based on this definition, the inner latch delay can be calculated from derivations presented in [14]. For each inner latch short channel transistor a piecewise linear relation between the current and VGS that is equal to GM is derived. If the differential input of the latch is ΔV in the propagation delay is obtained from T total ¼ τinv lnð0:5ðV DD GNDÞ=ΔV in Þ in which τinv ¼ C L =ðGMPMOS þ GMNMOS Þ. CL is the load capacitance at each output node and GMPMOS and GMNMOS are GM of inner inverters linear transconductance. Depending on the length of tamp, three different scenarios take place with regards to the initial condition of the inner latch before it enters the third phase. This condition influence the equation that governs the delay of the third phase. The first scenario occurs when at the end of the amplification phase, M1 and M2 remain completely off. The second scenario takes place when either one of M1 or M2 is turned on at the end of the amplification phase, yet the differential voltage is small and the output is determined in comparison phase. And in the last scenario, M1 and M2 are both on, and the output is determined at the end of the third phase. If mean of input currents is Iin and τ1;2 ¼ C L =GM1;2 . Therefore the
Please cite this article as: M. Hassanpourghadi, et al., A low-power low-offset dynamic comparator for analog to digital converters, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.11.012i
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delay can be obtained from
0 1 8 > > > B 0:5V DD C > > B C > > > t amp þ τinv ln@ΔI in t amp A > > > > > CL > > 0 1 > > > > > > B C > 0:5V DD > C > t amp þ τinv lnB > @ΔI V A < in th1;2 ðt amp ðC L V th1;2 Þ=I in =τ 1;2 Þ e T total ¼ I in > > > > > > > > > > > 0 1 > > > > > > B > C V 0:5V DD C > L th1;2 þ τ lnB C > > 1;2 @ΔI V A > > I in in th1;2 > > : I in
t amp o
C L V th1;2 I in
C L V th1;2 o t amp o T total3 I in T total3 o t amp
ð9Þ where Ttotal3 is equal to last subfunction of Eq. (9). The equation indicates that the propagation delay is nonlinear to tamp and the sensitivity to the length of the amplification phase degrades when tamp increases. 2.2.4. Kickback noise In the CMOS latched comparators the output voltage variation which is coupled to the input transistors can spoil the input voltage. This effect, which is called kickback noise, should be reduced to gain a higher precision. Fig. 4 illustrates the peak disturbance over the input voltage for different input voltages at 100 MHz clock frequency. The comparator's input is modeled by Thevenin equivalent with a resistor equal to 8 kΩ. The proposed comparator suffers from a large kickback noise, since its structure is similar to the Class-AB comparators. Moreover, as concluded in [15], faster output settling in dynamic comparators brings about a larger disturbance at the input nodes. Consequently, kickback
Peak Input Voltage Error (mv)
103
Proposed dynamic comparator Proposed dynamic comparator with neutralization
102
noise is inevitable in the high speed comparators. Some kickback noise reduction techniques like neutralization suggested in [15] can significantly reduce this effect. The proposed comparator simulated under neutralization technique, and the results are shown in Fig. 4. The reference nodes are usually low impedance, thus, voltage disturbances are smaller on the reference voltages compared to the inputs. Moreover, the main disturbance occurs at the start of the amplification phase, which provides the reference voltages a time to settle to their normal level before the beginning of the comparison phase. In other words, the reference voltage buffers correct their error during the time of tamp. The low power source follower buffers introduced in [16] fulfill the low impedance required for such voltage settling.
3. Simulation results and comparison Fig. 5 demonstrates the layout of the proposed comparator and the output buffer in 0:18 μm technology. The load capacitance due to the output latch is about C L ¼ 10 fF. The comparator takes the area of 180 μm2 while the output latch needs 100 μm2 . The transistor sizing is reported in Table 1. The proposed comparator is simulated in 180 nm and 90 nm CMOS technologies to verify its operation and the consistency with the analytical derivations. Fig. 6 shows the response of the comparator to a 1 mV differential signal for two cases of t amp ¼ 0 s and t amp ¼ 500 ps. It is observed that the amplification time of 500 ps creates a delay overhead about 131 ps at the output. Overdrive recovery test is conducted to investigate the memory effect of the comparator. It was observed that the comparator can successfully detect a 1 mV after a comparison of 1 V. Based on the baseline MC simulations, Fig. 7 combines a number of comparisons between the proposed and conventional comparators in terms of the trade-off between the VOS and the average dynamic power consumption. The power consumption of three sources, including VDD, V ref þ and V ref , are considered as overall
101
Table 1 Transistor sizing for proposed comparator shown in Fig. 2.
100
10-1
10
-1
10
0
10
1
10
2
Input Voltage (mv)
10
3
MOSFET
Size
M1, M2 M5, M6 M11 M3, M4 M7, M8
0:22 μm=0:18 μm 0:66 μm=0:18 μm 0:22 μm=0:18 μm 4:5 μm=0:36 μm 4 μm=0:18 μm
Fig. 4. Peak input voltage error due to kickback noise.
Fig. 5. Layout of proposed comparator and the output latch.
Please cite this article as: M. Hassanpourghadi, et al., A low-power low-offset dynamic comparator for analog to digital converters, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.11.012i
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associated with the transistor pair mismatch. As the frequency raises, tamp decreases in proportion to the overall evaluation time. Therefore, the dependency of the overall offset to the offset associated with the latch increases. Therefore, the amount of VOS is increased. To overcome the effect of the internal latch offset, larger latch transistors must be used at the expense of more power. For a given sizing, the effect of the length of the amplification time, tamp, on the overall offset voltage is shown in Fig. 8. The figure includes both analytical derivations presented in (7) and Monte-Carlo simulation results. In the simulation curve, each
power consumption in the proposed architecture. All comparisons are made in two different technologies of 90 nm and 180 nm CMOS and for three sampling frequencies of 40 MHz, 100 MHz and 1 GHz. In each graph, a target frequency is considered for the design and simulation of the comparators. In each curve, each point represents the offset of a conventional or proposed comparator with different sizing that offer a target offset. In each point, the offset is derived based on the 3s of the histogram of the offsets with 1k sampled Monte-Carlo simulation for the given sizing in that point. Interesting results can be inferred from the simulations. For the same power consumption, the proposed comparator offers about an order of magnitude smaller offset voltage compared to the conventional comparator. In lower frequencies where a large tamp is possible, the offset voltage can be as small as the offset
50
T
Calculated Vos Simulated Vos
= 0.585ns
45 2
40
Vout (v)
1.5 1
Vos (mv)
0.5 ns
131 ps
T
35 30
T
25
0.5
= 0.683ns
= 0.779ns = 0.874ns T = 0.965ns T = 1.06ns T = 1.13ns T = 1.2ns T
T
20 15
0
= 1.21ns
T
= 1.21ns
10 0
-0.5 0
0.5
1
1.5
2
2.5
200
400
600
1000 1200 1400 1600 1800 2000 tamp (ps)
Time (ns)
Fig. 8. Trade-off between amplification time and offset. Simulated and calculated VOS as a function of tamp, printed data represent propagation delay (ns) (each point calculated with 1k Monte-Carlo simulation).
Fig. 6. The step response of proposed comparator to ΔV in ¼ 1 mV for t amp ¼ 0 s and t amp ¼ 500 ps in 180 nm technology.
90nm technology
180nm technology
300
200 Proposed Conventional
150 40MHz Vos(mv)
800
3
200 100 100 50 0
0
5
10
15
20
25
250
0
10
20
30
40
200
200 100MHz Vos(mv)
0
150
150 f 100 100 50
50 0
0
10
20
30
40
250
0 10
20
30
40
50
60
50
100
150
200
250
300
1GHz Vos(mv)
200 200
150 100
100
50 0
0
100
200 Power(µw)
300
400
0
0
Power(µw)
Fig. 7. A comparison between the conventional and proposed comparator in 180 nm and 90 nm CMOS technologies (each point represents the offset associated with 1k Monte-Carlo Baseline simulation on a differently sized comparator for a targeted offset).
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80 VOS (mv)
60 40 20 0 0.5
0.6
0.7
0.8
0.9
1
1.1
VCM (v)
Fig. 9. Offset voltage vs common mode voltage.
Power (µW)
40 30 20
frequency at supply voltage of 1 V and the capacitive load of 10 fF. The dynamic offset, VOS, is estimated, by adding an intentional 1 fF capacitive load mismatch at the output for all comparators in addition to the stochastic mismatch of the transistors. The comparators are designed such that they achieve similar delay at ΔV in ¼ 1 mV. The results are reported in Table 2. The tamp in the proposed comparator was set to 20 ps. The offset voltage of the proposed comparator is at least three times smaller than two other dynamic comparators. Moreover, the power consumption of the proposed comparator is about 44% of the conventional and 85% of the differential pair structure. The power consumption of proposed comparator is considered to be equal to power consumption in three sources: VDD, V ref þ and V ref . The area of the comparators is estimated based on the size of the transistors and the number of nodes for a given comparator. It must be noted that shortcircuit power dominates the dynamic power, therefore power consumption is not completely related to area consumption.
10 0 0.5
0.6
0.7
0.8
0.9
1
1.1
4. Conclusion
VCM (v)
Fig. 10. Power consumption vs common mode voltage.
Table 2 A comparison between comparators. Comparators
V OS ð3sOS Þ (mV)
Power ðμWÞ
Delay (ps)
Area ðμm2 Þ
Dynamic VOS (mV)
Resistor divider [5] Differential pair [2] Double-tail comparator [17] Proposed
192 102 23.4
116 60 82
170 550 130
1.55 3.84 3.5
Very large 55–65.1 20.1–24.1
33
51
152
3.3
15.1–17.9
The previously reported comparators are sized to achieve nearly the same delay in the simulations in 90 nm CMOS technology.
point represents a set of 1k samples Monte-Carlo Baseline simulations in 180 nm CMOS technology at the sampling frequency of 100 MHz. The VOS derived from the calculations is less than simulated by a mere 5 mV. The difference is due to the dynamic offset and the mismatch caused by kp5;6 and kpin. Interesting results can be concluded from Fig. 8. For a given size of the devices a trade-off exists between the total delay and comparator offset. As expected from the derivations presented in Eqs. (7) and (8), large enough amplification time offers an effective mismatch cancelation of the inner latch transistors. In that case, the offset voltage is only affected by the mismatch of the input transistors. In this simulation, the input referred offset voltage caused by the input transistors is 14 mV. The comparator offset reaches to this value when tamp is about 1 ns. The figure also suggests that for large enough amplification times (e.g., t amp 4 600 ps) the offset voltage has minor sensitivity to the tamp. It suggests that a relaxed timing circuitry (e.g., an inverter chain with determined minimum delay) can be used for the generation of the clock signals. Fig. 9 illustrates the sensitivity of the input referred offset to input common mode voltage (VCM) and Fig. 10 depicts the power consumption. Decreasing the amount of VCM increases Iin, and magnifies K kpin . Consequently, the input referred offset increases. On the other hand, increasing common mode voltages, decreases the current consumption in the pre-amp section (Iin), which brings about more sensitivity to the inner latch mismatch which highly augments the offset. To draw a comparison, the proposed and two other comparators were simulated in 90 nm CMOS technology at 1 GHz sampling
A new low power and low offset dynamic comparator was proposed. The structure benefits from two phase signaling to cancel the mismatch of the inner devices. The offset voltage was obtained using analytical derivations as a function of mismatch and delay. The derivations were verified with high precision exhaustive Monte-Carlo simulations. The propagation delay of the comparator was calculated and the trade-offs between the speed and offset were explained. The comparator was simulated in CMOS 180 nm and 90 nm technologies and a good agreement between simulation and equations was obtained. At 1 GHz clock frequency, the power consumption of the proposed comparator is reduced to 44% of the conventional comparator power consumption while the offset is 33 mV that is at least three times smaller than offset voltage of the conventional comparators.
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Please cite this article as: M. Hassanpourghadi, et al., A low-power low-offset dynamic comparator for analog to digital converters, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.11.012i