- Email: [email protected]
A microprogrammable high-speed data collection system for position sensitive x-ray detectors
Nuclear Instruments and Methods in Physics Research 225 (1984) 335-346 North-Holland, Amsterdam
335
A MICROPROGRAMMABLE HIGH-SPEED DATA COLLECTION SYSTEM FOR POSITION SENSITIVE X-RAY DETECTORS H. H A S H I Z U M E
Research Laboratory of Engineering Materials, Tokyo Institute of Technology, Nagatsuta, Midori-ku, Yokohama 227, Japan Y. I I T A K A
Faculty of Pharmaceutical Sciences, University of Tokyo, Hongo, Bunkyo- ku, Tokyo 113, Japan r
T. O G A W A
Tri-C corporation, Dai-ichi Fuyo Bldg, 2-4-6 Mita, Meguro-ku, Tokyo 153, Japan Received 31 January 1984
A high-speed data acquisition system has been designed which collects digital data from one- and two-dimensional position sensitive X-ray detectors at a maximum average data rate of 1 MHz. The system consists of two separate fast buffer memories, a 64K word by 20-bit main storage, two timers, a display controller, a computer interface and a keyboard, controlled by a specially designed microprogrammable microprocessor. Data collection is performed by executing a microprogram stored in the control storage; data coming from a detector are first accumulated in a small but fast buffer memory by hardware and transferred to the main storage under control of the microprogram. This design not only permits time-resolved data collections but also provides maximum speed, flexibility and cost-effectiveness simultaneously. The system also accepts data from integrating detectors such as TV cameras. The system has been designed for use in experiments at conventional and synchrotron X-ray sources.
1. Introduction As hard X-rays from synchrotron light sources find a wide variety of applications, it becomes more evident that their characteristic high photon flux is fully usable only in experiments with fast detectors. Various approaches are thus being made to develop fast position sensitive detectors. Such detectors are most useful in time-resolved experiments, where many time frames of a diffraction diagram are recorded from a sample under rapid structural changes to millisecond frame resolutions; data collection is usually performed by detecting X-ray photons with a position sensitive counter and accumulating this information at separate locations in a digital store in synchronization with changes of the sample enviroment. The speed of various non-integrating position sensitive detectors depends on the two times: the time needed for the detector to derive a digitized coordinate of a detected event and the time spent in processing and storing this information in the associated data collection system. Since these times add to limit the high-count rate capability of a particular system, the latter time need be kept negligibly short as compared with the former time. Each synchrotron radiation facility has developed its 0167-5087/84/$03.00 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)
own data collection system [1]. A project was organized in 1979 to develop instrumentation for the Photon Factory, where priority was given to various attempts to build fast position sensitive detectors. The present paper describes a digital data collection system designed to support such detectors. The system has been reported in greater detail in the project reports [2,3] and elsewhere [4].
2. Design considerations In view of the present detector technology, we assume 1 MHz as a maximum average data rate that should be accommodated by our digital system. To meet this goal, a single event needs to be processed and recorded in less than a few 100 ns. This requires a memory system completing a read-modify-write cycle in a similar time or less at random addresses. In the meantime, a typical time-resolved experiment records 16 to 64 one-dimensional diagrams each containing 256 data. A practical wire-chamber area detector provides 64 × 64 to 256 × 256 resolution elements, requiring 4K to 64K memory words. The memory size requirement is further increased by a factor of, say, 16, if two-dimensional diagrams are to be recorded in time resolution.
336
H. Hashizume et al. / Microprograrnmable high -speed data collection system
Each word must be at least 20-bits long to minimize overflows that can occur in high data-rate applications. Thus, we need a fast, large and inexpensive memory system. When extremely high data rates over 1 M H z are anticipated, integrating detectors such as TV cameras and photodiode arrays are potentially useful; such detectors are able to store event information on the detection surface and practically have no dead time. The outputs are in the form of video signal produced in synchronization with external readout signals; the video amplitude is related in some way to the number of photons absorbed in each pixel during the readout period. A standard TV picture contains useful - 480 × 480 pixels scanned in 1 / 3 0 s. After digitization, sequential data at a regular rate of - 7 M H z are generated. It is desirable that the data collection system also accepts such data. The system needs to be highly flexible. Two modes of data collection, normal and time-resolved, should be selectable. In the latter time frame durations are desirably adjustable on a frame-by-frame base. At the start of each data collection, the system should generate a timing signal that can be used to trigger environmental conditioners for the sample. Although good bi-directional communications with a data processing computer are essential, it is advantageous that the system works also as a self-complete machine and collects data without control by the computer.
3. System architecture Fig. 1 shows the hardware architecture of our system. The system can be simply described as consisting
of four major units: a control microprocessor, two separate buffer memories and a 64K word by 20-bit main memory, connected together by an address bus and a data bus, each 20-bit wide. This design is based on the philosophy that maximum speed, flexibility and cost-effectiveness are provided simultaneously when we employ a small but fast buffer memory to accumulate data from a position-sensitive counter and transfer the buffer content at programmed points to a large main store under control of a microprogram. A difference between one- and two-dimensional counters is the bit length of output data. While data (i.e., event addresses) out from one-dimensional detectors are normally 8- or 9-bit long, two-dimensional detectors produce 12- to 16-bit data depending on the detector size. This difference affects the optimum designs of high-speed buffer memories. Thus, our system includes two separate buffers, a cache memory and a scaling memory followed by a derandomizing memory, intended for use with one- and two-dimensional position sensitive counters respectively. The cache memory and the scaling memory receive data via separate cable connectors on the rear panel of the chassis. Data coming from a detector are first accumulated in the selected buffer memory by hardware. At programmed points of data collection, a microprogram makes access to the active buffer and the main memory; the contents at specified memory addresses are read and subject to manipulation as dictated by the microprogram. The result is directed to the main memory and stored at specified addresses. The cache memory and the derandomizing memory have a double buffer structure; while one buffer is being read by a microprogram, an alternate buffer accepts data from the detector. This allows data collection without interruption.
MICROPROCESSOR ..~ A/D
[--DATABUS (20)
<~
ADDRESSBUS (29)--.
I COMPUTERI Fig. 1. General block diagram of the data collection system.
q
BUS
>
1 ->
H. Hashizume et al. / Microprogrammable high-speed data collection system
The microprocessor is the brain of the system. It controls the system hardware to collect data from external detectors and to display the accumulated data on a CRT screen. Further, it handles communications with the host computer to send and receive data. All these tasks are carried out by executing a microprogram stored in microprogram memory. Our processor includes three PROMs, which store microprograms developed for experiments employing the cache memory, the scaling memory and TV-type detectors. These microprograms are made available alternatively by front-panel switches. Fig. 1 shows two timers, a video data input unit, a CRT display controller, a computer interface and a keyboard tied by the bus lines. These devices form independent logical units and can be the source a n d / o r destination of data transfer by microprograms. The hardware specifications of the various components are given in table 1. The system is built on eighteen 220 x 270 mm 2 wire-wrap cards housed in four chassis mounted on a standard rack. Photographs of the complete system are shown in figs. 2a and b.
337
Am2910 microprogram controller, condition-code multiplexer, vector map ROM and priority interrupt controller. The scratchpad memory is a 16-word by 20-bit memory usable as general-purpose registers. A special design of this memory is that each word is accessible by parameter keys on the system's keyboard; key operations allow the content of the selected word to be displayed and modified to a new value. The scratchpad memory is normally used to hold parameters for timeresolved data collection and post-experiment display. The former parameters can also be given from the host computer. The BCD-to-binary converter is to save microprogram words in decoding a given parameter.
4. Control processor 4.1. Microprocessor design
The control processor is built around Advanced Micro Devices Am2901B bit-slice microprogrammable microprocessors. The Am2901B is a 4-bit microprocessor slice containing a high-speed ALU and a 16-word by 4-bit two-port RAM [5]. We cascade five of this device to form a 20-bit ALU (see fig. 3). The processor includes a microsequencer, four alternatively usable microprogram memories, a pipeline register, a scratchpad memory, a define-constant register and a BCD-to-binary converter. Three of the microprogram memories are PROMs as mentioned earlier, while the remaining one is a writable control storage capable of loading any microprogram from the host computer as well as from the system's panel switches. Each microprogram memory has 512 address locations to hold various microinstructions. A microinstruction word is 44-bit long, where some bits control the hardware of the system, while others define the location in the microprogram memory of the next microinstruction to be executed. Microinstructions are fetched word by word to the pipeline register under control of the microsequencer, and executed by the machine. While the current microinstruction is held at the pipeline register, the next microinstruction is being fetched and set up at the inputs to the pipeline register. Overlapped fetching and execution doubles the system throughput as compared with a non-pipelined design; the basic machine cycle time is 200 ns in our system. Fig. 3 shows that the microsequencer uses such units as
Fig. 2a. Appearance of the data collection system. From top to bottom, main controller, display panel, keyboard, microprogrammer's panel and power supply.
338
H. Hashizume et al. / Mtcroprogrammable hzgh-speed data collectton ~ystem
Fig. 2b. Layout of the keyboard. Function keys on the top row, parameter-key matrix on the left, digital switches and data entry key in the center, display control keys, rotary encoder and potentiometers on the right.
Table 1 Hardware specifications of the system Power Physical dimension Unit process time Control Microprogram memory Data length ALU functions General purpose register Cache memory Scaling memory Derandom memory Main memory Video data input unit Timers Display control Computer interface
Keyboard
Other functions
ac 100 V / 5 0 - 6 0 Hz, approx. 500 VA 530 X 650 x 1660 mm 3 200 n s / s t e p pipeline control by microprogramming ROM: 512 W (44 bits)X3, WCS: 512 W (44 bits) 20 b i t s / w o r d R + S , S , R , R - S , R v S , RA S,P, AS, R'~'S, R v S, left and right shift 32 registers/20 bits 512 W / 1 6 bits x 2, access time: 20 ns 64 K W / 3 bits, access time: 55 ns 1 K W / 1 6 bits x 2, access time: 70 ns 64 K W / 2 0 bits or 16 K W / 8 0 bits, access time: 70 ns video amp., discriminators, ADC 8 bits/50 ns, buffer registers, 80-bit full adder 1 ms timer and 1 s timer (BCD 5 digids) CRT monitor: X-axis 8 bits, Y-axis 8 bits, Z-axis 4 bits digital I / O : program cont. oh. 16 lines multiplexer cont. ch. 16 lines interrupt: 4 fines 7 function keys, 16 parameter keys, 5 digit data entry switches, 5 display control keys, 7 potentiometers, LED displays BCD-to-binary converter, BCD up-down counter, display panel, microprogrammer's panel
339
H. Hashizume et al. / Microprogrammable high-speed data collection system
>
DATA BUS (20)
BCO-TO-BINARY • CONVERTER
0.
I 12 /
=l~Am2910/
A L U
! /
0
17,
12
/ I I
~E~OR~
~l CLOCK [ - I PANEL SW. I CONTROLLER , ADOR,SYNC
I-I
"4
/ '-'1 P,~E',NE R~O,ST~RI I INTERRUPT / REOUEST I INTEFRUPT I
4 8 RAM A.B
INTERNAL CONDCTION
EXTERNAL CONDITION
0n-4 OVR F3 F=O
10 SOURCE,FUNO, OEST.,On
~"
>
CONTROL BUS
SOU REOUEST
<
~_>
ADDRESS BUS {20)
<
Fig. 3. Microprocessor block diagram.
Sequence Control field Format AL.U
BR
format
format
F'ormat Control code (binary)
0 1 2 3
7 8
Bus Control field
FormatControl held
ALU field
11 12
1516
2021
2324
26
Memory Address Increment field 0 1 2 3 7 8 11 12
1516
2021
2324
26
0 1 2 3
15 16
2021
2324
26 27
28
30313233
3536
3940
43
0
32
43
0
BHL1
format
1
BHL.2
format
2
7 8
7 8
3
Mask
format
4
SPM
format
6
11 12
1516
2021
2324
I
2627
43 Bit Handling
0 1 2 3 format
43 Bit Handling
0 1 2 3
DC
11 12
7 8
I1 12
0
1 2 3
0 1 2 3
Fig. 4. Microinstruction formats.
2021
2324
i,s.s I ,s.o
oo.o
IMAI ~0NO COND
1516
7 8
I 7 8
11 12
MSi
15 16
BUS-S [ 11 12
15 16
2627
43
o I 2021
BUS-D
2324
FORMATI
2021
2324
I
26
D
[ ~ 26
Oe,.oeOons,n,
I
2g
43
Interrupt Mask
I 40
43
340
H. Hashizume et al. / Microprogrammable high-speed data collection system
4. 2. Microprogramming
Fig. 4 depicts seven formats defined to organize the microinstructions. These are the A L U , BR, BHL1, BHL2, DC, Mask a n d SPM formats. All the formats are 44-bit wide a n d use identical field definitions in the left 27 bits. Here we define such fields as M e m o r y Address I n c r e m e n t field, Sequence Control field, Bus Control field, F o r m a t C o n t r o l field a n d A L U - D field. The purpose of the M A I field is to i n c r e m e n t m e m o r y address counters without d e p e n d i n g on the A L U operation. This allows these two operations to occur in the same microinstruction, thereby permitting developing efficient micro-routines for block d a t a transfer between memories. The Sequence Control field consists of the C C E N , C O N D a n d MSI fields, which determine the address of the next microinstruction to be executed; the MSI field selects one of the 16 different sequence control instructions for the Am2910 m i c r o p r o g r a m controller [5], while the C C E N and C O N D fields furnish test conditions for c o n d i t i o n a l instructions. The Am2910 provides powerful conditional instructions for branching to various m i c r o p r o g r a m sequences d e p e n d i n g upon test condition inputs. A m i c r o p r o g r a m is organized to execute tests on various inputs waiting for the condition to come true. W h e n the true condition is reached, the m a c h i n e b r a n c h e s a n d executes a set of microinstructions. Test conditions defined in our system include not only the A L U status (i.e. internal conditions) but also various flags representing the system status (i.e. external conditions): interrupts requested, buffer full, zeros in the timers a n d counters, enabled function keys a n d display keys, h a n d s h a k e signals in the I / O channels of the host computer, etc. The Bus Control field is to specify the source a n d d e s t i n a t i o n for data transfer o n the bus as well as the direct data source for some A L U operations. T a b l e 2 lists sources a n d destinations defined. It will be seen that various memories, registers, counters a n d timers are coupled to the address bus or the data bus. To select one of the seven formats, we code binary n u m b e r s in the 3-bit wide F O R M A T field. Fig. 4 shows that when this n u m b e r is a zero, two formats A L U a n d BR are selected simultaneously. To identify the BR f o r m a t a binary 1 is coded in the A L U - D field, which indicates N o O p e r a t i o n in the A L U format. A l t h o u g h we d o not go into the details of the A L U format, it is pointed out that this f o r m a t (and hardware) is designed to support all of the functions available with the Am2901B [5]. The B R f o r m a t is defined to provide the ability to b r a n c h to a desired m i c r o p r o g r a m address with reference to direct data. This f o r m a t is also used with some sequence control instructions involving a load-counter operation; such instructions are often used to set up a loop in the microprogram.
Table 2 Sources and destinations for data transfer on the bus lines BUS-S HXD Code
6 7 8 9 A B
C D E
NOP Enable ALU data source Enable ALU address source Enable 0 - F switch address source Enable scratchpad memory data source Enable cache memory data source (clear after read) Enable main memory data source Enable define constant data source Enable up/down counter data source Enable T1 timer data source (ms unit) Enable T2 timer data source (s unit) Enable CPU digital output register data source Enable digital switch data source Enable display marker data source Enable scaling memory data source and increment address counter (read only) Enable derandom memory data source and increment address counter (clear after read)
BUS-D HXD Code
9 A B
C D E F 10 11 12 13 14 15 16 17 18 19
NOP HALT Store scratchpad memory address register Store cache memory address register Store main memory address register Store scratchpad memory Store cache memory Store main memory Store define constant register (for BCD to binary answer) Store BCD-to-binary converter Store up/down counter Store T1 timer (ms unit) Store T2 timer (s unit) Store display X-axis register Store display Y-axis register Store display Z-axis register Store CPU digital input register Store keyboard display register Store panel display register 1 (TO) Store panel display register 2 (NO) Store panel display register 3 (not used) Store panel display register 4 (not used) Store compare address register Y1 Store compare address register Y2 Store zero in scaling memory and increment address counter Store zero in derandom memory and increment address counter
341
H. Hashizume et al. / Microprogrammable high-speed data collection system
In order that the processor be able to exert selective control on various elements, two bit-handling formats, BHL1 and BHL2, have been defined, each accomodating up to 17 operations. Each bit of the Bit Handling field is associated with a specific operation, and a logic 1 at a particular bit position asserts that operation. The BHL1 includes such operations as start T 1 / T 2 timers, couple/decouple the CRT X, Y, Z-axis registers with the data bus, reset flags, reset interrupt requests, generate interrupt request to the host computer, etc. The BHL2 contains such operations as generate handshake signals in the I / O channels of the computer, o n / o f f buzzer, start/stop data collection in the cache or scaling memory, alter the cache memory connection, reset address counters of the scaling memory and the derandomizing memory, etc. The bit-oriented assignment has the advantage that two or more operations can be directed simultaneously. To take this advantage, we have carefully distributed the various operations to BHL1 and BHL2. The DC, Mask and SPM formats refer to the direct data contained in the microprogram word. The DC format serves to load any value less than 217 - 1 into the define constant register. As noted earlier, the scratchpad memory is designed so that the parameter keys can play on the memory content. This memory has another feature that it is addressabl e by a single microinstruction. This is done by employing the SPM format, where a desired memory address is specified in the SPM Address field occupying bit 40 through 43. The scratchpad memory can also be addressed via the address bus. This takes, however, at least two microinstructions. One of the Am2910 instructions C O N D I T I O N A L
J U M P VECTOR provides the capability of performing interrupt-type branching at the microprogram level. Our system utilizes this capability to handle commands given to the system from the host computer or the system's function keys. Table 3 lists fifteen events that generate interrupt requests. With each event is associated an interrupt level of a fixed priority. The Mask format is defined to selectively inhibit interrupt requests by program. Bits in the Mask field are oriented to individual interrupts in the descending priority order from the MSB to LSB. We have devoted microprogram word address 1 through 15 to the vector area. From the microword structure described above, it will be seen that a single microinstruction can perform three independent controls simultaneously besides the next address control: memory address increment, data transfer on the bus and a specific control directed by the format. This allows data collection programs to be written in minimum microinstruction counts, which has the effect of improving the system throughput.
5. Buffer memories 5.1. Cache memory
The cache memory consists of two equivalent 512word by 16-bit memories, which form a double buffer for data acquisition (see fig. 5). Each memory is built using ECL memories of 20 ns access time. All address and control signals are TTL levels and routed to the active memory through the 50-pin rear panel Amphenol connector; the control signals use a negative logic. We
Table 3 Microprogram interrupts Abbreviation ")
Name
Event source
Vector address
Priority
ERR 1 ERR 2 TOUT * SCLR * STOP * MCLR * START * SADDR
Error 1 Error 2 Time out 1 s System Clear Stop Data Collection Memory Clear Start Data Collection Set Top Memory Address for Data Transfer Set Data Length for Data Transfer Set Parameter Read Main Memory Write Main Memory Display Main Memory Content Load Parameter from Digital S w i t c h Access to Scratchpad Memory at the Address Specified by 0-F Switch
System System System Keyboard/Host CPU Keyboard/Host CPU Keyboard/Host CPU Keyboard/Host CPU Host CPU
1 2 3 4 5 6 7 8
(High)
Host CPU Host CPU Host CPU Host CPU Keyboard Keyboard Keyboard
9 A B C D E F
* SDLEN * SPARA * RMEMO * WMEMO * DISP * LDSW 0FSW
a) Events marked with * are system commands.
(Low)
H. Hashizume et al. / Microprogrammable high- speed data collection system
342 <
DATA BDS (20)
d--ADDRESS BUS ~20~
3
r.
.
.
.
BUFFER I
~EOISTER
J
E
I
BLS Ta'ANCENEN
~
20
MEMORY SELECTOr':
i -4 80
V!OEO L~,"
I
VIDEO
MAIN MEMORY
UNff /9
I DETECTORINTERFACEI DATA
DRDY
AGK
Fig. 5. Block diagram of the cache memory and the main memory.
employ a very simple control scheme of data-ready/acknowledge type. When the external device (i.e., the position encoding electronics associated with the position sensitive counter) is ready to write data, it asserts D R D Y with the address data set up not later than 15 ns after the high-to-low transition of the D R D Y signal. Then, the active memory is incremented by hardware at the address presented in 100 ns. At the completion of the increment cycle, the memory returns the A C K signal, which can be used to initiate a next encoding cycle in the external device. The two cache memories, CM1 and CM2, are alternatively connected to either the external device or the system data bus. This connection is controlled by bithandling instructions. In one configuration, CM1 accumulates data from the detector while CM2 is read by a microprogram. In time-resolved experiments, timer T1 is loaded with a frame time and the memory connections are interchanged when condition T1 = 0 is reached. N o w CM2 is allowed to collect data for the next frame with timer T1 loaded with the next frame time. Simultaneously, CM1 is made available to the microprogram; a set of microinstructions read and add the contents of CM1 to those of the main memory, whereby the origin of the data array is shifted by a multiple of 512 (or any number). To reduce the microinstruction
count, a special microcode is provided to clear the cache memory after each read (see table 2). This used in conjuction with a Memory Address Increment code allows to transfer the array of 512 data into the main memory in about 410/~s. At the completion of the data transfer, the accessed cache memory is automatically cleared and ready for data collection of the next frame. 5.2. Scaling memory and derandomizing memory
The data buffer for two-dimensional position sensitive counters consists of the scaling memory and the derandomizing memory (fig. 6). We assume that for each detected event the detector electronics processes a pair of (x, y ) coordinates to deliver a linear address. The address and control signals are furnished at the inputs to the buffer register via a 50-pin chassis-mounted connector. The scaling memory is a 64K word by 3-bit memory constructed from MOS memories of 55 ns access time. It uses control and timing schemes similar to those employed in the cache memory; on negative transition of the ~ signal, the address is latched into the buffer register and a hardware sequence is initiated in the scaling memory to increment the content at the address presented in 120 ns. The scaling memory works like an array of 1 / 8 scalers associated with
H. Hashizume et aL / Microprogrammable high-speed data collection system
<
DATA
BUS
fl DATA
343
I
BUFFER
fl
MUX
fl ADD
SM I DOUNTER ADDRESS
¢
~ ~AN~ :SS
I INCREMENTER DARRY DETECTOR
SELECTOR
&
¢
'~
ADD~ESS
fl SMDM I CONTROLLER f] BUS OONTROL
Fig. 6. Functional block diagram of the scaling memory and the derandomizing memory.
individual 64K (or less) resolution elements i n the two-dimensional detector. The overflows that occur when a memory word counts eight events are watched by the carry detector. Whenever a carry is detected, the SMDM controller issues a write enable signal, which makes the address latched in the buffer register pushed into the derandomizing memory. This push is completed in 70 ns and the associated DM address counter is incremented by hardware. The derandomizing memory uses two equivalent 16bit wide, 1K word deep first-in/first-out (FIFO) buffers, DM1 and DM2, alternatively connected to either the buffer register or the system data bus. The connections of DM1 and DM2 are initialized by a microinstruction and interchanged by hardware when 1024 data are pushed into the active buffer. Full data entry is flagged. A microprogram is then organized to repeat a test on condition Buffer Full;" when the test is passed, the DM address counter is reset to sequentially transfer the buffer content to the address counter of the main memDry. A special microcode (see table 2) allows to clear the derandomizing memory after each read and increment the associated address counter in a single execution cycle. The next mieroinstructions read the main memory, add eight to the content, restore the new value at the same address. These whole operations can be performed in a four-instruction loop. It takes then four microsteps, i.e. 800 ns, to transfer a record in the derandomizing memory to the main memory. Since one record in the derandomizing memory represents eight counts in the scaling memory, the system hardly suffers from a rate problem at an incoming data rate of 1 MHz. At the cessation of a data collection, the scaling memory and the derandomizing memory are read by a microprogram and the existing data are added into the main memory. The system also allows to collect two-di-
mensional data in time resolution unless the total number of recorded data exceeds 64K.
6. Main memory and video data input unit The main memory uses stati~ RAMs (access time 70 ns) assembled in four banks. Each bank has a capacity of 16K words/20 bits for a total of 64K words/20 bits. In addition to the I / O port interfacing to the system bus, the memory has a port to read and write 80-bit words. This port is used to store video data in a reduced effective cycle time for sequential accesses. The video unit in fig. 1 includes a fast 8-bit ADC, double buffer registers and a 80-bit full adder; four consecutive ADC outputs are arranged into a 80-bit word and added to the content of the corresponding memory location by hardware. This allows the video signal to be digitized and recorded at a standard TV scanning rate. To .......accommodate an entire TV picture in the main memory, the video unit is programmed to sample 256 data points on a scanning line, and data for odd and even picture fields are'added: After a ~ven.number of picture frames are thus integrated, the main memory is read by microprograms in words of 20 bits via the bus.
7. Data-collection program The data collection system described above is very flexible because of its programmable design. The system can be adapted by microprograms to a wide assortment of experimental conditions and requirements. Microprograms can be assembled on the control computer and directly loaded down to the writable control storage of the system. To facilitate microprogram development, we
344
H. Hashizume et al. / Microprogrammable high -speed data collection system
have organized our own microprogram assembler, which allows microinstructions to be represented in mnemonics. The assembler has an error checking capability and compiles symbolic statements to produce bit patterns (i.e. the object program) on the disc of the control computer. An IPL program transfers thus created microprograms to the WCS. The system can also be operated by one of three internal microprograms stored in the ROMs; a front panel toggle switch allows to select the WCS or R O M for the microprogram source. The internal microprograms are of general-purpose nature, designed for data collection employing different classes of detector (see sect. 3). The following paragraphs describe one such microprogram. This microprogram has a modular structure with each module executable by a system c o m m a n d (see table 3). It also includes a power-up routine beginning at microprogram memory address 0 to initialize the system. Two options, on-line and off-line, are selectable by the function key on the keyboard (see fig. 2). Depending on the option selected, the microprogram accepts all commands and parameters from either the control computer or the system keyboard. The data collection module is designed to collect data from a linear position sensitive counter delivering 9-bit addresses to the cache memory. There are two modes of data collection: normal and time-resolved. Either mode should be preselected by the function key. Fig. 7 shows a timing diagram for the time-resolved mode. We can use four different frame times T 1 through T4 with respective repetition numbers N l through N 4. T 1 to T4 can be any value between 0 and 99999 ms, while N 1 to
START
N 4 can be 1-99999. Values for these parameters must be
given prior to data collection. The microprogram checks if 1 < N l + N2 + N3 + N4 ~ 1 2 8 and O < T I N I +- "~ N2 + 7 ~ N 3 + T 4 N 4 ~ To, and gives a warning by buzzer and alarm light for invalid parameters. Data collection is initiated on S T A R T command. The microprogram first clears both the cache memory and the main memory and then opens the gate to admit data into the cache memory. Simultaneously, a TTL-level pulse of 1 ~s duration is provided on a B N C connector, which is used to trigger enviroment conditioners for the sample. An arbitrary delay can be placed between pulse generation and data collection, if necessary. During data collection, the microprogram samples incoming data every 1 /~s to display the current contents of the active cache memory on the C R T screen. Whenever the frame time expires, the microprogram switches the cache memories and adds the accumulated data to the contents of corresponding locations in the main memory. At the completion of one data collection cycle, the gate is closed to resume the next cycle after a period T0. The course of experiment is indicated by front panel five-digid counters displaying current values of TO and N o . When NO cycles of data collection are completed and if the on-line option is selected, the microprogram generates an interrupt to the computer, which is normally answered by a task to read the main memory. The display module is designed to work on manual operation of the display keys on the keyboard (see fig. 2). A histogram of accumulated data for any desired frame is shown on a C R T screen on entry of frame number from the digital switches. A display marker is driven to a point of interest on a histogram by opera-
r-[
MEMORY CLEAR J
I
GATE ON TRIGGER SIGNAL
1
I
2
No
FI
I1 NI
N2
N3 N4
NI
N2
N3
IIII IIIIIII CPU INTERRUPT I
TI
T2
T3
T4
PARAMETER I TRANSFER
DISPLAY
Fig. 7. Timing diagram for time-resolved data collection.
N4
1!1
NI
N2
N3 N4
I"" "'1"'1'"[ MEMORY OATA TRANSFER
I I ........
I
H. Hashizume et a L / Microprogrammable high-speed data collection system
345
,,¢
._I I..I.I Z Z ,< --rU~ ~. ~;)_
Z 0 U
0
4'o
'
8'o
'
16o
CHANNEL NUMBER Fig. 8. Time-resolved equatorial diffraction diagrams recorded from stimulated and stretched muscle. A frog sartorius muscle on a small-angle camera was stimulated for 3.5 s by a pulse train and stretched slowly 1 s after the onset of the stimulation. Data were accumulated from five stimulations and stretches at 0.5 s frame resolution. Left halves of the diagrams are masked for clarity. From left to right on each diagram, background scattering peak, the 1,0 reflection and the 1,1 reflection. Note the intensity changes of the reflections in response to the stimulation and stretch.
tion of the ~utary encoder to exhibit the channel number and recorded count on LED displays. It is also possible to display a region of interest in a magnified horizontal scale. Also, histograms of any selected two frames can be shown simultaneously for quick visual comparison. Fig. 8 shows an example of data recorded from live frog muscle actively contracting on a small-angle camera. The diffracted X-rays were detected with a laboratorymade linear proportional counter using a 800 ns delay line for readout and a T A C - A D C combination for position encoding [6-8]. The average count rate was - 10 kHz at a rotating-anode X-ray generator. A more critical test of the system will be made at Beam Line 15A of the Photon Factory, where a fast linear detector has been built as a part of a small-angle diffractometer [9-11].
8. Communications with computer The data collection system is interfaced to a MELCOM 70-30 minicomputer, which was originally thought to be the control computer for BL-15A of the Photon Factory. The computer interface of our system is compatible with communication features of a parallel
I / O port of the MELCOM 70-30. This port provides four data channels and four interrupt control lines; two of the data channels are program controlled, while the other two are multiplexer controlled. Each data channel has 16 parallel unidirectional data lines. Communications are handled by a microprogram at one end and by a control program at the other end. Powerful subroutines provided by the Real Time System Package allow the control program to be written in a FORTRAN language. The control program transmits commands and reads the device status word over the program control channels. The multiplexer channels of the MELCOM 70-30 permit block data transfer at a rate of 20K words/s. Through these channels, the control program transfers parameters, sends and receives memory data and dumps a microprogram onto the system WCS. To read or write the system main memory, the program first specifies the top memory address and the data length to be transferred. Since the MELCOM 70-30 is a 16-bit machine, one memory data in the system takes two computer memory words. Similarly, three computer words are spent to represent a microinstruction for the system. The current version of the Real Time System Package allows to transfer a data block of 256 to 32768 words in a single subroutine call. This does not, however, interfere with. the need to read/write a large data block in a short time.
346
H. Hashizume et al. / Microprogrammable high -speed data collection svstem
W e t h a n k M. Ogawa for his helps in developing the m i c r o p r o g r a m assembler. The data shown in fig. 8 were collected in collaboration with Drs. H. T a n a k a a n d T. T a m e y a s u from Teikyo University. We also appreciate interest a n d support from Prof. S. Hosoya, Prof. T. Mitsui a n d Prof. K. Kohra. This work is s u p p o r t e d by a G r a n t from the Ministry for Education, Science a n d Culture.
References
[1] Prec. Int. Conf. on X-ray detectors for synchrotron radiation, Nucl. Instr. and Meth. 201 (1982). [2] H. Hashizume and T. Osawa, J. Cryst. Soc. Japan 24 (1983) 312. [3] H. Hashizume, T. Ogawa and Y. Iitaka, to be published in X-ray instrumentation for photon factory (KTK Science/D. Reidel, Tokyo). [4] T. Ogawa and H. Hashizume, Rept. Res. Lab. Eng. Mat., Tokyo Inst. Tech. 9 (1984) 41.
[5] Am2900 Family 1983 Data Book, Bipolar Microprocessor Logic and Interface, Advanced Micro Devices lnc. (901 Thompson Place, P.O. Box 453, Sunnyvale, Cal. 94086, USA). [6] H. Hashizume, K. Mase, Y. Amemiya and K. Kohra, Nucl. Instr. and Meth. 152 (1978) 199. [7] Y. Amemiya and H. Hashizume, J. Fac. Eng. Univ. Tokyo 35 (1979) 313. [8] Y. Amemiya, H. Sugi and H. Hashizume, in Cross-bridge mechanism in muscle contraction (University of Tokyo Press, Tokyo, 1979) p. 425. [9] H. Hashizume, K. Wakabayashi, Y. Amemiya, T. Harnanaka, T. Wakabayashi, T. Matsushita, T. Ueki, Y. Hiiragi, Y. Izumi and H. Tagawa, KEK Internal Report 81-11 (March 1982). [10] Y. Amemiya, K. Wakabayashi, T. Hamanaka, T. Wakabayashi, T. Matsushita and H. Hashizume, Nucl. Instr. and Meth. 208 (1983) 471. [11] K. Wakabayashi, T. Hamanaka, Y. Amemiya, H. Tanaka, T. Wakabayashi and H. Hashizume, Photon Factory Activity Report, 1982/1983, p. VI-88.
335
A MICROPROGRAMMABLE HIGH-SPEED DATA COLLECTION SYSTEM FOR POSITION SENSITIVE X-RAY DETECTORS H. H A S H I Z U M E
Research Laboratory of Engineering Materials, Tokyo Institute of Technology, Nagatsuta, Midori-ku, Yokohama 227, Japan Y. I I T A K A
Faculty of Pharmaceutical Sciences, University of Tokyo, Hongo, Bunkyo- ku, Tokyo 113, Japan r
T. O G A W A
Tri-C corporation, Dai-ichi Fuyo Bldg, 2-4-6 Mita, Meguro-ku, Tokyo 153, Japan Received 31 January 1984
A high-speed data acquisition system has been designed which collects digital data from one- and two-dimensional position sensitive X-ray detectors at a maximum average data rate of 1 MHz. The system consists of two separate fast buffer memories, a 64K word by 20-bit main storage, two timers, a display controller, a computer interface and a keyboard, controlled by a specially designed microprogrammable microprocessor. Data collection is performed by executing a microprogram stored in the control storage; data coming from a detector are first accumulated in a small but fast buffer memory by hardware and transferred to the main storage under control of the microprogram. This design not only permits time-resolved data collections but also provides maximum speed, flexibility and cost-effectiveness simultaneously. The system also accepts data from integrating detectors such as TV cameras. The system has been designed for use in experiments at conventional and synchrotron X-ray sources.
1. Introduction As hard X-rays from synchrotron light sources find a wide variety of applications, it becomes more evident that their characteristic high photon flux is fully usable only in experiments with fast detectors. Various approaches are thus being made to develop fast position sensitive detectors. Such detectors are most useful in time-resolved experiments, where many time frames of a diffraction diagram are recorded from a sample under rapid structural changes to millisecond frame resolutions; data collection is usually performed by detecting X-ray photons with a position sensitive counter and accumulating this information at separate locations in a digital store in synchronization with changes of the sample enviroment. The speed of various non-integrating position sensitive detectors depends on the two times: the time needed for the detector to derive a digitized coordinate of a detected event and the time spent in processing and storing this information in the associated data collection system. Since these times add to limit the high-count rate capability of a particular system, the latter time need be kept negligibly short as compared with the former time. Each synchrotron radiation facility has developed its 0167-5087/84/$03.00 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)
own data collection system [1]. A project was organized in 1979 to develop instrumentation for the Photon Factory, where priority was given to various attempts to build fast position sensitive detectors. The present paper describes a digital data collection system designed to support such detectors. The system has been reported in greater detail in the project reports [2,3] and elsewhere [4].
2. Design considerations In view of the present detector technology, we assume 1 MHz as a maximum average data rate that should be accommodated by our digital system. To meet this goal, a single event needs to be processed and recorded in less than a few 100 ns. This requires a memory system completing a read-modify-write cycle in a similar time or less at random addresses. In the meantime, a typical time-resolved experiment records 16 to 64 one-dimensional diagrams each containing 256 data. A practical wire-chamber area detector provides 64 × 64 to 256 × 256 resolution elements, requiring 4K to 64K memory words. The memory size requirement is further increased by a factor of, say, 16, if two-dimensional diagrams are to be recorded in time resolution.
336
H. Hashizume et al. / Microprograrnmable high -speed data collection system
Each word must be at least 20-bits long to minimize overflows that can occur in high data-rate applications. Thus, we need a fast, large and inexpensive memory system. When extremely high data rates over 1 M H z are anticipated, integrating detectors such as TV cameras and photodiode arrays are potentially useful; such detectors are able to store event information on the detection surface and practically have no dead time. The outputs are in the form of video signal produced in synchronization with external readout signals; the video amplitude is related in some way to the number of photons absorbed in each pixel during the readout period. A standard TV picture contains useful - 480 × 480 pixels scanned in 1 / 3 0 s. After digitization, sequential data at a regular rate of - 7 M H z are generated. It is desirable that the data collection system also accepts such data. The system needs to be highly flexible. Two modes of data collection, normal and time-resolved, should be selectable. In the latter time frame durations are desirably adjustable on a frame-by-frame base. At the start of each data collection, the system should generate a timing signal that can be used to trigger environmental conditioners for the sample. Although good bi-directional communications with a data processing computer are essential, it is advantageous that the system works also as a self-complete machine and collects data without control by the computer.
3. System architecture Fig. 1 shows the hardware architecture of our system. The system can be simply described as consisting
of four major units: a control microprocessor, two separate buffer memories and a 64K word by 20-bit main memory, connected together by an address bus and a data bus, each 20-bit wide. This design is based on the philosophy that maximum speed, flexibility and cost-effectiveness are provided simultaneously when we employ a small but fast buffer memory to accumulate data from a position-sensitive counter and transfer the buffer content at programmed points to a large main store under control of a microprogram. A difference between one- and two-dimensional counters is the bit length of output data. While data (i.e., event addresses) out from one-dimensional detectors are normally 8- or 9-bit long, two-dimensional detectors produce 12- to 16-bit data depending on the detector size. This difference affects the optimum designs of high-speed buffer memories. Thus, our system includes two separate buffers, a cache memory and a scaling memory followed by a derandomizing memory, intended for use with one- and two-dimensional position sensitive counters respectively. The cache memory and the scaling memory receive data via separate cable connectors on the rear panel of the chassis. Data coming from a detector are first accumulated in the selected buffer memory by hardware. At programmed points of data collection, a microprogram makes access to the active buffer and the main memory; the contents at specified memory addresses are read and subject to manipulation as dictated by the microprogram. The result is directed to the main memory and stored at specified addresses. The cache memory and the derandomizing memory have a double buffer structure; while one buffer is being read by a microprogram, an alternate buffer accepts data from the detector. This allows data collection without interruption.
MICROPROCESSOR ..~ A/D
[--DATABUS (20)
<~
ADDRESSBUS (29)--.
I COMPUTERI Fig. 1. General block diagram of the data collection system.
q
BUS
>
1 ->
H. Hashizume et al. / Microprogrammable high-speed data collection system
The microprocessor is the brain of the system. It controls the system hardware to collect data from external detectors and to display the accumulated data on a CRT screen. Further, it handles communications with the host computer to send and receive data. All these tasks are carried out by executing a microprogram stored in microprogram memory. Our processor includes three PROMs, which store microprograms developed for experiments employing the cache memory, the scaling memory and TV-type detectors. These microprograms are made available alternatively by front-panel switches. Fig. 1 shows two timers, a video data input unit, a CRT display controller, a computer interface and a keyboard tied by the bus lines. These devices form independent logical units and can be the source a n d / o r destination of data transfer by microprograms. The hardware specifications of the various components are given in table 1. The system is built on eighteen 220 x 270 mm 2 wire-wrap cards housed in four chassis mounted on a standard rack. Photographs of the complete system are shown in figs. 2a and b.
337
Am2910 microprogram controller, condition-code multiplexer, vector map ROM and priority interrupt controller. The scratchpad memory is a 16-word by 20-bit memory usable as general-purpose registers. A special design of this memory is that each word is accessible by parameter keys on the system's keyboard; key operations allow the content of the selected word to be displayed and modified to a new value. The scratchpad memory is normally used to hold parameters for timeresolved data collection and post-experiment display. The former parameters can also be given from the host computer. The BCD-to-binary converter is to save microprogram words in decoding a given parameter.
4. Control processor 4.1. Microprocessor design
The control processor is built around Advanced Micro Devices Am2901B bit-slice microprogrammable microprocessors. The Am2901B is a 4-bit microprocessor slice containing a high-speed ALU and a 16-word by 4-bit two-port RAM [5]. We cascade five of this device to form a 20-bit ALU (see fig. 3). The processor includes a microsequencer, four alternatively usable microprogram memories, a pipeline register, a scratchpad memory, a define-constant register and a BCD-to-binary converter. Three of the microprogram memories are PROMs as mentioned earlier, while the remaining one is a writable control storage capable of loading any microprogram from the host computer as well as from the system's panel switches. Each microprogram memory has 512 address locations to hold various microinstructions. A microinstruction word is 44-bit long, where some bits control the hardware of the system, while others define the location in the microprogram memory of the next microinstruction to be executed. Microinstructions are fetched word by word to the pipeline register under control of the microsequencer, and executed by the machine. While the current microinstruction is held at the pipeline register, the next microinstruction is being fetched and set up at the inputs to the pipeline register. Overlapped fetching and execution doubles the system throughput as compared with a non-pipelined design; the basic machine cycle time is 200 ns in our system. Fig. 3 shows that the microsequencer uses such units as
Fig. 2a. Appearance of the data collection system. From top to bottom, main controller, display panel, keyboard, microprogrammer's panel and power supply.
338
H. Hashizume et al. / Mtcroprogrammable hzgh-speed data collectton ~ystem
Fig. 2b. Layout of the keyboard. Function keys on the top row, parameter-key matrix on the left, digital switches and data entry key in the center, display control keys, rotary encoder and potentiometers on the right.
Table 1 Hardware specifications of the system Power Physical dimension Unit process time Control Microprogram memory Data length ALU functions General purpose register Cache memory Scaling memory Derandom memory Main memory Video data input unit Timers Display control Computer interface
Keyboard
Other functions
ac 100 V / 5 0 - 6 0 Hz, approx. 500 VA 530 X 650 x 1660 mm 3 200 n s / s t e p pipeline control by microprogramming ROM: 512 W (44 bits)X3, WCS: 512 W (44 bits) 20 b i t s / w o r d R + S , S , R , R - S , R v S , RA S,P, AS, R'~'S, R v S, left and right shift 32 registers/20 bits 512 W / 1 6 bits x 2, access time: 20 ns 64 K W / 3 bits, access time: 55 ns 1 K W / 1 6 bits x 2, access time: 70 ns 64 K W / 2 0 bits or 16 K W / 8 0 bits, access time: 70 ns video amp., discriminators, ADC 8 bits/50 ns, buffer registers, 80-bit full adder 1 ms timer and 1 s timer (BCD 5 digids) CRT monitor: X-axis 8 bits, Y-axis 8 bits, Z-axis 4 bits digital I / O : program cont. oh. 16 lines multiplexer cont. ch. 16 lines interrupt: 4 fines 7 function keys, 16 parameter keys, 5 digit data entry switches, 5 display control keys, 7 potentiometers, LED displays BCD-to-binary converter, BCD up-down counter, display panel, microprogrammer's panel
339
H. Hashizume et al. / Microprogrammable high-speed data collection system
>
DATA BUS (20)
BCO-TO-BINARY • CONVERTER
0.
I 12 /
=l~Am2910/
A L U
! /
0
17,
12
/ I I
~E~OR~
~l CLOCK [ - I PANEL SW. I CONTROLLER , ADOR,SYNC
I-I
"4
/ '-'1 P,~E',NE R~O,ST~RI I INTERRUPT / REOUEST I INTEFRUPT I
4 8 RAM A.B
INTERNAL CONDCTION
EXTERNAL CONDITION
0n-4 OVR F3 F=O
10 SOURCE,FUNO, OEST.,On
~"
>
CONTROL BUS
SOU REOUEST
<
~_>
ADDRESS BUS {20)
<
Fig. 3. Microprocessor block diagram.
Sequence Control field Format AL.U
BR
format
format
F'ormat Control code (binary)
0 1 2 3
7 8
Bus Control field
FormatControl held
ALU field
11 12
1516
2021
2324
26
Memory Address Increment field 0 1 2 3 7 8 11 12
1516
2021
2324
26
0 1 2 3
15 16
2021
2324
26 27
28
30313233
3536
3940
43
0
32
43
0
BHL1
format
1
BHL.2
format
2
7 8
7 8
3
Mask
format
4
SPM
format
6
11 12
1516
2021
2324
I
2627
43 Bit Handling
0 1 2 3 format
43 Bit Handling
0 1 2 3
DC
11 12
7 8
I1 12
0
1 2 3
0 1 2 3
Fig. 4. Microinstruction formats.
2021
2324
i,s.s I ,s.o
oo.o
IMAI ~0NO COND
1516
7 8
I 7 8
11 12
MSi
15 16
BUS-S [ 11 12
15 16
2627
43
o I 2021
BUS-D
2324
FORMATI
2021
2324
I
26
D
[ ~ 26
Oe,.oeOons,n,
I
2g
43
Interrupt Mask
I 40
43
340
H. Hashizume et al. / Microprogrammable high-speed data collection system
4. 2. Microprogramming
Fig. 4 depicts seven formats defined to organize the microinstructions. These are the A L U , BR, BHL1, BHL2, DC, Mask a n d SPM formats. All the formats are 44-bit wide a n d use identical field definitions in the left 27 bits. Here we define such fields as M e m o r y Address I n c r e m e n t field, Sequence Control field, Bus Control field, F o r m a t C o n t r o l field a n d A L U - D field. The purpose of the M A I field is to i n c r e m e n t m e m o r y address counters without d e p e n d i n g on the A L U operation. This allows these two operations to occur in the same microinstruction, thereby permitting developing efficient micro-routines for block d a t a transfer between memories. The Sequence Control field consists of the C C E N , C O N D a n d MSI fields, which determine the address of the next microinstruction to be executed; the MSI field selects one of the 16 different sequence control instructions for the Am2910 m i c r o p r o g r a m controller [5], while the C C E N and C O N D fields furnish test conditions for c o n d i t i o n a l instructions. The Am2910 provides powerful conditional instructions for branching to various m i c r o p r o g r a m sequences d e p e n d i n g upon test condition inputs. A m i c r o p r o g r a m is organized to execute tests on various inputs waiting for the condition to come true. W h e n the true condition is reached, the m a c h i n e b r a n c h e s a n d executes a set of microinstructions. Test conditions defined in our system include not only the A L U status (i.e. internal conditions) but also various flags representing the system status (i.e. external conditions): interrupts requested, buffer full, zeros in the timers a n d counters, enabled function keys a n d display keys, h a n d s h a k e signals in the I / O channels of the host computer, etc. The Bus Control field is to specify the source a n d d e s t i n a t i o n for data transfer o n the bus as well as the direct data source for some A L U operations. T a b l e 2 lists sources a n d destinations defined. It will be seen that various memories, registers, counters a n d timers are coupled to the address bus or the data bus. To select one of the seven formats, we code binary n u m b e r s in the 3-bit wide F O R M A T field. Fig. 4 shows that when this n u m b e r is a zero, two formats A L U a n d BR are selected simultaneously. To identify the BR f o r m a t a binary 1 is coded in the A L U - D field, which indicates N o O p e r a t i o n in the A L U format. A l t h o u g h we d o not go into the details of the A L U format, it is pointed out that this f o r m a t (and hardware) is designed to support all of the functions available with the Am2901B [5]. The B R f o r m a t is defined to provide the ability to b r a n c h to a desired m i c r o p r o g r a m address with reference to direct data. This f o r m a t is also used with some sequence control instructions involving a load-counter operation; such instructions are often used to set up a loop in the microprogram.
Table 2 Sources and destinations for data transfer on the bus lines BUS-S HXD Code
6 7 8 9 A B
C D E
NOP Enable ALU data source Enable ALU address source Enable 0 - F switch address source Enable scratchpad memory data source Enable cache memory data source (clear after read) Enable main memory data source Enable define constant data source Enable up/down counter data source Enable T1 timer data source (ms unit) Enable T2 timer data source (s unit) Enable CPU digital output register data source Enable digital switch data source Enable display marker data source Enable scaling memory data source and increment address counter (read only) Enable derandom memory data source and increment address counter (clear after read)
BUS-D HXD Code
9 A B
C D E F 10 11 12 13 14 15 16 17 18 19
NOP HALT Store scratchpad memory address register Store cache memory address register Store main memory address register Store scratchpad memory Store cache memory Store main memory Store define constant register (for BCD to binary answer) Store BCD-to-binary converter Store up/down counter Store T1 timer (ms unit) Store T2 timer (s unit) Store display X-axis register Store display Y-axis register Store display Z-axis register Store CPU digital input register Store keyboard display register Store panel display register 1 (TO) Store panel display register 2 (NO) Store panel display register 3 (not used) Store panel display register 4 (not used) Store compare address register Y1 Store compare address register Y2 Store zero in scaling memory and increment address counter Store zero in derandom memory and increment address counter
341
H. Hashizume et al. / Microprogrammable high-speed data collection system
In order that the processor be able to exert selective control on various elements, two bit-handling formats, BHL1 and BHL2, have been defined, each accomodating up to 17 operations. Each bit of the Bit Handling field is associated with a specific operation, and a logic 1 at a particular bit position asserts that operation. The BHL1 includes such operations as start T 1 / T 2 timers, couple/decouple the CRT X, Y, Z-axis registers with the data bus, reset flags, reset interrupt requests, generate interrupt request to the host computer, etc. The BHL2 contains such operations as generate handshake signals in the I / O channels of the computer, o n / o f f buzzer, start/stop data collection in the cache or scaling memory, alter the cache memory connection, reset address counters of the scaling memory and the derandomizing memory, etc. The bit-oriented assignment has the advantage that two or more operations can be directed simultaneously. To take this advantage, we have carefully distributed the various operations to BHL1 and BHL2. The DC, Mask and SPM formats refer to the direct data contained in the microprogram word. The DC format serves to load any value less than 217 - 1 into the define constant register. As noted earlier, the scratchpad memory is designed so that the parameter keys can play on the memory content. This memory has another feature that it is addressabl e by a single microinstruction. This is done by employing the SPM format, where a desired memory address is specified in the SPM Address field occupying bit 40 through 43. The scratchpad memory can also be addressed via the address bus. This takes, however, at least two microinstructions. One of the Am2910 instructions C O N D I T I O N A L
J U M P VECTOR provides the capability of performing interrupt-type branching at the microprogram level. Our system utilizes this capability to handle commands given to the system from the host computer or the system's function keys. Table 3 lists fifteen events that generate interrupt requests. With each event is associated an interrupt level of a fixed priority. The Mask format is defined to selectively inhibit interrupt requests by program. Bits in the Mask field are oriented to individual interrupts in the descending priority order from the MSB to LSB. We have devoted microprogram word address 1 through 15 to the vector area. From the microword structure described above, it will be seen that a single microinstruction can perform three independent controls simultaneously besides the next address control: memory address increment, data transfer on the bus and a specific control directed by the format. This allows data collection programs to be written in minimum microinstruction counts, which has the effect of improving the system throughput.
5. Buffer memories 5.1. Cache memory
The cache memory consists of two equivalent 512word by 16-bit memories, which form a double buffer for data acquisition (see fig. 5). Each memory is built using ECL memories of 20 ns access time. All address and control signals are TTL levels and routed to the active memory through the 50-pin rear panel Amphenol connector; the control signals use a negative logic. We
Table 3 Microprogram interrupts Abbreviation ")
Name
Event source
Vector address
Priority
ERR 1 ERR 2 TOUT * SCLR * STOP * MCLR * START * SADDR
Error 1 Error 2 Time out 1 s System Clear Stop Data Collection Memory Clear Start Data Collection Set Top Memory Address for Data Transfer Set Data Length for Data Transfer Set Parameter Read Main Memory Write Main Memory Display Main Memory Content Load Parameter from Digital S w i t c h Access to Scratchpad Memory at the Address Specified by 0-F Switch
System System System Keyboard/Host CPU Keyboard/Host CPU Keyboard/Host CPU Keyboard/Host CPU Host CPU
1 2 3 4 5 6 7 8
(High)
Host CPU Host CPU Host CPU Host CPU Keyboard Keyboard Keyboard
9 A B C D E F
* SDLEN * SPARA * RMEMO * WMEMO * DISP * LDSW 0FSW
a) Events marked with * are system commands.
(Low)
H. Hashizume et al. / Microprogrammable high- speed data collection system
342 <
DATA BDS (20)
d--ADDRESS BUS ~20~
3
r.
.
.
.
BUFFER I
~EOISTER
J
E
I
BLS Ta'ANCENEN
~
20
MEMORY SELECTOr':
i -4 80
V!OEO L~,"
I
VIDEO
MAIN MEMORY
UNff /9
I DETECTORINTERFACEI DATA
DRDY
AGK
Fig. 5. Block diagram of the cache memory and the main memory.
employ a very simple control scheme of data-ready/acknowledge type. When the external device (i.e., the position encoding electronics associated with the position sensitive counter) is ready to write data, it asserts D R D Y with the address data set up not later than 15 ns after the high-to-low transition of the D R D Y signal. Then, the active memory is incremented by hardware at the address presented in 100 ns. At the completion of the increment cycle, the memory returns the A C K signal, which can be used to initiate a next encoding cycle in the external device. The two cache memories, CM1 and CM2, are alternatively connected to either the external device or the system data bus. This connection is controlled by bithandling instructions. In one configuration, CM1 accumulates data from the detector while CM2 is read by a microprogram. In time-resolved experiments, timer T1 is loaded with a frame time and the memory connections are interchanged when condition T1 = 0 is reached. N o w CM2 is allowed to collect data for the next frame with timer T1 loaded with the next frame time. Simultaneously, CM1 is made available to the microprogram; a set of microinstructions read and add the contents of CM1 to those of the main memory, whereby the origin of the data array is shifted by a multiple of 512 (or any number). To reduce the microinstruction
count, a special microcode is provided to clear the cache memory after each read (see table 2). This used in conjuction with a Memory Address Increment code allows to transfer the array of 512 data into the main memory in about 410/~s. At the completion of the data transfer, the accessed cache memory is automatically cleared and ready for data collection of the next frame. 5.2. Scaling memory and derandomizing memory
The data buffer for two-dimensional position sensitive counters consists of the scaling memory and the derandomizing memory (fig. 6). We assume that for each detected event the detector electronics processes a pair of (x, y ) coordinates to deliver a linear address. The address and control signals are furnished at the inputs to the buffer register via a 50-pin chassis-mounted connector. The scaling memory is a 64K word by 3-bit memory constructed from MOS memories of 55 ns access time. It uses control and timing schemes similar to those employed in the cache memory; on negative transition of the ~ signal, the address is latched into the buffer register and a hardware sequence is initiated in the scaling memory to increment the content at the address presented in 120 ns. The scaling memory works like an array of 1 / 8 scalers associated with
H. Hashizume et aL / Microprogrammable high-speed data collection system
<
DATA
BUS
fl DATA
343
I
BUFFER
fl
MUX
fl ADD
SM I DOUNTER ADDRESS
¢
~ ~AN~ :SS
I INCREMENTER DARRY DETECTOR
SELECTOR
&
¢
'~
ADD~ESS
fl SMDM I CONTROLLER f] BUS OONTROL
Fig. 6. Functional block diagram of the scaling memory and the derandomizing memory.
individual 64K (or less) resolution elements i n the two-dimensional detector. The overflows that occur when a memory word counts eight events are watched by the carry detector. Whenever a carry is detected, the SMDM controller issues a write enable signal, which makes the address latched in the buffer register pushed into the derandomizing memory. This push is completed in 70 ns and the associated DM address counter is incremented by hardware. The derandomizing memory uses two equivalent 16bit wide, 1K word deep first-in/first-out (FIFO) buffers, DM1 and DM2, alternatively connected to either the buffer register or the system data bus. The connections of DM1 and DM2 are initialized by a microinstruction and interchanged by hardware when 1024 data are pushed into the active buffer. Full data entry is flagged. A microprogram is then organized to repeat a test on condition Buffer Full;" when the test is passed, the DM address counter is reset to sequentially transfer the buffer content to the address counter of the main memDry. A special microcode (see table 2) allows to clear the derandomizing memory after each read and increment the associated address counter in a single execution cycle. The next mieroinstructions read the main memory, add eight to the content, restore the new value at the same address. These whole operations can be performed in a four-instruction loop. It takes then four microsteps, i.e. 800 ns, to transfer a record in the derandomizing memory to the main memory. Since one record in the derandomizing memory represents eight counts in the scaling memory, the system hardly suffers from a rate problem at an incoming data rate of 1 MHz. At the cessation of a data collection, the scaling memory and the derandomizing memory are read by a microprogram and the existing data are added into the main memory. The system also allows to collect two-di-
mensional data in time resolution unless the total number of recorded data exceeds 64K.
6. Main memory and video data input unit The main memory uses stati~ RAMs (access time 70 ns) assembled in four banks. Each bank has a capacity of 16K words/20 bits for a total of 64K words/20 bits. In addition to the I / O port interfacing to the system bus, the memory has a port to read and write 80-bit words. This port is used to store video data in a reduced effective cycle time for sequential accesses. The video unit in fig. 1 includes a fast 8-bit ADC, double buffer registers and a 80-bit full adder; four consecutive ADC outputs are arranged into a 80-bit word and added to the content of the corresponding memory location by hardware. This allows the video signal to be digitized and recorded at a standard TV scanning rate. To .......accommodate an entire TV picture in the main memory, the video unit is programmed to sample 256 data points on a scanning line, and data for odd and even picture fields are'added: After a ~ven.number of picture frames are thus integrated, the main memory is read by microprograms in words of 20 bits via the bus.
7. Data-collection program The data collection system described above is very flexible because of its programmable design. The system can be adapted by microprograms to a wide assortment of experimental conditions and requirements. Microprograms can be assembled on the control computer and directly loaded down to the writable control storage of the system. To facilitate microprogram development, we
344
H. Hashizume et al. / Microprogrammable high -speed data collection system
have organized our own microprogram assembler, which allows microinstructions to be represented in mnemonics. The assembler has an error checking capability and compiles symbolic statements to produce bit patterns (i.e. the object program) on the disc of the control computer. An IPL program transfers thus created microprograms to the WCS. The system can also be operated by one of three internal microprograms stored in the ROMs; a front panel toggle switch allows to select the WCS or R O M for the microprogram source. The internal microprograms are of general-purpose nature, designed for data collection employing different classes of detector (see sect. 3). The following paragraphs describe one such microprogram. This microprogram has a modular structure with each module executable by a system c o m m a n d (see table 3). It also includes a power-up routine beginning at microprogram memory address 0 to initialize the system. Two options, on-line and off-line, are selectable by the function key on the keyboard (see fig. 2). Depending on the option selected, the microprogram accepts all commands and parameters from either the control computer or the system keyboard. The data collection module is designed to collect data from a linear position sensitive counter delivering 9-bit addresses to the cache memory. There are two modes of data collection: normal and time-resolved. Either mode should be preselected by the function key. Fig. 7 shows a timing diagram for the time-resolved mode. We can use four different frame times T 1 through T4 with respective repetition numbers N l through N 4. T 1 to T4 can be any value between 0 and 99999 ms, while N 1 to
START
N 4 can be 1-99999. Values for these parameters must be
given prior to data collection. The microprogram checks if 1 < N l + N2 + N3 + N4 ~ 1 2 8 and O < T I N I +- "~ N2 + 7 ~ N 3 + T 4 N 4 ~ To, and gives a warning by buzzer and alarm light for invalid parameters. Data collection is initiated on S T A R T command. The microprogram first clears both the cache memory and the main memory and then opens the gate to admit data into the cache memory. Simultaneously, a TTL-level pulse of 1 ~s duration is provided on a B N C connector, which is used to trigger enviroment conditioners for the sample. An arbitrary delay can be placed between pulse generation and data collection, if necessary. During data collection, the microprogram samples incoming data every 1 /~s to display the current contents of the active cache memory on the C R T screen. Whenever the frame time expires, the microprogram switches the cache memories and adds the accumulated data to the contents of corresponding locations in the main memory. At the completion of one data collection cycle, the gate is closed to resume the next cycle after a period T0. The course of experiment is indicated by front panel five-digid counters displaying current values of TO and N o . When NO cycles of data collection are completed and if the on-line option is selected, the microprogram generates an interrupt to the computer, which is normally answered by a task to read the main memory. The display module is designed to work on manual operation of the display keys on the keyboard (see fig. 2). A histogram of accumulated data for any desired frame is shown on a C R T screen on entry of frame number from the digital switches. A display marker is driven to a point of interest on a histogram by opera-
r-[
MEMORY CLEAR J
I
GATE ON TRIGGER SIGNAL
1
I
2
No
FI
I1 NI
N2
N3 N4
NI
N2
N3
IIII IIIIIII CPU INTERRUPT I
TI
T2
T3
T4
PARAMETER I TRANSFER
DISPLAY
Fig. 7. Timing diagram for time-resolved data collection.
N4
1!1
NI
N2
N3 N4
I"" "'1"'1'"[ MEMORY OATA TRANSFER
I I ........
I
H. Hashizume et a L / Microprogrammable high-speed data collection system
345
,,¢
._I I..I.I Z Z ,< --rU~ ~. ~;)_
Z 0 U
0
4'o
'
8'o
'
16o
CHANNEL NUMBER Fig. 8. Time-resolved equatorial diffraction diagrams recorded from stimulated and stretched muscle. A frog sartorius muscle on a small-angle camera was stimulated for 3.5 s by a pulse train and stretched slowly 1 s after the onset of the stimulation. Data were accumulated from five stimulations and stretches at 0.5 s frame resolution. Left halves of the diagrams are masked for clarity. From left to right on each diagram, background scattering peak, the 1,0 reflection and the 1,1 reflection. Note the intensity changes of the reflections in response to the stimulation and stretch.
tion of the ~utary encoder to exhibit the channel number and recorded count on LED displays. It is also possible to display a region of interest in a magnified horizontal scale. Also, histograms of any selected two frames can be shown simultaneously for quick visual comparison. Fig. 8 shows an example of data recorded from live frog muscle actively contracting on a small-angle camera. The diffracted X-rays were detected with a laboratorymade linear proportional counter using a 800 ns delay line for readout and a T A C - A D C combination for position encoding [6-8]. The average count rate was - 10 kHz at a rotating-anode X-ray generator. A more critical test of the system will be made at Beam Line 15A of the Photon Factory, where a fast linear detector has been built as a part of a small-angle diffractometer [9-11].
8. Communications with computer The data collection system is interfaced to a MELCOM 70-30 minicomputer, which was originally thought to be the control computer for BL-15A of the Photon Factory. The computer interface of our system is compatible with communication features of a parallel
I / O port of the MELCOM 70-30. This port provides four data channels and four interrupt control lines; two of the data channels are program controlled, while the other two are multiplexer controlled. Each data channel has 16 parallel unidirectional data lines. Communications are handled by a microprogram at one end and by a control program at the other end. Powerful subroutines provided by the Real Time System Package allow the control program to be written in a FORTRAN language. The control program transmits commands and reads the device status word over the program control channels. The multiplexer channels of the MELCOM 70-30 permit block data transfer at a rate of 20K words/s. Through these channels, the control program transfers parameters, sends and receives memory data and dumps a microprogram onto the system WCS. To read or write the system main memory, the program first specifies the top memory address and the data length to be transferred. Since the MELCOM 70-30 is a 16-bit machine, one memory data in the system takes two computer memory words. Similarly, three computer words are spent to represent a microinstruction for the system. The current version of the Real Time System Package allows to transfer a data block of 256 to 32768 words in a single subroutine call. This does not, however, interfere with. the need to read/write a large data block in a short time.
346
H. Hashizume et al. / Microprogrammable high -speed data collection svstem
W e t h a n k M. Ogawa for his helps in developing the m i c r o p r o g r a m assembler. The data shown in fig. 8 were collected in collaboration with Drs. H. T a n a k a a n d T. T a m e y a s u from Teikyo University. We also appreciate interest a n d support from Prof. S. Hosoya, Prof. T. Mitsui a n d Prof. K. Kohra. This work is s u p p o r t e d by a G r a n t from the Ministry for Education, Science a n d Culture.
References
[1] Prec. Int. Conf. on X-ray detectors for synchrotron radiation, Nucl. Instr. and Meth. 201 (1982). [2] H. Hashizume and T. Osawa, J. Cryst. Soc. Japan 24 (1983) 312. [3] H. Hashizume, T. Ogawa and Y. Iitaka, to be published in X-ray instrumentation for photon factory (KTK Science/D. Reidel, Tokyo). [4] T. Ogawa and H. Hashizume, Rept. Res. Lab. Eng. Mat., Tokyo Inst. Tech. 9 (1984) 41.
[5] Am2900 Family 1983 Data Book, Bipolar Microprocessor Logic and Interface, Advanced Micro Devices lnc. (901 Thompson Place, P.O. Box 453, Sunnyvale, Cal. 94086, USA). [6] H. Hashizume, K. Mase, Y. Amemiya and K. Kohra, Nucl. Instr. and Meth. 152 (1978) 199. [7] Y. Amemiya and H. Hashizume, J. Fac. Eng. Univ. Tokyo 35 (1979) 313. [8] Y. Amemiya, H. Sugi and H. Hashizume, in Cross-bridge mechanism in muscle contraction (University of Tokyo Press, Tokyo, 1979) p. 425. [9] H. Hashizume, K. Wakabayashi, Y. Amemiya, T. Harnanaka, T. Wakabayashi, T. Matsushita, T. Ueki, Y. Hiiragi, Y. Izumi and H. Tagawa, KEK Internal Report 81-11 (March 1982). [10] Y. Amemiya, K. Wakabayashi, T. Hamanaka, T. Wakabayashi, T. Matsushita and H. Hashizume, Nucl. Instr. and Meth. 208 (1983) 471. [11] K. Wakabayashi, T. Hamanaka, Y. Amemiya, H. Tanaka, T. Wakabayashi and H. Hashizume, Photon Factory Activity Report, 1982/1983, p. VI-88.