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A multiplex-switch controller
Nuclear Instruments and Methods in Physics Research A302 (1991) 339-341 North-Holland
339
A multiplex-switch controller M. Brendle and K. Schmidt
Physikahsches Institut der Unroersitrit Tübingen, Auf der Morgenstelle 14, D-7400 Tübingen, FRG
Received 28 September 1990 and in revised form 20 November 1990
A multiplex-switch controller for experiments with up to eight counter telescopes is described .
The designer of the electronics for measuring angular distributions with several counter telescopes can provide either a separate set of analog-to-digital converters (ADCs) for each telescope, connected to the data acquiring computer via a digital multiplexer, or he can connect all telescopes to a common set of ADCs via an analog multiplexer . The first option allows to digitize events of several telescopes simultaneously . So higher counting rates can be accepted . In the second case, much less ADCs are needed . Therefore, the use of faster and more expensive ADCs can be justified . So the speed argument for the multi-ADC solution becomes less significant . The analog multiplexer solution has a true advantage : in such a system, the relative dead-time losses of all channels tend to be equal, whereas in a digital multiplexer system they do not . The analog multiplexer of the second option is made up of some linear gates and summing amplifiers . It must be controlled by coincidence signals from the individual telescopes . Gate signals for the individual channels of the analog multiplexer, gate signals for the ADCs, a composite dead-time signal, and the binary encoded number of the channel number must be produced . The controller to be described here generates those signals from the individual coincidence signals and from the dead-time signals of up to four ADCs . The channel number can be read out on a 16-bit wide bus. A similar instrument has been developed by one of the authors before [1] . Since then, much better components have become available. Due to that, the new controller is more than an order of magnitude smaller, less expensive, and generates much less heat. A block diagram of the multiplex switch controller is shown in fig. 1 . The channel request (coincidence) input signals INO, INI, . . . , IN7 are level-translated from NIM fastnegative-logic (FNL) levels to TTL levels . A channel flipflop is provided for each channel request input . A
low going edge of an input signal will set the corresponding flipflop, if an external enable signal EN is active and if the controller is not busy . The channel arbiter will inhibit all other channels, when one flipflop has been set or when the controller is busy. When a channel flipflop has been set, a dead-time signal MPBUSY (MultiPlexer is BUSY) is activated . Shortly after that, the signal GATE becomes active . It activates the gate output Gi for the active channel and four gate signals ADCO, ADC1, ADC2, and ADC3 for triggering ADCs . At the same time, it triggers a delay generator . During the gate time, one or several ADCs will become busy . The internal GATE signal and the ADC gate signals will end, when the delay generator output pulse CLR will become active . After the end of the gate interval, the binary coded channel number is written into the three least significant bits, 0, 1, and 2 of the 16-bit output register by the leading edge of CLR . Simultaneously, a switch-selectable module identification number is written into the three most significant bits, 13, 14, and 15 of the same register. The remaining 10 bits can be used for routing data : the controller contains 10 routing flipflps . If any of the 10 routing signals, X0, XI, . . . ' X9 are active continuously or for any short time interval during the gate time, then the corresponding routing flipflop is set . After the end of the gate interval, the flipflop states are written into bits 3 to 12 of the output register . When the output register is loaded, a flag OUTPUTBUSY indicating the output register to be full is set . The output control logic demands access to the output bus, and when it has got it, it transmits its data word . Then OUTPUTBUSY becomes passive again . The output bus is an asynchronous bus conforming to a protocol created by LeCroy Corp . for its 3510 series of CAMAC spectroscopy ADCs [2] . When the ADCs have finished their conversions, and when they have been read out, then their ADCiBUSY (i = 0, 1, 2, 3) signals become passive, too. The delay
0168-9002/91/$03 .50 © 1991 - Elsevier Science Publishers B .V. (North-Holland)
340
M. Brendle, K. Schmidt / A multiplex-switch controller B nary Coded Channel Number
N N L EL w _a > 4 L d47 - N li N _ ;, 0U C N t GL U O
INO INI I N2 IN3 IN4 INS INS IN7
N â
N N C f
GB G1 G2 C3 04 G5 GG C7
L m 0 U C W L
ADCOBUSY ADCIBUSY ADC28USY ADC3BUSY
-
_N m
â~
OUTPUTBUSY
M -
& O rN m m
a âz-
GATE
J J J C ..
CLR
X0 X1 X2 X3 X4 X5 XB X7
N
,o 0
N L L
L 4
N>
ut
N L m m Y
C Cm _ J L 0 0 N
XB X9
O N 7 Nm
GATE
o
J
J J a v O
N C m r U
O
m
O
EN ADCO ADC1 ADC2 ADC3
°' N N L U >W
GATE
U L a
Fig. 1 . Block diagram of the controller .
s
ISO
VCC
8N 74F74
100
INO
14HC240
4
1
VCC
10E 74HCTOO
IAI 1Y1 1A2 1Y2 IA3 IY3 l A4 I Y4 QUAD BUFFER/ LINE DRIVER
3
SI
S2
VCC
VCC
4xiBO GO
-SV
ON EN CIN C2N C3N C4N CSN CSN C7N CLR
CON
EMMEEMsenomma
A B C D E F G H I
1Y 2Y 3Y 4Y SY SY 7Y BY
CLRIN CLRLIN CLR3N CLR4N CLRSN CLRSN CLRIN
~MMEM MMMMMw
1111111 MEMNON MEMOS ONES MEN
MEMMEM MMEEM MMEM MENU
I
VCC
MEMNONMEMO
74LS30
oi
l
2
1W
Fig. 2. Level translator, channel flipflop, channel gate, line driver and arbiter circuit.
MPBUSY
CATE
M. Brendle, K. Schmidt / A multiplex-switch controller
generator is reset, CLR becomes passive, MPBUSY becomes passive, and the controller becomes ready to accept the next event. For external dead-time correction circuits, the state of MPBUSY is put out in the form of two +5 V signals MPBUYO and MPBUY1 and an FNL signal MPBUSYFNL. A circuit diagram of a single channel flipflop and the channel arbitration logic is shown in fig. 2. The input signal is level-translated by an inverting Schmitt-trigger made from one half of a fast voltage comparator Signetics NE521. A negative edge of the input signal will set the channel flipflop 1/2 741774, if the active-low channel-clear signal CLRiN is passive. The channel-clear signals CLRi N (i = 0, 1, . . . , 7) are generated by a GAL (Generic Array Logic) circuit Lattice GAL 16V8 [3] according to the equations: CLRiN = (CON and ClN and . . . and C(i - 1)N and C(i + 1)N and . . . and C7N and Not CLR And EN) Or (CON and CIN and . . . and C(i - 1)N and C(i + 1)N and . . . and C7N and Not CLR And Not CiN) . EN is the external enable signal . CLR is the clear signal, activated by the gate generator after the gate interval has expired. From the CLRiN equations one can see, that a channel flipflop is cleared and setting is inhibited as long as any other channel flipflop is in its active state or the common clear signal CLR is active . It can be set, if none of the channel flipflops is on, if the clear signal is passive, indicating that the controller and its ADCs are not busy, and if the external enable signal EN is active . If EN becomes passive, after a channel flipflop has been set, the processing of the current event is not disturbed. A pull-up resistor has been provided on the EN input. So the controller will work, when the enable input is open .
341
When a channel flipflop is set, than the clear signals for all other channel flipflops are activated. This is to prevent that two or more channel flipflops are active at the same time . Nevertheless it is possible, that two or more input signals arriving simultaneously activate two or more channel flipflops at the same time. Although all or all but one of them will be cleared again after a very short time, spikes at the flipflop outputs cannot be excluded completely . Therefore, the NAND gate 74LS30 combining the CiN signals is followed by a spike filter consisting of an RC low pass and a Schmidt-trigger NAND gate 1/4 74LS132 . The delay time between the leading edges of an INi input pulse and the associated Gi output pulse is 150 ns . The delay generator consists of a 10 MHz start/stop oscillator and a counter. The gate time can be chosen between 0.15 and 12 .85 Ws in 0.1 Ws increments . This timer is almost free of recovery effects. The individual channel gate signals GO, Gl, . . . ,and G7, the ADC gate signals, and the BUSY signals MPBUYO and MPBUY1 are generated by drivers able to drive long lines with TTL levels . Such a driver is shown in fig. 2. Its source resistance is about 50 S2 . Thus a 50 9 cable is in series terminated at the source. Even with parallel termination at the far end of the cable, TTL levels are reached. References [1] K. BÖpple and M. Brendle, Nucl. Instr. and Meth. [2]
[3]
(1971) 7.
94
CAMAC Model 3511, 3512, 3514, and 3515 High-Performance Spectroscopy ADC, Manual by LeCroy Corporation, 700 Chestnut Ridge Road, Chestnut Ridge, NY 10977-6499, USA (1984) .
GAL Data Book, Lattice Semiconductor Corporation, 5555 Northeast Moore Court, Hillsboro, Oregon 97124, USA (1990) .
339
A multiplex-switch controller M. Brendle and K. Schmidt
Physikahsches Institut der Unroersitrit Tübingen, Auf der Morgenstelle 14, D-7400 Tübingen, FRG
Received 28 September 1990 and in revised form 20 November 1990
A multiplex-switch controller for experiments with up to eight counter telescopes is described .
The designer of the electronics for measuring angular distributions with several counter telescopes can provide either a separate set of analog-to-digital converters (ADCs) for each telescope, connected to the data acquiring computer via a digital multiplexer, or he can connect all telescopes to a common set of ADCs via an analog multiplexer . The first option allows to digitize events of several telescopes simultaneously . So higher counting rates can be accepted . In the second case, much less ADCs are needed . Therefore, the use of faster and more expensive ADCs can be justified . So the speed argument for the multi-ADC solution becomes less significant . The analog multiplexer solution has a true advantage : in such a system, the relative dead-time losses of all channels tend to be equal, whereas in a digital multiplexer system they do not . The analog multiplexer of the second option is made up of some linear gates and summing amplifiers . It must be controlled by coincidence signals from the individual telescopes . Gate signals for the individual channels of the analog multiplexer, gate signals for the ADCs, a composite dead-time signal, and the binary encoded number of the channel number must be produced . The controller to be described here generates those signals from the individual coincidence signals and from the dead-time signals of up to four ADCs . The channel number can be read out on a 16-bit wide bus. A similar instrument has been developed by one of the authors before [1] . Since then, much better components have become available. Due to that, the new controller is more than an order of magnitude smaller, less expensive, and generates much less heat. A block diagram of the multiplex switch controller is shown in fig. 1 . The channel request (coincidence) input signals INO, INI, . . . , IN7 are level-translated from NIM fastnegative-logic (FNL) levels to TTL levels . A channel flipflop is provided for each channel request input . A
low going edge of an input signal will set the corresponding flipflop, if an external enable signal EN is active and if the controller is not busy . The channel arbiter will inhibit all other channels, when one flipflop has been set or when the controller is busy. When a channel flipflop has been set, a dead-time signal MPBUSY (MultiPlexer is BUSY) is activated . Shortly after that, the signal GATE becomes active . It activates the gate output Gi for the active channel and four gate signals ADCO, ADC1, ADC2, and ADC3 for triggering ADCs . At the same time, it triggers a delay generator . During the gate time, one or several ADCs will become busy . The internal GATE signal and the ADC gate signals will end, when the delay generator output pulse CLR will become active . After the end of the gate interval, the binary coded channel number is written into the three least significant bits, 0, 1, and 2 of the 16-bit output register by the leading edge of CLR . Simultaneously, a switch-selectable module identification number is written into the three most significant bits, 13, 14, and 15 of the same register. The remaining 10 bits can be used for routing data : the controller contains 10 routing flipflps . If any of the 10 routing signals, X0, XI, . . . ' X9 are active continuously or for any short time interval during the gate time, then the corresponding routing flipflop is set . After the end of the gate interval, the flipflop states are written into bits 3 to 12 of the output register . When the output register is loaded, a flag OUTPUTBUSY indicating the output register to be full is set . The output control logic demands access to the output bus, and when it has got it, it transmits its data word . Then OUTPUTBUSY becomes passive again . The output bus is an asynchronous bus conforming to a protocol created by LeCroy Corp . for its 3510 series of CAMAC spectroscopy ADCs [2] . When the ADCs have finished their conversions, and when they have been read out, then their ADCiBUSY (i = 0, 1, 2, 3) signals become passive, too. The delay
0168-9002/91/$03 .50 © 1991 - Elsevier Science Publishers B .V. (North-Holland)
340
M. Brendle, K. Schmidt / A multiplex-switch controller B nary Coded Channel Number
N N L EL w _a > 4 L d47 - N li N _ ;, 0U C N t GL U O
INO INI I N2 IN3 IN4 INS INS IN7
N â
N N C f
GB G1 G2 C3 04 G5 GG C7
L m 0 U C W L
ADCOBUSY ADCIBUSY ADC28USY ADC3BUSY
-
_N m
â~
OUTPUTBUSY
M -
& O rN m m
a âz-
GATE
J J J C ..
CLR
X0 X1 X2 X3 X4 X5 XB X7
N
,o 0
N L L
L 4
N>
ut
N L m m Y
C Cm _ J L 0 0 N
XB X9
O N 7 Nm
GATE
o
J
J J a v O
N C m r U
O
m
O
EN ADCO ADC1 ADC2 ADC3
°' N N L U >W
GATE
U L a
Fig. 1 . Block diagram of the controller .
s
ISO
VCC
8N 74F74
100
INO
14HC240
4
1
VCC
10E 74HCTOO
IAI 1Y1 1A2 1Y2 IA3 IY3 l A4 I Y4 QUAD BUFFER/ LINE DRIVER
3
SI
S2
VCC
VCC
4xiBO GO
-SV
ON EN CIN C2N C3N C4N CSN CSN C7N CLR
CON
EMMEEMsenomma
A B C D E F G H I
1Y 2Y 3Y 4Y SY SY 7Y BY
CLRIN CLRLIN CLR3N CLR4N CLRSN CLRSN CLRIN
~MMEM MMMMMw
1111111 MEMNON MEMOS ONES MEN
MEMMEM MMEEM MMEM MENU
I
VCC
MEMNONMEMO
74LS30
oi
l
2
1W
Fig. 2. Level translator, channel flipflop, channel gate, line driver and arbiter circuit.
MPBUSY
CATE
M. Brendle, K. Schmidt / A multiplex-switch controller
generator is reset, CLR becomes passive, MPBUSY becomes passive, and the controller becomes ready to accept the next event. For external dead-time correction circuits, the state of MPBUSY is put out in the form of two +5 V signals MPBUYO and MPBUY1 and an FNL signal MPBUSYFNL. A circuit diagram of a single channel flipflop and the channel arbitration logic is shown in fig. 2. The input signal is level-translated by an inverting Schmitt-trigger made from one half of a fast voltage comparator Signetics NE521. A negative edge of the input signal will set the channel flipflop 1/2 741774, if the active-low channel-clear signal CLRiN is passive. The channel-clear signals CLRi N (i = 0, 1, . . . , 7) are generated by a GAL (Generic Array Logic) circuit Lattice GAL 16V8 [3] according to the equations: CLRiN = (CON and ClN and . . . and C(i - 1)N and C(i + 1)N and . . . and C7N and Not CLR And EN) Or (CON and CIN and . . . and C(i - 1)N and C(i + 1)N and . . . and C7N and Not CLR And Not CiN) . EN is the external enable signal . CLR is the clear signal, activated by the gate generator after the gate interval has expired. From the CLRiN equations one can see, that a channel flipflop is cleared and setting is inhibited as long as any other channel flipflop is in its active state or the common clear signal CLR is active . It can be set, if none of the channel flipflops is on, if the clear signal is passive, indicating that the controller and its ADCs are not busy, and if the external enable signal EN is active . If EN becomes passive, after a channel flipflop has been set, the processing of the current event is not disturbed. A pull-up resistor has been provided on the EN input. So the controller will work, when the enable input is open .
341
When a channel flipflop is set, than the clear signals for all other channel flipflops are activated. This is to prevent that two or more channel flipflops are active at the same time . Nevertheless it is possible, that two or more input signals arriving simultaneously activate two or more channel flipflops at the same time. Although all or all but one of them will be cleared again after a very short time, spikes at the flipflop outputs cannot be excluded completely . Therefore, the NAND gate 74LS30 combining the CiN signals is followed by a spike filter consisting of an RC low pass and a Schmidt-trigger NAND gate 1/4 74LS132 . The delay time between the leading edges of an INi input pulse and the associated Gi output pulse is 150 ns . The delay generator consists of a 10 MHz start/stop oscillator and a counter. The gate time can be chosen between 0.15 and 12 .85 Ws in 0.1 Ws increments . This timer is almost free of recovery effects. The individual channel gate signals GO, Gl, . . . ,and G7, the ADC gate signals, and the BUSY signals MPBUYO and MPBUY1 are generated by drivers able to drive long lines with TTL levels . Such a driver is shown in fig. 2. Its source resistance is about 50 S2 . Thus a 50 9 cable is in series terminated at the source. Even with parallel termination at the far end of the cable, TTL levels are reached. References [1] K. BÖpple and M. Brendle, Nucl. Instr. and Meth. [2]
[3]
(1971) 7.
94
CAMAC Model 3511, 3512, 3514, and 3515 High-Performance Spectroscopy ADC, Manual by LeCroy Corporation, 700 Chestnut Ridge Road, Chestnut Ridge, NY 10977-6499, USA (1984) .
GAL Data Book, Lattice Semiconductor Corporation, 5555 Northeast Moore Court, Hillsboro, Oregon 97124, USA (1990) .