- Email: [email protected]
A new successive approximation architecture for high-speed low-power ADCs
Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223 www.elsevier.de/aeue
A new successive approximation architecture for high-speed low-power ADCs Khosrov Dabbagh-Sadeghipour∗ , Khayrollah Hadidi, Abdollah Khoei Department of Electrical Engineering, Urmia University, Urmia 57159, Iran Received 2 January 2005; accepted 15 February 2005
Abstract A new high-speed successive approximation analog-to-digital converter (ADC) architecture is presented. Two-bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two digital-to-analog converter (DACs), is another novelty of the new architecture. The proposed DAC structure allows a substantial reduction in overall control logic complexity. A 10-bit 40 Ms/S successive approximation ADC was designed based on the proposed architecture in 0.35 m CMOS technology. The simulation results show that the proposed architecture introduces 7% reduction in power consumption over conventional architecture. Furthermore, chip area for the new ADC is 40% less than what otherwise would be needed by an ADC using conventional architecture. 䉷 2005 Elsevier GmbH. All rights reserved. Keywords: Analog-to-digital converter; Successive approximation; Low-power; High-speed
1. Introduction Analog-to-digital converters (ADCs) have been incorporated into most of the complex mixed signal systems. Due to high-density integration capability of CMOS process, the design of high-speed and low-power with small chip size CMOS ADCs is one of the major challenges in mixed-signal system-on-chip (SoC) applications. Among the Nyquist rate ADC design techniques, full flash and multi-step flash architectures in different system level approaches are widely used for high-speed analog-to-digital conversion. Full flash architecture needs 2n−1 comparators for n-bit conversion, which introduces large area and power consumption in higherresolution ADCs. The required comparators number reduction is realized by using multi-step flash architectures. It can ∗ Corresponding author.
E-mail address: [email protected] (K. Dabbagh-Sadeghipour). 1434-8411/$ - see front matter 䉷 2005 Elsevier GmbH. All rights reserved. doi:10.1016/j.aeue.2005.03.006
be reduced to 2(1+n/2) comparators in two-step flash architecture, which uses a coarse ADC as well as a fine ADC. Recently, the most high-speed and low-power ADCs are implemented by the well-known pipeline ADC architecture which is based on multi-step flash approach. It uses just n comparators for one-bit per stage pipelined architecture. This brings considerable reduction in area and power consumption relative to full flash architecture [1]. To reach high-resolution analog-to-digital conversion, the overall throughput of above architectures will be reduced, due to additional preparation time of comparators, which contains offset cancellation performed in every conversion cycle. This constraint can be relaxed by digital error correction techniques. Among other Nyquist rate ADC architectures, folding and interpolation techniques reduce the required comparators number in flash architecture to meet high-speed and low-power condition. However, it is difficult to achieve a high resolution (e.g. > eight-bit) due to the limitation in folding factor [2]. All of above ADC architectures
218
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223
Conventional SA-ADC
Required Clock Cycles
14 12
2, the proposed SA-ADC architecture is presented. Section 3 describes the circuit-level implementation of proposed architecture. The comparison results for the new and conventional SA-ADC architectures are demonstrated in Section 4. Concluding remarks are given in Section 5.
10 Proposed SA-ADC
8 6 4
Flash, Pipeline, 2 Folding 2
4
6
8
10 12 14
Bits of Resolution
Fig. 1. Comparison of A/D conversion techniques.
need just one clock cycle for n-bit conversion without offset cancellation and error correction cycles consideration. Successive approximation ADC (SA-ADC) architecture requires minimal area and power consumption [3–6], due to using just one comparator for n-bit conversion, but its throughput rate is clock frequency divided by n. In the other words, it requires n clock cycles for an n-bit analog-to-digital conversion. Fig. 1 shows comparison of above ADC architectures on throughput basis. As explained flash, pipeline and folding architectures use just one clock cycle for each conversion, regardless of resolution. But it takes at least n cycles for n-bit SA-ADC. In conventional SA-ADC, conversion rate inversely depends on ADC resolution which limits the ADC speed for higher resolutions. This constraint on conversion rate is reduced by half, applying the technique proposed here to conventional SA-ADC architecture. As shown in Fig. 1, the required clock cycles for n-bit proposed ADC architecture is n/2, half the cycles in conventional SA-ADC. The newly proposed high-speed SA-ADC (HSA-ADC) architecture can be assumed the first step in conventional successive approximation ADC architecture evolving toward flash-like architectures. It was found that if a number of SA-ADC are used in parallel, the overall throughput can be greatly improved. However, this introduces channel mismatch noise in digitized data, which can be eliminated by modern adaptive digital signal processing approaches proposed in [7,8]. This is not exaggeration that the parallel HSA-ADC architecture will be one of the best candidate architectures for low-power, low-cost and high-speed ADC design in future. For a 10-bit ADC using proposed architecture, doubling conversion rate requires a 70% increase in power consumption and 20% increase in area only. This is dramatically less than what otherwise would be needed. Notice that when two SAADCs are configured in parallel, to double conversion rate, certain blocks can be merged. Thus, its power consumption would be increased 83% and an extra area of 100% would be needed. This paper is organized as follows. In Section
2. The proposed SA-ADC architecture Fig. 2 shows the conventional SA-ADC architecture. It contains sample-and-hold, internal DAC, successive approximation register (SAR), control logic and finally voltage comparator. Its conversion rate is limited by the DAC settling time combined with the comparator resolution time. The accuracy of a SA-ADC is also limited by the precision of DAC’s component matching and the ability of the comparator to resolve small voltage differences. In a conventional SA-ADC, due to a single comparison in each clock cycle, only one bit is extracted in each cycle. Thus, for an n-bit SA-ADC (n + k) clock cycles are required, which k is the clock cycles needed to sample analog input and perform offset cancellation. As conversion proceeds, more and more internal DAC’s output approaches the sampled analog input signal. This can be written as Vdac [j ] = Vref ×
j −1
(bi × 2−i ) + Vref × 2−j ,
i=1
j = 1, 2, . . . , n,
(1)
where bi is ith most significant bit detected, Vdac [j ] is analog value of DAC in j th cycle and Vref is reference voltage of ADC. To increase conversion rate, two bits in each clock cycle are extracted in the newly proposed HSA-ADC architecture. Therefore, its required clock cycles for n-bit digitization will be n/2 + k. Fig. 3 shows the conceptual block diagram for two-bits extraction in each clock cycle. It uses flash-like three comparator structure for three-level comparison, and three internal DACs to generate the following analog voltages: Vdac_A [j ] = Vref ×
j −1
(bi × 2−i ) + Vref × 2−j
i=1
+ Vref × 2−(j +1) , j −1 (bi × 2−i ) + Vref × 2−j , Vdac_B [j ] = Vref × Vdac_C [j ] = Vref ×
i=1 j −1
(bi × 2−i ) + Vref × 2−j
i=1
− Vref × 2−(j +1) ,
j = 1, 3, 5, . . . , (n − 1). (2)
The above equations can be simplified to two equations as follows, which reduces required DACs to two and simplifies
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223
Vin
Vin
S/H
+
S/H
+
Vdac
DAC1
+
DAC1
-
219
Σ
-
+
Vdac1
+ -
DAC2
Vdac2 + -
SAR & Control Logic
+
-
SAR & Control Logic
Fig. 2. The conventional SA-ADC architecture.
Vin
Σ
Fig. 4. The proposed HSA-ADC architecture.
S/H + Vdac_A
DAC_A
ages for comparison defined in (4). The sampled analog input is compared with DAC1 output to determine the higher bit and is compared to (DAC1+DAC2) and (DAC1−DAC2) output values to find the lower bit in each conversion cycle. Three comparators output thermometer code is encoded to two binary bits by SAR built-in single encoder. Notice that although in Fig. 4 both signal and different reference levels are shown in pure voltage format, however, in our design all operations of offset cancellation, sampling, holding, subtraction and addition are performed with charge redistribution capacitor arrays and resistor string of 64 taps. Hence, a limited number of unit capacitors and unit resistors provide charge domain DAC operation which easily achieve 10-bit matching.
-
+ Vdac_B DAC_B
-
+ Vdac_C
DAC_C
-
SAR & Control Logic
3. Implementation Fig. 3. Two bits per clock cycle SA-ADC block diagram.
them dramatically. Vdac_A [j ] = Vdac1 [j ] + Vdac2 [j ], Vdac_B [j ] = Vdac1 [j ], Vdac_C [j ] = Vdac1 [j ] − Vdac2 [j ],
j = 1, 3, 5, . . . , (n − 1), (3)
Where Vdac1 and Vdac2 are the new DACs outputs determined by the following equations: Vdac1 [j ] = Vref ×
j −1
(bi × 2−i ) + Vref × 2−j ,
i=1
Vdac2 [j ] = Vref × 2−(j +1) ,
j = 1, 3, 5, . . . , (n − 1).
(4)
In above equation, the Vdac1 value is the same as DAC output voltage in an n − 1 bit SA-ADC and Vdac2 value can be produced by another simple DAC. The simplified diagram of proposed HSA-ADC architecture is illustrated in Fig. 4. DAC1 and DAC2 outputs generate the required analog volt-
A 10-bit, 40 Ms/S fully differential converter with 240 MHz clock has been designed based on the proposed HSA-ADC architecture in 0.35 m double poly, triple metal (DPTM) CMOS technology. It needs five clock cycles for 10-bits extraction (instead of 10 cycles in conventional architecture) and one clock cycle for sampling and offset cancellation in each conversion cycle. The designed ADC contains three offset cancelled comparators, charge redistribution DACs, a resistor string, a wideband passive sample-and-hold and control logic unit. The designed comparator block diagram is shown in Fig. 5. Three gain stages have been used to amplify 21 LSB to a large enough voltage which would regenerate the latch. Addition and subtraction operation of DAC1 and DAC2 in Fig. 4 is performed at comparator inputs. The comparator recovery time is efficiently reduced by using reset switches in output nodes of each stage. By comparator recovery we mean bringing differential outputs of each comparator stage to its corresponding common-mode level. The operation is performed by simply connecting differential output nodes of each
220
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223
φ
φ φ
+
Vin+
+
Vin-
-
φ
-
φ + -
φ
rst
φ
rst
+
+ rst
- +
- +
φ
Reg. Latch
dout
φ φ
φ
φ
clk
φ rst MSB MSB-1
...
...
...
LSB+1 LSB
MSB MSB-1
Comparsion Offset Cancellation
Fig. 5. The four-stage offset cancelled comparator. φ
φ CBS
VBS
φ
φ
φ Vgate Vout CSampling
Vin φ φ
SBottom plate
Vin Vgate
Fig. 6. Bootstrapped bottom-plate sample and hold.
stage, for a short time, using a small switch. This is many times faster than otherwise letting minimal differential currents to pull the stage out of overdriven state. To achieve high-speed comparison and perform offset cancellation in minimum required time, each gain stage offset is saved in the same stage in one clock cycle. Moreover, input analog voltage is sampled in the same clock cycle simultaneously. The comparator timing diagram is shown in Fig. 5. After offset cancellation, comparator performs accurate comparison in next five clock cycles. In other words, just one time offset zeroing is sufficient to perform five times correct comparison. This is the built-in advantage of successive approximation architecture over flash-like structures. Bootstrapped input switches (as in [9] and bottom plate sampling techniques have been used to reach required sampling linearity and speed as shown in Fig. 6. In hold phase, CBS
is charged to VBS. VBS is the maximum voltage when added to the pick of input signal, the total is still a little under gate breakdown voltage. In sampling phase, the gate voltage of sampling switch follows analog input to reduce MOS transistor nonlinear transconductance effect by keeping gate-source voltage constant. The analog input sampling and offset cancellation time was reduced to one clock cycle in the new ADC, while it takes two and four cycles in [3,10] respectively. The overall block diagram of the new ADC is shown in Fig. 7. The proposed DAC1 and DAC2 are implemented by resistive reference voltage division and charge redistribution techniques [4,6,10,11] as shown in Fig. 7.
4. Cost comparison To evaluate the new architecture performance, we have compared it with a conventional 10-bit SA-ADC. The conventional ADC uses 12 clock cycles for 10-bit conversion (10 cycles for 10-bits extraction and two cycles for sampling and offset cancellation [10]). Its conversion rate with 240 MHz clock is 20 Ms/S, half the rate of the designed HSA-ADC. The simulation results for comparison of the proposed HSA-ADC with conventional SA-ADC are given in Table 1. Both ADCs (SA-ADC and HSA-ADC) use the same comparator and S/H circuits for equitable comparison. Due to use of three comparators in HSA-ADC, the power consumption and area of analog section have increased, but those for digital section have decreased. This is due to simplification in control logic which requires only six clock cycles instead of 12 cycles. From DAC comparison viewpoint, both ADCs use a 64-tap resistive reference voltage division, but 20 extra unit capacitors and 11 extra switches are required in HSA-ADC. Twenty per cent increase in estimated chip core area and 70% increase in power consumption has
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223
SAR & Control Logic
Comparators Bootstrapped switches
Capacitor Array
Capacitor Array
Capacitor Array
VinCapacitor Array
Vin+
221
Resistor String DAC1
DAC2
Fig. 7. The designed HSA-ADC with efficient DAC structure.
Table 1. Comparison of HSA-ADC and conventional SA-ADC architectures
Resolution Clock freq. Sample rate Input range Input bandwidth Power consumption SNDR Power supply Estimated area Technology No. of unit resistors No. of unit capacitors No. of switches
Proposed HSA-ADC
Conventional SA-ADC
Conventional PSA-ADC
10-bit 240 MHz 40 Ms/S 1.6 Vp–p 120 MHz 43.2 mW −60.6 dB fin = 12.4 MHz 3.3 V 0.2 mm2 0.35 m DPTM CMOS 64 40 57
10-bit 240 MHz 20 Ms/S 1.6 Vp–p 120 MHz 25.4 mW −60.5 dB fin = 6.2 MHz 3.3 V 0.166 mm2 0.35 m DPTM CMOS 64 20 46
10-bit 240 MHz 40 Ms/S 1.6 Vp–p 120 MHz 46.5 mW −58 dB fin = 12.4 MHz 3.3 V 0.332 mm2 0.35 m DPTM CMOS 64 40 92
been obtained with HSA-ADC architecture implementation over the SA-ADC architecture for doubling conversion rate. The signal-to-noise-and-distortion-ratio (SNDR) was calculated from simulation results as −60.6 and −60.5 dB for HSA-ADC and SA-ADC, respectively. For fair comparison, the designed HSA-ADC’s specifications have been compared with two time-interleaved SA-ADCs as Parallel SAADC (PSA-ADC) in Table 1, to evaluate the two structures in identical conversion rates. Both of HSA-ADC and PSAADC perform conversion in 40 Ms/S. A 7% reduction in power consumption and 40% reduction in estimated chip size are the major advantages of the proposed HSA-ADC architecture. It is important to note that the parallel SA-ADC architecture introduces channel mismatch
error, which will damage signal-to-noise ratio [3,12,13] (this effect was not considered in simulations); while single channel HSA-ADC architecture is immune to such a mismatch error source. Notice that the data in Table 1 are taken from completely designed and simulated ADCs in circuit level. Using dynamic range (DR), bandwidth (BW), power dissipation (P) and process feature size (L), we define figure of merit (FoM) as FoM = (DR)dB + 20 log
(BW)MHz × (L)m (P )mW
.
(5)
Hence, we can compare all architectures/designs using FoM. Fig. 8 shows FoM of previously published as well as
222
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223 50 [21]
Proposed Pipeline Folding Two-Step Successive Approximation Parallel-Pipeline
Proposed
45
FoM (Figure-of-Merit)
[15]
[19]
40 [16]
[22]
[10] 35
[18]
[17] 30
[14]
[20]
25
[24] [23]
20
15 5
15
25
35
45
55
65
75
85
Nyquist Bandwidth (MHz)
Fig. 8. Comparison with different ADC architectures [14–24].
proposed work. There is only one other ADC with a higher FoM. However, it operates at a lower sampling rate.
5. Conclusions This paper presents a new ADC architecture employing a modified successive approximation algorithm. In order to reach high conversion rate in successive approximation ADC (SA-ADC) architecture, two bits are extracted in each clock cycle. Thus, two extra comparators are required. To overcome DAC complexity problem, a new efficient DAC structure has been proposed. The simulation results for the designed 10-bit ADC show that at the same conversion rate, the proposed SA-ADC architecture introduces 40% and 7% reduction in chip size and power consumption over conventional SA-ADC architecture, while is immune to any mismatch error of parallel SA-ADC.
References [1] Cho T, et al., Design consideration for high-speed lowpower low-voltage CMOS analog-to-digital converters. IEEE symposium on low-power electronics, 1994. p. 461–4. [2] Nabavi A, Dabbagh K. A 10-bit, 20 ms/s, 22 MW folding and interpolating CMOS ADC. IEEE international conference on microelectronics, 2000. p. 43–6. [3] Yuan J, Svensson C. A 10-bit 5-ms/s successive approximation ADC cell used in a 70-ms/s ADC array in 1.2-m CMOS. IEEE J Solid-State Circuits 1994;29:866–72. [4] Fotouhi B, Hodges D. High-resolution A/D conversion in MOS/LSI. IEEE J Solid-State Circuits 1979;14:920–6. [5] Bacrania K. A 12-bit successive-approximation-type ADC with digital error correction. IEEE J Solid-State Circuits 1986;21:1016–25.
[6] Hadidi K, Tso V, Temes G. An 8-bit 1.3 MHz successive approximation A/D converter. IEEE J Solid-State Circuits 1990;25:880–5. [7] Velazquez S, et al., Adaptive parallel processing analog and digital converter. US Patent 6 339 390, 2002. [8] Velazquez S, et al., Parallel processing analog and digital converter. US Patent 6 177 89, 2001. [9] Abo A, Gray P. A 1.5 v, 10-bit, 14.3-ms/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circuits 1999;34:599–606. [10] Ghoddami H, A 10-bit 50-ms/s parallel successiveapproximation A/D. Diploma thesis, Electrical Engineering Department, Urmia University, Iran, 1998. [11] McCreary J, Gray P. All-MOS charge redistribution analogto-digital conversion techniques—part i. IEEE J Solid-State Circuits 1975;10:371–9. [12] Black W, Hodges D. Time interleaved converter arrays. IEEE J Solid-State Circuits 1980;15:1022–9. [13] Petraglia A, Mitra S. Analysis of mismatch effect among A/D converters in a time-interleaved waveform digitizer. IEEE Trans Instrum Meas 1991;40:831–5. [14] Sang-Min Y, et al., A 10 b 150 ms/s 123 MW 0.18 m CMOS pipelined ADC. IEEE international solid-state circuits conference digest technical papers, 2003. p. 326–7. [15] Miyazaki D, et al., A 16 MW 30 msample/s 10 b pipelined A/D converter using a pseudo-differential architecture. IEEE international solid-state circuits conference digest technical papers, 2002. p. 174–5. [16] Jamal S, et al., A 10 b 120 msample/s time-interleaved analogto-digital converter with digital background calibration. IEEE international solid-state circuits conference digest technical papers, 2002. p. 172–3. [17] Kuttner F, et al., A 1.2 V 10 b 20 msample/s non-binary successive approximation ADC in 0.13 m CMOS. IEEE international solid-state circuits conference digest technical papers, 2002. p. 176–7. [18] Park Y, et al., A 10 b 100 msample/s CMOS pipelined ADC with 1.8 V power supply. IEEE international solid-state circuits conference digest technical papers, 2001. p. 130–1.
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223
[19] Byung-Moo M, et al., A 69 MW 10 b 80 ms/s pipelined CMOS ADC. IEEE international solid-state circuits conference digest technical papers, 2003. p. 324–5. [20] Bult K, Buckwald A. An embedded 240-MW 10-b 50ms/s CMOS ADC in 1-mm2 . IEEE J Solid-State Circuits 1997;32:1887–95. [21] Cho T, Gray P. A 10-b, 20-msample/s, 35-MW pipeline A/D converter. IEEE J Solid-State Circuits 1995;30:166–72. [22] Nakamura K. et al. An 85 MW, 10 b, 40 msample/s CMOS parallel-pipeline ADC. IEEE J Solid-State 1995;30:173–83. [23] Yotsuyanagi M. et al. A 10-b 50 MHz pipelined CMOS A/D converter with S/H. IEEE J Solid-State Circuits 1993;28: 292–300. [24] Van Der Ploeg H, Remmers R. A 3.3 V 10-b 25-msample/s two-step ADC in 0.35 m CMOS. IEEE J Solid-State Circuits 1999;34:1803–11. Khosrov Dabbagh-Sadeghipour was born in Tabriz, Iran, in 1975. He received his B.S. degrees in Electrical Engineering from Urmia University, Iran in 1997, his M.S. degree in Electrical Engineering from Tarbiat-Modares University, Iran in 2000. He is currently pursuing the Ph.D. degree in Electrical Engineering at Electrical Engineering Department, Urmia University, Iran. His research interests include analog IC design for high-speed data acquisition and wireless communication applications.
223
Khayrollah Hadidi received his B.S. degree from Sharif University of Technology in Tehran, Iran, his M.S. degree from polytechnic University, New York, and his Ph.D. degree from University of California, Los Angeles, all in Electrical Engineering. His research interests are high-speed high-resolution data converter design, wideband integrated filter design, and nonlinearity analysis and improvement in analog circuits. He is currently with Electrical Engineering Department and Microelectronics Research Laboratory in Urmia University, Urmia, Iran. He holds one US patent (issued), and one US plus 12 Japanese patents (pending). Abdollah Khoei was born in Urmia, Iran. He received B.S., M.S. and Ph.D. degrees in Electrical Engineering from North Dakota State University, USA, in 1982, 1985, 1989, respectively. His research interests are analog and digital integrated circuit design for fuzzy and neural network applications, fuzzy-based industrial electronics, and DC–DC converters for portable applications. He is currently with Electrical Engineering Department and Microelectronics Research Laboratory in Urmia University, Urmia, Iran.
A new successive approximation architecture for high-speed low-power ADCs Khosrov Dabbagh-Sadeghipour∗ , Khayrollah Hadidi, Abdollah Khoei Department of Electrical Engineering, Urmia University, Urmia 57159, Iran Received 2 January 2005; accepted 15 February 2005
Abstract A new high-speed successive approximation analog-to-digital converter (ADC) architecture is presented. Two-bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two digital-to-analog converter (DACs), is another novelty of the new architecture. The proposed DAC structure allows a substantial reduction in overall control logic complexity. A 10-bit 40 Ms/S successive approximation ADC was designed based on the proposed architecture in 0.35 m CMOS technology. The simulation results show that the proposed architecture introduces 7% reduction in power consumption over conventional architecture. Furthermore, chip area for the new ADC is 40% less than what otherwise would be needed by an ADC using conventional architecture. 䉷 2005 Elsevier GmbH. All rights reserved. Keywords: Analog-to-digital converter; Successive approximation; Low-power; High-speed
1. Introduction Analog-to-digital converters (ADCs) have been incorporated into most of the complex mixed signal systems. Due to high-density integration capability of CMOS process, the design of high-speed and low-power with small chip size CMOS ADCs is one of the major challenges in mixed-signal system-on-chip (SoC) applications. Among the Nyquist rate ADC design techniques, full flash and multi-step flash architectures in different system level approaches are widely used for high-speed analog-to-digital conversion. Full flash architecture needs 2n−1 comparators for n-bit conversion, which introduces large area and power consumption in higherresolution ADCs. The required comparators number reduction is realized by using multi-step flash architectures. It can ∗ Corresponding author.
E-mail address: [email protected] (K. Dabbagh-Sadeghipour). 1434-8411/$ - see front matter 䉷 2005 Elsevier GmbH. All rights reserved. doi:10.1016/j.aeue.2005.03.006
be reduced to 2(1+n/2) comparators in two-step flash architecture, which uses a coarse ADC as well as a fine ADC. Recently, the most high-speed and low-power ADCs are implemented by the well-known pipeline ADC architecture which is based on multi-step flash approach. It uses just n comparators for one-bit per stage pipelined architecture. This brings considerable reduction in area and power consumption relative to full flash architecture [1]. To reach high-resolution analog-to-digital conversion, the overall throughput of above architectures will be reduced, due to additional preparation time of comparators, which contains offset cancellation performed in every conversion cycle. This constraint can be relaxed by digital error correction techniques. Among other Nyquist rate ADC architectures, folding and interpolation techniques reduce the required comparators number in flash architecture to meet high-speed and low-power condition. However, it is difficult to achieve a high resolution (e.g. > eight-bit) due to the limitation in folding factor [2]. All of above ADC architectures
218
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223
Conventional SA-ADC
Required Clock Cycles
14 12
2, the proposed SA-ADC architecture is presented. Section 3 describes the circuit-level implementation of proposed architecture. The comparison results for the new and conventional SA-ADC architectures are demonstrated in Section 4. Concluding remarks are given in Section 5.
10 Proposed SA-ADC
8 6 4
Flash, Pipeline, 2 Folding 2
4
6
8
10 12 14
Bits of Resolution
Fig. 1. Comparison of A/D conversion techniques.
need just one clock cycle for n-bit conversion without offset cancellation and error correction cycles consideration. Successive approximation ADC (SA-ADC) architecture requires minimal area and power consumption [3–6], due to using just one comparator for n-bit conversion, but its throughput rate is clock frequency divided by n. In the other words, it requires n clock cycles for an n-bit analog-to-digital conversion. Fig. 1 shows comparison of above ADC architectures on throughput basis. As explained flash, pipeline and folding architectures use just one clock cycle for each conversion, regardless of resolution. But it takes at least n cycles for n-bit SA-ADC. In conventional SA-ADC, conversion rate inversely depends on ADC resolution which limits the ADC speed for higher resolutions. This constraint on conversion rate is reduced by half, applying the technique proposed here to conventional SA-ADC architecture. As shown in Fig. 1, the required clock cycles for n-bit proposed ADC architecture is n/2, half the cycles in conventional SA-ADC. The newly proposed high-speed SA-ADC (HSA-ADC) architecture can be assumed the first step in conventional successive approximation ADC architecture evolving toward flash-like architectures. It was found that if a number of SA-ADC are used in parallel, the overall throughput can be greatly improved. However, this introduces channel mismatch noise in digitized data, which can be eliminated by modern adaptive digital signal processing approaches proposed in [7,8]. This is not exaggeration that the parallel HSA-ADC architecture will be one of the best candidate architectures for low-power, low-cost and high-speed ADC design in future. For a 10-bit ADC using proposed architecture, doubling conversion rate requires a 70% increase in power consumption and 20% increase in area only. This is dramatically less than what otherwise would be needed. Notice that when two SAADCs are configured in parallel, to double conversion rate, certain blocks can be merged. Thus, its power consumption would be increased 83% and an extra area of 100% would be needed. This paper is organized as follows. In Section
2. The proposed SA-ADC architecture Fig. 2 shows the conventional SA-ADC architecture. It contains sample-and-hold, internal DAC, successive approximation register (SAR), control logic and finally voltage comparator. Its conversion rate is limited by the DAC settling time combined with the comparator resolution time. The accuracy of a SA-ADC is also limited by the precision of DAC’s component matching and the ability of the comparator to resolve small voltage differences. In a conventional SA-ADC, due to a single comparison in each clock cycle, only one bit is extracted in each cycle. Thus, for an n-bit SA-ADC (n + k) clock cycles are required, which k is the clock cycles needed to sample analog input and perform offset cancellation. As conversion proceeds, more and more internal DAC’s output approaches the sampled analog input signal. This can be written as Vdac [j ] = Vref ×
j −1
(bi × 2−i ) + Vref × 2−j ,
i=1
j = 1, 2, . . . , n,
(1)
where bi is ith most significant bit detected, Vdac [j ] is analog value of DAC in j th cycle and Vref is reference voltage of ADC. To increase conversion rate, two bits in each clock cycle are extracted in the newly proposed HSA-ADC architecture. Therefore, its required clock cycles for n-bit digitization will be n/2 + k. Fig. 3 shows the conceptual block diagram for two-bits extraction in each clock cycle. It uses flash-like three comparator structure for three-level comparison, and three internal DACs to generate the following analog voltages: Vdac_A [j ] = Vref ×
j −1
(bi × 2−i ) + Vref × 2−j
i=1
+ Vref × 2−(j +1) , j −1 (bi × 2−i ) + Vref × 2−j , Vdac_B [j ] = Vref × Vdac_C [j ] = Vref ×
i=1 j −1
(bi × 2−i ) + Vref × 2−j
i=1
− Vref × 2−(j +1) ,
j = 1, 3, 5, . . . , (n − 1). (2)
The above equations can be simplified to two equations as follows, which reduces required DACs to two and simplifies
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223
Vin
Vin
S/H
+
S/H
+
Vdac
DAC1
+
DAC1
-
219
Σ
-
+
Vdac1
+ -
DAC2
Vdac2 + -
SAR & Control Logic
+
-
SAR & Control Logic
Fig. 2. The conventional SA-ADC architecture.
Vin
Σ
Fig. 4. The proposed HSA-ADC architecture.
S/H + Vdac_A
DAC_A
ages for comparison defined in (4). The sampled analog input is compared with DAC1 output to determine the higher bit and is compared to (DAC1+DAC2) and (DAC1−DAC2) output values to find the lower bit in each conversion cycle. Three comparators output thermometer code is encoded to two binary bits by SAR built-in single encoder. Notice that although in Fig. 4 both signal and different reference levels are shown in pure voltage format, however, in our design all operations of offset cancellation, sampling, holding, subtraction and addition are performed with charge redistribution capacitor arrays and resistor string of 64 taps. Hence, a limited number of unit capacitors and unit resistors provide charge domain DAC operation which easily achieve 10-bit matching.
-
+ Vdac_B DAC_B
-
+ Vdac_C
DAC_C
-
SAR & Control Logic
3. Implementation Fig. 3. Two bits per clock cycle SA-ADC block diagram.
them dramatically. Vdac_A [j ] = Vdac1 [j ] + Vdac2 [j ], Vdac_B [j ] = Vdac1 [j ], Vdac_C [j ] = Vdac1 [j ] − Vdac2 [j ],
j = 1, 3, 5, . . . , (n − 1), (3)
Where Vdac1 and Vdac2 are the new DACs outputs determined by the following equations: Vdac1 [j ] = Vref ×
j −1
(bi × 2−i ) + Vref × 2−j ,
i=1
Vdac2 [j ] = Vref × 2−(j +1) ,
j = 1, 3, 5, . . . , (n − 1).
(4)
In above equation, the Vdac1 value is the same as DAC output voltage in an n − 1 bit SA-ADC and Vdac2 value can be produced by another simple DAC. The simplified diagram of proposed HSA-ADC architecture is illustrated in Fig. 4. DAC1 and DAC2 outputs generate the required analog volt-
A 10-bit, 40 Ms/S fully differential converter with 240 MHz clock has been designed based on the proposed HSA-ADC architecture in 0.35 m double poly, triple metal (DPTM) CMOS technology. It needs five clock cycles for 10-bits extraction (instead of 10 cycles in conventional architecture) and one clock cycle for sampling and offset cancellation in each conversion cycle. The designed ADC contains three offset cancelled comparators, charge redistribution DACs, a resistor string, a wideband passive sample-and-hold and control logic unit. The designed comparator block diagram is shown in Fig. 5. Three gain stages have been used to amplify 21 LSB to a large enough voltage which would regenerate the latch. Addition and subtraction operation of DAC1 and DAC2 in Fig. 4 is performed at comparator inputs. The comparator recovery time is efficiently reduced by using reset switches in output nodes of each stage. By comparator recovery we mean bringing differential outputs of each comparator stage to its corresponding common-mode level. The operation is performed by simply connecting differential output nodes of each
220
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223
φ
φ φ
+
Vin+
+
Vin-
-
φ
-
φ + -
φ
rst
φ
rst
+
+ rst
- +
- +
φ
Reg. Latch
dout
φ φ
φ
φ
clk
φ rst MSB MSB-1
...
...
...
LSB+1 LSB
MSB MSB-1
Comparsion Offset Cancellation
Fig. 5. The four-stage offset cancelled comparator. φ
φ CBS
VBS
φ
φ
φ Vgate Vout CSampling
Vin φ φ
SBottom plate
Vin Vgate
Fig. 6. Bootstrapped bottom-plate sample and hold.
stage, for a short time, using a small switch. This is many times faster than otherwise letting minimal differential currents to pull the stage out of overdriven state. To achieve high-speed comparison and perform offset cancellation in minimum required time, each gain stage offset is saved in the same stage in one clock cycle. Moreover, input analog voltage is sampled in the same clock cycle simultaneously. The comparator timing diagram is shown in Fig. 5. After offset cancellation, comparator performs accurate comparison in next five clock cycles. In other words, just one time offset zeroing is sufficient to perform five times correct comparison. This is the built-in advantage of successive approximation architecture over flash-like structures. Bootstrapped input switches (as in [9] and bottom plate sampling techniques have been used to reach required sampling linearity and speed as shown in Fig. 6. In hold phase, CBS
is charged to VBS. VBS is the maximum voltage when added to the pick of input signal, the total is still a little under gate breakdown voltage. In sampling phase, the gate voltage of sampling switch follows analog input to reduce MOS transistor nonlinear transconductance effect by keeping gate-source voltage constant. The analog input sampling and offset cancellation time was reduced to one clock cycle in the new ADC, while it takes two and four cycles in [3,10] respectively. The overall block diagram of the new ADC is shown in Fig. 7. The proposed DAC1 and DAC2 are implemented by resistive reference voltage division and charge redistribution techniques [4,6,10,11] as shown in Fig. 7.
4. Cost comparison To evaluate the new architecture performance, we have compared it with a conventional 10-bit SA-ADC. The conventional ADC uses 12 clock cycles for 10-bit conversion (10 cycles for 10-bits extraction and two cycles for sampling and offset cancellation [10]). Its conversion rate with 240 MHz clock is 20 Ms/S, half the rate of the designed HSA-ADC. The simulation results for comparison of the proposed HSA-ADC with conventional SA-ADC are given in Table 1. Both ADCs (SA-ADC and HSA-ADC) use the same comparator and S/H circuits for equitable comparison. Due to use of three comparators in HSA-ADC, the power consumption and area of analog section have increased, but those for digital section have decreased. This is due to simplification in control logic which requires only six clock cycles instead of 12 cycles. From DAC comparison viewpoint, both ADCs use a 64-tap resistive reference voltage division, but 20 extra unit capacitors and 11 extra switches are required in HSA-ADC. Twenty per cent increase in estimated chip core area and 70% increase in power consumption has
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223
SAR & Control Logic
Comparators Bootstrapped switches
Capacitor Array
Capacitor Array
Capacitor Array
VinCapacitor Array
Vin+
221
Resistor String DAC1
DAC2
Fig. 7. The designed HSA-ADC with efficient DAC structure.
Table 1. Comparison of HSA-ADC and conventional SA-ADC architectures
Resolution Clock freq. Sample rate Input range Input bandwidth Power consumption SNDR Power supply Estimated area Technology No. of unit resistors No. of unit capacitors No. of switches
Proposed HSA-ADC
Conventional SA-ADC
Conventional PSA-ADC
10-bit 240 MHz 40 Ms/S 1.6 Vp–p 120 MHz 43.2 mW −60.6 dB fin = 12.4 MHz 3.3 V 0.2 mm2 0.35 m DPTM CMOS 64 40 57
10-bit 240 MHz 20 Ms/S 1.6 Vp–p 120 MHz 25.4 mW −60.5 dB fin = 6.2 MHz 3.3 V 0.166 mm2 0.35 m DPTM CMOS 64 20 46
10-bit 240 MHz 40 Ms/S 1.6 Vp–p 120 MHz 46.5 mW −58 dB fin = 12.4 MHz 3.3 V 0.332 mm2 0.35 m DPTM CMOS 64 40 92
been obtained with HSA-ADC architecture implementation over the SA-ADC architecture for doubling conversion rate. The signal-to-noise-and-distortion-ratio (SNDR) was calculated from simulation results as −60.6 and −60.5 dB for HSA-ADC and SA-ADC, respectively. For fair comparison, the designed HSA-ADC’s specifications have been compared with two time-interleaved SA-ADCs as Parallel SAADC (PSA-ADC) in Table 1, to evaluate the two structures in identical conversion rates. Both of HSA-ADC and PSAADC perform conversion in 40 Ms/S. A 7% reduction in power consumption and 40% reduction in estimated chip size are the major advantages of the proposed HSA-ADC architecture. It is important to note that the parallel SA-ADC architecture introduces channel mismatch
error, which will damage signal-to-noise ratio [3,12,13] (this effect was not considered in simulations); while single channel HSA-ADC architecture is immune to such a mismatch error source. Notice that the data in Table 1 are taken from completely designed and simulated ADCs in circuit level. Using dynamic range (DR), bandwidth (BW), power dissipation (P) and process feature size (L), we define figure of merit (FoM) as FoM = (DR)dB + 20 log
(BW)MHz × (L)m (P )mW
.
(5)
Hence, we can compare all architectures/designs using FoM. Fig. 8 shows FoM of previously published as well as
222
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223 50 [21]
Proposed Pipeline Folding Two-Step Successive Approximation Parallel-Pipeline
Proposed
45
FoM (Figure-of-Merit)
[15]
[19]
40 [16]
[22]
[10] 35
[18]
[17] 30
[14]
[20]
25
[24] [23]
20
15 5
15
25
35
45
55
65
75
85
Nyquist Bandwidth (MHz)
Fig. 8. Comparison with different ADC architectures [14–24].
proposed work. There is only one other ADC with a higher FoM. However, it operates at a lower sampling rate.
5. Conclusions This paper presents a new ADC architecture employing a modified successive approximation algorithm. In order to reach high conversion rate in successive approximation ADC (SA-ADC) architecture, two bits are extracted in each clock cycle. Thus, two extra comparators are required. To overcome DAC complexity problem, a new efficient DAC structure has been proposed. The simulation results for the designed 10-bit ADC show that at the same conversion rate, the proposed SA-ADC architecture introduces 40% and 7% reduction in chip size and power consumption over conventional SA-ADC architecture, while is immune to any mismatch error of parallel SA-ADC.
References [1] Cho T, et al., Design consideration for high-speed lowpower low-voltage CMOS analog-to-digital converters. IEEE symposium on low-power electronics, 1994. p. 461–4. [2] Nabavi A, Dabbagh K. A 10-bit, 20 ms/s, 22 MW folding and interpolating CMOS ADC. IEEE international conference on microelectronics, 2000. p. 43–6. [3] Yuan J, Svensson C. A 10-bit 5-ms/s successive approximation ADC cell used in a 70-ms/s ADC array in 1.2-m CMOS. IEEE J Solid-State Circuits 1994;29:866–72. [4] Fotouhi B, Hodges D. High-resolution A/D conversion in MOS/LSI. IEEE J Solid-State Circuits 1979;14:920–6. [5] Bacrania K. A 12-bit successive-approximation-type ADC with digital error correction. IEEE J Solid-State Circuits 1986;21:1016–25.
[6] Hadidi K, Tso V, Temes G. An 8-bit 1.3 MHz successive approximation A/D converter. IEEE J Solid-State Circuits 1990;25:880–5. [7] Velazquez S, et al., Adaptive parallel processing analog and digital converter. US Patent 6 339 390, 2002. [8] Velazquez S, et al., Parallel processing analog and digital converter. US Patent 6 177 89, 2001. [9] Abo A, Gray P. A 1.5 v, 10-bit, 14.3-ms/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circuits 1999;34:599–606. [10] Ghoddami H, A 10-bit 50-ms/s parallel successiveapproximation A/D. Diploma thesis, Electrical Engineering Department, Urmia University, Iran, 1998. [11] McCreary J, Gray P. All-MOS charge redistribution analogto-digital conversion techniques—part i. IEEE J Solid-State Circuits 1975;10:371–9. [12] Black W, Hodges D. Time interleaved converter arrays. IEEE J Solid-State Circuits 1980;15:1022–9. [13] Petraglia A, Mitra S. Analysis of mismatch effect among A/D converters in a time-interleaved waveform digitizer. IEEE Trans Instrum Meas 1991;40:831–5. [14] Sang-Min Y, et al., A 10 b 150 ms/s 123 MW 0.18 m CMOS pipelined ADC. IEEE international solid-state circuits conference digest technical papers, 2003. p. 326–7. [15] Miyazaki D, et al., A 16 MW 30 msample/s 10 b pipelined A/D converter using a pseudo-differential architecture. IEEE international solid-state circuits conference digest technical papers, 2002. p. 174–5. [16] Jamal S, et al., A 10 b 120 msample/s time-interleaved analogto-digital converter with digital background calibration. IEEE international solid-state circuits conference digest technical papers, 2002. p. 172–3. [17] Kuttner F, et al., A 1.2 V 10 b 20 msample/s non-binary successive approximation ADC in 0.13 m CMOS. IEEE international solid-state circuits conference digest technical papers, 2002. p. 176–7. [18] Park Y, et al., A 10 b 100 msample/s CMOS pipelined ADC with 1.8 V power supply. IEEE international solid-state circuits conference digest technical papers, 2001. p. 130–1.
K. Dabbagh-Sadeghipour et al. / Int. J. Electron. Commun. (AEÜ) 60 (2006) 217 – 223
[19] Byung-Moo M, et al., A 69 MW 10 b 80 ms/s pipelined CMOS ADC. IEEE international solid-state circuits conference digest technical papers, 2003. p. 324–5. [20] Bult K, Buckwald A. An embedded 240-MW 10-b 50ms/s CMOS ADC in 1-mm2 . IEEE J Solid-State Circuits 1997;32:1887–95. [21] Cho T, Gray P. A 10-b, 20-msample/s, 35-MW pipeline A/D converter. IEEE J Solid-State Circuits 1995;30:166–72. [22] Nakamura K. et al. An 85 MW, 10 b, 40 msample/s CMOS parallel-pipeline ADC. IEEE J Solid-State 1995;30:173–83. [23] Yotsuyanagi M. et al. A 10-b 50 MHz pipelined CMOS A/D converter with S/H. IEEE J Solid-State Circuits 1993;28: 292–300. [24] Van Der Ploeg H, Remmers R. A 3.3 V 10-b 25-msample/s two-step ADC in 0.35 m CMOS. IEEE J Solid-State Circuits 1999;34:1803–11. Khosrov Dabbagh-Sadeghipour was born in Tabriz, Iran, in 1975. He received his B.S. degrees in Electrical Engineering from Urmia University, Iran in 1997, his M.S. degree in Electrical Engineering from Tarbiat-Modares University, Iran in 2000. He is currently pursuing the Ph.D. degree in Electrical Engineering at Electrical Engineering Department, Urmia University, Iran. His research interests include analog IC design for high-speed data acquisition and wireless communication applications.
223
Khayrollah Hadidi received his B.S. degree from Sharif University of Technology in Tehran, Iran, his M.S. degree from polytechnic University, New York, and his Ph.D. degree from University of California, Los Angeles, all in Electrical Engineering. His research interests are high-speed high-resolution data converter design, wideband integrated filter design, and nonlinearity analysis and improvement in analog circuits. He is currently with Electrical Engineering Department and Microelectronics Research Laboratory in Urmia University, Urmia, Iran. He holds one US patent (issued), and one US plus 12 Japanese patents (pending). Abdollah Khoei was born in Urmia, Iran. He received B.S., M.S. and Ph.D. degrees in Electrical Engineering from North Dakota State University, USA, in 1982, 1985, 1989, respectively. His research interests are analog and digital integrated circuit design for fuzzy and neural network applications, fuzzy-based industrial electronics, and DC–DC converters for portable applications. He is currently with Electrical Engineering Department and Microelectronics Research Laboratory in Urmia University, Urmia, Iran.