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A novel approach to resistivity and interconnect modeling
Microelectronic Engineering 83 (2006) 2417–2421 www.elsevier.com/locate/mee
A novel approach to resistivity and interconnect modeling Y. Travaly *, M. Bamal, L. Carbonell, F. Iacopi, M. Stucchi, M. Van Hove, G.P. Beyer IMEC vzw, 75 Kapeldreef, 3001 Heverlee, Belgium Available online 20 October 2006
Abstract This paper describes a simple and novel approach to calculate the line resistance of copper interconnects. The proposed methodology is simply based on a linear representation of the Cu resistivity vs. 1/SCu (SCu is the Cu cross-sectional area) in which the slope captures the net result of scattering phenomena in Cu. Ó 2006 Elsevier B.V. All rights reserved. Keywords: Copper resistivity; Modeling; RC delay; Variability
1. Introduction Accurate modeling and prediction of the resistivity of Cu thin films and damascene Cu lines have been the subject of many studies. While the existing Cu resistivity models including the effects of scattering phenomena (grain boundary, interface, surface roughness, impurities, etc.) on the resistivity of Cu thin films are generally well described [1,2], their extension to Cu lines is far more difficult. Kuan et al. [3] proposed a model based on the combined surface and grain boundary scattering effects, which depends on the line width and the grain size. However, such a model requires a detailed characterization of grain size distribution and also, does not include explicitly the line height. These limitations are overcome by Hinode et al. [4] who proposed a generalization of the Fuch and Sondheimer [5] formula for describing the resisitivity of Cu lines in terms of both line width and line thickness. Even if this model takes only into account the effect of electron-surface scattering, it already goes beyond the earlier applied equation of the simple form q = q0Ck/W, where q0 is the resistivity of bulk Cu, k is the electron mean free path and W is the line width, in the sense that the Cu height is taken into
*
Corresponding author. Tel.: +32 16 281723; fax: +32 16 281576. E-mail address: [email protected] (Y. Travaly).
0167-9317/$ - see front matter Ó 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2006.10.048
account. More recently, Steinho¨gl et al. [6] used a numerical approach, which accounts for the influence of most scattering phenomena besides the inclusion of line width and height. This is, as of today, the most complete description of resistivity of damascene Cu lines. However, even if it delivers good results in terms of measured resisitivity data fitting and interpretation, the model is quite complex and only valid for rectangular cross-sections. For instance, we calculated for 160 nm metal pitch that approximating a trapezoidal cross-section by a rectangular one (in this case using an average line for area calculation of the rectangular cross-section) leads to a 6% overestimation of cross-sectional area. Due to these limitations, it can not enable an accurate assessment of IC performance trends which should take into account process variability in dimensions and shape of wire cross-section. As a matter of fact, continuous process optimization and performance assessment are equally important to control the Cu resistivity increase. As scaling continues, process variability becomes more important, resulting in substantial statistical interconnect process fluctuations that complicate the use of existing performance metrics for backend-of-line (BEOL) processes. For these reasons, when scaling interconnects, process assessment metrics must ensure that process variability is included. As highlighted in literature [7–9], a realistic assessment of interconnect performance requires the separation of parameter variations caused by fundamental vari-
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Y. Travaly et al. / Microelectronic Engineering 83 (2006) 2417–2421
ations effects (impact on k-value and qCu) from those due to imperfect processing (statistical fluctuations). It is clear that key requirements for line resistance modeling consist in being able to model the actual damascene Cu resistivity and to predict future IC performance trends to enable the right choice of the suitable interconnect technology option based on the targeted application. 2. Results and discussion Interconnect behavior is characterized by electrical parameters such as resistance, capacitance and inductance. The relative importance of each of these parameters depends upon several circuit level factors of the driver interconnect load system, such as the length of interconnects, the line and driver impedance, and the time rise of the signal applied to the driver. However, for short interconnects (local), inductive effects can be neglected and a lumped or distributed interconnect RC delay model can be used. The computation of RC for a given technology node requires a separate calculation of the line-to-line capacitance (C) and the copper resistance (R) from a two-dimensional (2D) interconnect model taking into account geometry and material properties such as Cu resistivity and insulator dielectric constant. The line-toline capacitance per unit length can easily be computed using a static field solver such as Raphael [10] taking into account the conductors surrounding the wire of interest. The line resistance per unit length is however far more difficult to derive because of size-dependent effects (i.e. grain boundary and interface scattering), that impact resistivity for deep submicron dimensions. In addition to that, trench profile, barrier area, aspect ratio (AR), etc. are also becoming increasingly sensitive to process variability as scaling proceeds. All these effects should be accounted for in the calculation of the effective line resistivity qCu.
Assuming that the line height does not vary significantly within the studied line width range and considering that PCu 2 (W + H), Eq. (2) can be written as qCu 2k Rsc 2k Rsc H ¼ 1þ ð3Þ þ S Cu q0 H where H is the Cu height. Eq. (3) immediately shows that both the intercept with the y-axis of the qCu vs. 1/SCu graph and the slope depend on the line thickness. Additionally the influence of grain boundary scattering should be taken into account and is traditionally given to first order by: qCu 3k R ¼1 2rgrain 1 R qgrain
where rgrain is the grain size and R is the grain boundary reflection coefficient. The two extreme cases for rgrain that can be identified are a linear dependence on linewidth (1/ rgrain 1/W = H/SCu) i.e. growth is limited by the line dimensions, and a constant grain size i.e. complete overburden in-growth is achieved. For both these extremes and linear combinations thereof (e.g. in growth in only some parts of the line) a linear relation of qCu vs. 1/SCu is expected when a range of linewidths with constant line height are examined. Thus the total resistivity can be written in a general form as:
TM
2.1. Resisitivity modeling In [11], for a wire cross-section of arbitrary shape, the line conductance decrease with respect to the bulk conductivity rCu/r0 of a given specimen can be approximated as: rCu P Cu ¼1 k Rsc r0 S Cu
ð1Þ
where r0 represents the bulk conductivity of the metal, SCu and PCu are the specimen cross-sectional area and perimeter respectively, k the mean free path of electrons in Cu and Rsc a dimensionless constant, which captures electron scattering phenomena. Using a first order Taylor expansion on (1), the following expression, including scattering phenomena, can be derived for the ratio of Cu resisitivity to the bulk resistivity: qCu 1 ¼ 1 þ P Cu k Rsc S Cu q0
ð2Þ
ð4Þ
qCu ¼ b þ a
1 S Cu
ð5Þ
where b always depends on surface scattering and background scattering resistivity (e.g. affected by impurities and defects) but can depend on grain boundary scattering when overburden in-growth is achieved. a depends on both surface and grain boundary scattering. In this empirical model changes in Cu resistivity are therefore mainly dictated by changes in the Cu area. However, this is only valid for one line height (the same a, b parameters cannot be used for different line height). To verify experimentally this linear relationship, Matthiessen’s rule [3,4,12] were applied to determine the Cu resisitivity vs. 1/SCu (Fig. 1(a)). This is done by measuring the resistance of 0.3 lm lines with various line widths, at four different temperatures. The line width ranges from 200 nm down to 80 nm and for a wire thickness of 130 nm as derived from TEM cross-sections (Fig. 1(b)). As expected, Cu resistivity varies linearly as a function of 1/SCu with a = 0.0072 and b = 1.9357 lX cm1. Uncertainties on a and b are determined by measuring 32 dies per wafer. Most importantly, this observation enables an experimental determination of the overall (grain boundary, surface, defects, etc.) electron scattering coefficient Rsc: a ð6Þ Rsc ¼ 2k q0 H The values of a and b will be used later in this paper in the computation of interconnects RC delay. Moreover, from Fig. 1(a), uncertainties on a and b can be derived and sub-
Y. Travaly et al. / Microelectronic Engineering 83 (2006) 2417–2421
2419
Effective Resistivity (μΩ-cm)
3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3
y = 0.0072x + 1.9357 R2 = 0.9977
2.2 2.1 2.0 0
20
40
60
100
80
120
-2
1 / Cross Sectional Area (μm )
Fig. 1. (a) Cu resisitivity as a function of Cu area for a wire thickness of 130 nm and (b) TEM cross-section of the corresponding structure.
99.99 99.9
%
99 95 90 80 70 50 30 20 10 5
Experimental capacitance
1
Simulated capacitance with k = 2.9 - 3.0
.1 .01 0.1
0.15
0.2
0.25
Capacitance (pF/mm)
Fig. 2. (a) General methodoly for k-value extraction and (b) simulated and experimental capacitance for the SD-Cu/Low-k structure shown in Fig. 1(b).
sequently be used in variability studies. However, the contributions to Rsc of specific scattering mechanisms (interface scattering, grain boundary scattering, roughnessinduced scattering, etc.) remain difficult to evaluate, unless some precautions are taken to isolate a specific electron scattering process. In addition to that, a mathematical formulation of Rsc as a function of the various scattering coefficients (interface, grain boundaries, etc.) is required. The effective wire resistivity, which includes the effect of the Cu barrier, can finally be computed by taking into account the Cu barrier area and the aspect ratio according to [9]: ! 1 qeffective ¼ qCu ð7Þ Abarrier 1 ðARÞ W2 where W is the line width, Abarrier the barrier area, AR the wire aspect ratio and qCu the Cu wire resistivity calculated according to Eq. (5). 2.2. Capacitance modeling To determine the integrated k-value, our methodology consists in performing a simulation of the line-to-line capacitance. As illustrated in Fig. 2(a), in order to do so,
Fig. 3. Parameterized 2D Cu wire model used in our calculation.
Table 1 Description of model parameters Process
Input parameter
Bottom CD (Width) Trench profile (Profile) Cu height (Height) Barrier thickness (BB: bottom barrier; BW: sidewall barrier) Electron scattering Capacitance
W P H tBB, tBW a k
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Y. Travaly et al. / Microelectronic Engineering 83 (2006) 2417–2421
Width * Barrier at bottom Electron scattering Profile Sidewall barrier Bottom barrier Height Width k-value
-10
-5
0
5
10
15
20
25
Contribution of process variation to RC [a.u]
Fig. 4. Most important contributions of input parameters to RC delay variation.
from a TEM cross-section, relevant stack parameters (line width and height, trench shape, etc.) are determined and subsequently used to build-up a general model for the SD Cu/low-k structure under study. In addition, from the TEM measurements, uncertainties on line dimensions are determined (dw, dh, etc.) and then used in a full factorial DOE run for generating a simulate capacitance distribution. In this DOE run, the k-value is also varied (dk), starting from its as-deposited value, until a good match between simulated and experimental capacitance distributions is achieved (Fig. 2(b)). The value of dk is taken as a factor of merit of the given integration exercise and subsequently used for RC simulation studies. 2.3. RC modeling To calculate RC delay, we assume the most general trapezoidal-like trench profile (Fig. 3) from which barrier and Cu areas can easily be calculated. Given the effective q, the calculation of the line resistance per unit length and thereby the RC product is straightforward. Given the process parameters introduced in Fig. 3, a BEOL performance metric (f), in this case q, can be written as f = f(W, a, H, tBB, tBW, tSiC_etch, P). Table 1 describes input parameters. To study the effect of process variations, the perturbations (d) previously obtained are introduced in each process parameter. For the geometrical factors, the amplitude of the perturbation was determined from TEM cross-sections, thickness measurements or from known uncertainties of specific unit process steps, the uncertainty on a was obtained from resistivity data obtained from Matthiessen’s rule and finally, the one on k-value was derived from the line-to-line capacitance. From the full factorial DOE run, the relative contributions (or sensitivity factors) of various process parameters to the resistivity and RC delay can be derived. For interconnects RC delay (Fig. 4), an important contribution originates from the
sidewall barrier layer. This observation suggests that in the next optimization step, the focus should be on the barrier step coverage improvement. 3. Conclusion An accurate interpretation of experimental data and prediction of future performance trends require an assessment procedure that accounts for process variability. In this study, to calculate the line resistance, a novel methodology based on a linear representation of the Cu resistivity vs. 1/SCu (SCu is the Cu area) was introduced. The slope of this representation captures the net result of scattering phenomena in Cu and can be used in combination with capacitance simulations to evaluate various interconnects parameters such as RC distribution and integrated k-value. Interconnect modeling taking into account the resistivity model and the possible sources of variations in geometry and dielectric constant enables to determine the relative importance of each process parameters on BEOL performance metrics, which is valuable information in a BEOL optimization loop. This methodology can also be employed to understand the impact on R and C of process technology scaling at a system level and to enable an informed choice of the suitable interconnect technology option based on the targeted application. References [1] [2] [3] [4]
Sondheimer et al., Phys. Rev. 80 (3) (1950). Mayadas et al., Phys. Rev. B 1 (4) (1970). T.S. Kuan et al., Mat. Res. Soc. Symp. Proc. 612 (2000), D7.1.1. K. Hinode, Y. Hanaoka, K.-I. Takeda, S. Kondo, Jpn. J. Appl. Phys. 40 (2001) L1097. [5] K. Fuchs, P. Cam. Phil. Soc. 34 (1938) 100. [6] W. Steinho¨gl, G. Schindler, G. Steinlesberger, M. Traving, M. Engelhardt, J. Appl. Phys. 97 (2005) 023706. [7] N. Shigyo, IEEE T. Electron Dev. 47 (9) (2000) 174.
Y. Travaly et al. / Microelectronic Engineering 83 (2006) 2417–2421 [8] C.J. Alpert, A. Devgan, C.V. Kashyap, T. On Computer-aided design of integrated circuits and systems 5 (5) (2001) 571. [9] P. Kapur, J. Mc. Vittie, K.C. Saraswat, IEEE T. Electron Dev. 49 (4) (2002) 598.
2421
[10] Raphael – Interconnect analysis program, Synopsys, 2003. [11] R.B. Dingle, Proc. Roy. Soc. 62 (1949) 77. [12] H. Li, et al., in: Proceedings of the Advanced Metallization Conference, 1999.
A novel approach to resistivity and interconnect modeling Y. Travaly *, M. Bamal, L. Carbonell, F. Iacopi, M. Stucchi, M. Van Hove, G.P. Beyer IMEC vzw, 75 Kapeldreef, 3001 Heverlee, Belgium Available online 20 October 2006
Abstract This paper describes a simple and novel approach to calculate the line resistance of copper interconnects. The proposed methodology is simply based on a linear representation of the Cu resistivity vs. 1/SCu (SCu is the Cu cross-sectional area) in which the slope captures the net result of scattering phenomena in Cu. Ó 2006 Elsevier B.V. All rights reserved. Keywords: Copper resistivity; Modeling; RC delay; Variability
1. Introduction Accurate modeling and prediction of the resistivity of Cu thin films and damascene Cu lines have been the subject of many studies. While the existing Cu resistivity models including the effects of scattering phenomena (grain boundary, interface, surface roughness, impurities, etc.) on the resistivity of Cu thin films are generally well described [1,2], their extension to Cu lines is far more difficult. Kuan et al. [3] proposed a model based on the combined surface and grain boundary scattering effects, which depends on the line width and the grain size. However, such a model requires a detailed characterization of grain size distribution and also, does not include explicitly the line height. These limitations are overcome by Hinode et al. [4] who proposed a generalization of the Fuch and Sondheimer [5] formula for describing the resisitivity of Cu lines in terms of both line width and line thickness. Even if this model takes only into account the effect of electron-surface scattering, it already goes beyond the earlier applied equation of the simple form q = q0Ck/W, where q0 is the resistivity of bulk Cu, k is the electron mean free path and W is the line width, in the sense that the Cu height is taken into
*
Corresponding author. Tel.: +32 16 281723; fax: +32 16 281576. E-mail address: [email protected] (Y. Travaly).
0167-9317/$ - see front matter Ó 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2006.10.048
account. More recently, Steinho¨gl et al. [6] used a numerical approach, which accounts for the influence of most scattering phenomena besides the inclusion of line width and height. This is, as of today, the most complete description of resistivity of damascene Cu lines. However, even if it delivers good results in terms of measured resisitivity data fitting and interpretation, the model is quite complex and only valid for rectangular cross-sections. For instance, we calculated for 160 nm metal pitch that approximating a trapezoidal cross-section by a rectangular one (in this case using an average line for area calculation of the rectangular cross-section) leads to a 6% overestimation of cross-sectional area. Due to these limitations, it can not enable an accurate assessment of IC performance trends which should take into account process variability in dimensions and shape of wire cross-section. As a matter of fact, continuous process optimization and performance assessment are equally important to control the Cu resistivity increase. As scaling continues, process variability becomes more important, resulting in substantial statistical interconnect process fluctuations that complicate the use of existing performance metrics for backend-of-line (BEOL) processes. For these reasons, when scaling interconnects, process assessment metrics must ensure that process variability is included. As highlighted in literature [7–9], a realistic assessment of interconnect performance requires the separation of parameter variations caused by fundamental vari-
2418
Y. Travaly et al. / Microelectronic Engineering 83 (2006) 2417–2421
ations effects (impact on k-value and qCu) from those due to imperfect processing (statistical fluctuations). It is clear that key requirements for line resistance modeling consist in being able to model the actual damascene Cu resistivity and to predict future IC performance trends to enable the right choice of the suitable interconnect technology option based on the targeted application. 2. Results and discussion Interconnect behavior is characterized by electrical parameters such as resistance, capacitance and inductance. The relative importance of each of these parameters depends upon several circuit level factors of the driver interconnect load system, such as the length of interconnects, the line and driver impedance, and the time rise of the signal applied to the driver. However, for short interconnects (local), inductive effects can be neglected and a lumped or distributed interconnect RC delay model can be used. The computation of RC for a given technology node requires a separate calculation of the line-to-line capacitance (C) and the copper resistance (R) from a two-dimensional (2D) interconnect model taking into account geometry and material properties such as Cu resistivity and insulator dielectric constant. The line-toline capacitance per unit length can easily be computed using a static field solver such as Raphael [10] taking into account the conductors surrounding the wire of interest. The line resistance per unit length is however far more difficult to derive because of size-dependent effects (i.e. grain boundary and interface scattering), that impact resistivity for deep submicron dimensions. In addition to that, trench profile, barrier area, aspect ratio (AR), etc. are also becoming increasingly sensitive to process variability as scaling proceeds. All these effects should be accounted for in the calculation of the effective line resistivity qCu.
Assuming that the line height does not vary significantly within the studied line width range and considering that PCu 2 (W + H), Eq. (2) can be written as qCu 2k Rsc 2k Rsc H ¼ 1þ ð3Þ þ S Cu q0 H where H is the Cu height. Eq. (3) immediately shows that both the intercept with the y-axis of the qCu vs. 1/SCu graph and the slope depend on the line thickness. Additionally the influence of grain boundary scattering should be taken into account and is traditionally given to first order by: qCu 3k R ¼1 2rgrain 1 R qgrain
where rgrain is the grain size and R is the grain boundary reflection coefficient. The two extreme cases for rgrain that can be identified are a linear dependence on linewidth (1/ rgrain 1/W = H/SCu) i.e. growth is limited by the line dimensions, and a constant grain size i.e. complete overburden in-growth is achieved. For both these extremes and linear combinations thereof (e.g. in growth in only some parts of the line) a linear relation of qCu vs. 1/SCu is expected when a range of linewidths with constant line height are examined. Thus the total resistivity can be written in a general form as:
TM
2.1. Resisitivity modeling In [11], for a wire cross-section of arbitrary shape, the line conductance decrease with respect to the bulk conductivity rCu/r0 of a given specimen can be approximated as: rCu P Cu ¼1 k Rsc r0 S Cu
ð1Þ
where r0 represents the bulk conductivity of the metal, SCu and PCu are the specimen cross-sectional area and perimeter respectively, k the mean free path of electrons in Cu and Rsc a dimensionless constant, which captures electron scattering phenomena. Using a first order Taylor expansion on (1), the following expression, including scattering phenomena, can be derived for the ratio of Cu resisitivity to the bulk resistivity: qCu 1 ¼ 1 þ P Cu k Rsc S Cu q0
ð2Þ
ð4Þ
qCu ¼ b þ a
1 S Cu
ð5Þ
where b always depends on surface scattering and background scattering resistivity (e.g. affected by impurities and defects) but can depend on grain boundary scattering when overburden in-growth is achieved. a depends on both surface and grain boundary scattering. In this empirical model changes in Cu resistivity are therefore mainly dictated by changes in the Cu area. However, this is only valid for one line height (the same a, b parameters cannot be used for different line height). To verify experimentally this linear relationship, Matthiessen’s rule [3,4,12] were applied to determine the Cu resisitivity vs. 1/SCu (Fig. 1(a)). This is done by measuring the resistance of 0.3 lm lines with various line widths, at four different temperatures. The line width ranges from 200 nm down to 80 nm and for a wire thickness of 130 nm as derived from TEM cross-sections (Fig. 1(b)). As expected, Cu resistivity varies linearly as a function of 1/SCu with a = 0.0072 and b = 1.9357 lX cm1. Uncertainties on a and b are determined by measuring 32 dies per wafer. Most importantly, this observation enables an experimental determination of the overall (grain boundary, surface, defects, etc.) electron scattering coefficient Rsc: a ð6Þ Rsc ¼ 2k q0 H The values of a and b will be used later in this paper in the computation of interconnects RC delay. Moreover, from Fig. 1(a), uncertainties on a and b can be derived and sub-
Y. Travaly et al. / Microelectronic Engineering 83 (2006) 2417–2421
2419
Effective Resistivity (μΩ-cm)
3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3
y = 0.0072x + 1.9357 R2 = 0.9977
2.2 2.1 2.0 0
20
40
60
100
80
120
-2
1 / Cross Sectional Area (μm )
Fig. 1. (a) Cu resisitivity as a function of Cu area for a wire thickness of 130 nm and (b) TEM cross-section of the corresponding structure.
99.99 99.9
%
99 95 90 80 70 50 30 20 10 5
Experimental capacitance
1
Simulated capacitance with k = 2.9 - 3.0
.1 .01 0.1
0.15
0.2
0.25
Capacitance (pF/mm)
Fig. 2. (a) General methodoly for k-value extraction and (b) simulated and experimental capacitance for the SD-Cu/Low-k structure shown in Fig. 1(b).
sequently be used in variability studies. However, the contributions to Rsc of specific scattering mechanisms (interface scattering, grain boundary scattering, roughnessinduced scattering, etc.) remain difficult to evaluate, unless some precautions are taken to isolate a specific electron scattering process. In addition to that, a mathematical formulation of Rsc as a function of the various scattering coefficients (interface, grain boundaries, etc.) is required. The effective wire resistivity, which includes the effect of the Cu barrier, can finally be computed by taking into account the Cu barrier area and the aspect ratio according to [9]: ! 1 qeffective ¼ qCu ð7Þ Abarrier 1 ðARÞ W2 where W is the line width, Abarrier the barrier area, AR the wire aspect ratio and qCu the Cu wire resistivity calculated according to Eq. (5). 2.2. Capacitance modeling To determine the integrated k-value, our methodology consists in performing a simulation of the line-to-line capacitance. As illustrated in Fig. 2(a), in order to do so,
Fig. 3. Parameterized 2D Cu wire model used in our calculation.
Table 1 Description of model parameters Process
Input parameter
Bottom CD (Width) Trench profile (Profile) Cu height (Height) Barrier thickness (BB: bottom barrier; BW: sidewall barrier) Electron scattering Capacitance
W P H tBB, tBW a k
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Y. Travaly et al. / Microelectronic Engineering 83 (2006) 2417–2421
Width * Barrier at bottom Electron scattering Profile Sidewall barrier Bottom barrier Height Width k-value
-10
-5
0
5
10
15
20
25
Contribution of process variation to RC [a.u]
Fig. 4. Most important contributions of input parameters to RC delay variation.
from a TEM cross-section, relevant stack parameters (line width and height, trench shape, etc.) are determined and subsequently used to build-up a general model for the SD Cu/low-k structure under study. In addition, from the TEM measurements, uncertainties on line dimensions are determined (dw, dh, etc.) and then used in a full factorial DOE run for generating a simulate capacitance distribution. In this DOE run, the k-value is also varied (dk), starting from its as-deposited value, until a good match between simulated and experimental capacitance distributions is achieved (Fig. 2(b)). The value of dk is taken as a factor of merit of the given integration exercise and subsequently used for RC simulation studies. 2.3. RC modeling To calculate RC delay, we assume the most general trapezoidal-like trench profile (Fig. 3) from which barrier and Cu areas can easily be calculated. Given the effective q, the calculation of the line resistance per unit length and thereby the RC product is straightforward. Given the process parameters introduced in Fig. 3, a BEOL performance metric (f), in this case q, can be written as f = f(W, a, H, tBB, tBW, tSiC_etch, P). Table 1 describes input parameters. To study the effect of process variations, the perturbations (d) previously obtained are introduced in each process parameter. For the geometrical factors, the amplitude of the perturbation was determined from TEM cross-sections, thickness measurements or from known uncertainties of specific unit process steps, the uncertainty on a was obtained from resistivity data obtained from Matthiessen’s rule and finally, the one on k-value was derived from the line-to-line capacitance. From the full factorial DOE run, the relative contributions (or sensitivity factors) of various process parameters to the resistivity and RC delay can be derived. For interconnects RC delay (Fig. 4), an important contribution originates from the
sidewall barrier layer. This observation suggests that in the next optimization step, the focus should be on the barrier step coverage improvement. 3. Conclusion An accurate interpretation of experimental data and prediction of future performance trends require an assessment procedure that accounts for process variability. In this study, to calculate the line resistance, a novel methodology based on a linear representation of the Cu resistivity vs. 1/SCu (SCu is the Cu area) was introduced. The slope of this representation captures the net result of scattering phenomena in Cu and can be used in combination with capacitance simulations to evaluate various interconnects parameters such as RC distribution and integrated k-value. Interconnect modeling taking into account the resistivity model and the possible sources of variations in geometry and dielectric constant enables to determine the relative importance of each process parameters on BEOL performance metrics, which is valuable information in a BEOL optimization loop. This methodology can also be employed to understand the impact on R and C of process technology scaling at a system level and to enable an informed choice of the suitable interconnect technology option based on the targeted application. References [1] [2] [3] [4]
Sondheimer et al., Phys. Rev. 80 (3) (1950). Mayadas et al., Phys. Rev. B 1 (4) (1970). T.S. Kuan et al., Mat. Res. Soc. Symp. Proc. 612 (2000), D7.1.1. K. Hinode, Y. Hanaoka, K.-I. Takeda, S. Kondo, Jpn. J. Appl. Phys. 40 (2001) L1097. [5] K. Fuchs, P. Cam. Phil. Soc. 34 (1938) 100. [6] W. Steinho¨gl, G. Schindler, G. Steinlesberger, M. Traving, M. Engelhardt, J. Appl. Phys. 97 (2005) 023706. [7] N. Shigyo, IEEE T. Electron Dev. 47 (9) (2000) 174.
Y. Travaly et al. / Microelectronic Engineering 83 (2006) 2417–2421 [8] C.J. Alpert, A. Devgan, C.V. Kashyap, T. On Computer-aided design of integrated circuits and systems 5 (5) (2001) 571. [9] P. Kapur, J. Mc. Vittie, K.C. Saraswat, IEEE T. Electron Dev. 49 (4) (2002) 598.
2421
[10] Raphael – Interconnect analysis program, Synopsys, 2003. [11] R.B. Dingle, Proc. Roy. Soc. 62 (1949) 77. [12] H. Li, et al., in: Proceedings of the Advanced Metallization Conference, 1999.