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A novel LNA with noise cancellation in 4–11.5 GHz bandwidth for UWB receivers
Microelectronics Journal 88 (2019) 99–107
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A novel LNA with noise cancellation in 4–11.5 GHz bandwidth for UWB receivers Hosein Seyedi, Ramin Dehdasht-Heydari *, Saeed Roshani Department of Electrical Engineering, College of Engineering, Kermanshah Branch, Islamic Azad University, Kermanshah, Iran
A R T I C L E I N F O
A B S T R A C T
Keywords: Bandwidth enhancement CMOS LNA NF UWB
In this paper, an ultra wide band-low noise amplifier (UWB-LNA) is presented using two new noise cancellation and bandwidth enhancement techniques. The noise cancellation technique was performed using two additional transistors to a common-gate differential amplifier, while the presented amplifier provides a new concept of series inductors to increase the practical bandwidth. Simulation results demonstrate that the minimum noise figure and S21 are 2.75 dB and 21.3 1 dB, respectively. Meanwhile, the average IIP3 in the entire band is 7.5 dB m and the power consumption is 5.15 mW from a 1.2 V power supply. It should be noted that the circuit was simulated in a 65 nm TSMC RF CMOS technology at a bandwidth of 4–11.5 GHz with cadence spectre tool, and has an occupied area of 731 μm 1816 μm.
1. Introduction As the first class on the receiver's path, LNA has the most contribution on the receiver noise, and its design with low power and high gain can lead to a very cost-effective system, that all of its components along with digital parts are placed on a chip. Several factors are involved in the design of a low noise amplifier, which establishing consistency between them makes the design of such amplifier difficult [1]. The ultra-wideband LNAs structure has been considered as a proper solution to achieve ultra wideband that has attracted the attention of many designers and inventors for use in many applications such as mobile phones [1]. So far, many techniques have been proposed to increase bandwidth and noise reduction. One of these structures is distributed amplifier, which, has very good linearity and enough input-output matching in addition to ultra wide bandwidth and low noise, while these circuits have high power consumption due to sequential classes [1,2]. Further, another approach to increase bandwidth is to apply lots of resistors to increase bandwidth that is known as resistive shunt-feedback [3]. The use of common-gate arrays is another way to increase bandwidth. Although these classes have high noise, they provide a good match in the input. Also, in the conventional works [4–7], using this type of structure caused to increase power consumption significantly due to the use of sequential stages, which is an important issue when comparing the suitability and
superiority of circuits with each other. Approaches such as current-reused method has low power consumption, while it suffers from input impedance matching [8]. Accordingly, this paper targets the design of a differential cascode common-gate structure to reduce noise and increase bandwidth. To reduce LNA Noise, two transistors are used to reduce the noise figure that the noise of them can cancel by internal path of the LNA core. Another technique is used for flattening the gain by using series inductor. The rest of the paper is organized as follows. In section 2, a summary of the proposed designed circuit is expressed. In the third section, the noise cancellation technique is examined using two quantitative and qualitative views. In section 4, the bandwidth extension technique and its performance are described. Section 5 presents an explanation for IIP3 improvement. Finally in section 6, simulation results and comparison with previous related works are explained and this paper ends with conclusion in the last section. 2. Presented circuit Fig. 1 illustrates the schematic of conventional circuit that consists of the differential cascode common-gate amplifier. This circuit has input inductors of LS to eliminate the input of parasitic capacitance and increase the bandwidth in the input impedance matching as well as two LD inductors to resonate with parasitic capacitance output to increase the
* Corresponding author. E-mail addresses: [email protected] (H. Seyedi), [email protected], [email protected] (R. Dehdasht-Heydari), s_roshany@ yahoo.com (S. Roshani). https://doi.org/10.1016/j.mejo.2019.04.015 Received 26 December 2018; Received in revised form 6 April 2019; Accepted 19 April 2019 Available online 4 May 2019 0026-2692/© 2019 Elsevier Ltd. All rights reserved.
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Microelectronics Journal 88 (2019) 99–107
discussed and then its quantitative and computational views will be examined.
3.1. Qualitative view of noise cancellation Proposed circuit in Fig. 2 shows the noise cancellation technique with using two transistors and four capacitors. C1 and C2 capacitors perform two acts as shown in Fig. 3: 1 Due to ac short between source and drain of M1 by C1 and C2 , Noise of M1 doesn't inject to the gate of M5 . C1 and C2 capacitors are considered equal. 2 A part of M3 noise is injected to the gate of M5 by C2 capacitors without any change in phase of noise (positive path of the noise). Fig. 1. Schematic of conventional circuit.
After noise injection, M5 inverts the noise and injects it to the second output. Beside, M3 inverts its noise to the first output, simultaneously. Therefore, noise of M3 has the same sign in the both outputs and according to the differential view, the noise of M3 can be cancelled. M1;3 can cancel the noise of M6 and vice versa. In order to determine the concept of how the noises can be eliminated by M1;3;5 , the presented concept in Fig. 3 can be used and is shown in Fig. 4. As can be seen in Fig. 4, the modeled noise in the gate of M1 injects to the output from two paths. The first one is M1 in common-source structure, and the second one is M1 in common-drain with M6 in common-gate structure. Both of these two paths are with a negative and positive signs, respectively. As a result, noise of M1 can be cancelled by aforementioned paths by selecting the appropriate transconductance for M1;3;5 transistors which is investigated in the next subsection. Also for M6 noise cancellation, there is two path. The first one is M6 in common-source structure, and the second path includes: common-drain path of M6 , M1 in common-gate structure and common-gate path of M3 . Both of these two paths are with a negative and positive signs, respectively. As a result, noise of M6 can be cancelled
gain. This circuit has high noise figure due to the presence of four inductors and four transistors. Also, output capacitor has a resonance frequency which causes the circuit acts the same as a narrow band circuit due to being fixed. Therefore, it can be mentioned that two main subjects in this circuit are very low bandwidth and very high noise figure. Fig. 2 shows the schematic view of the proposed circuit. In this circuit, two techniques have been used to increase the bandwidth (top dashed box) and improve the noise figure (bottom dashed box). These two techniques will be explained in detail qualitatively and quantitatively, in terms of the noise cancellation in 3.1 and 3.2 subsections respectively and bandwidth enhancement techniques is described section 4. 3. Noise cancellation technique This section is divided into qualitative and quantitative sections of noise cancellation technique. First, the qualitative perspective is
Fig. 2. Schematic of proposed circuit. 100
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NF ¼ 10logFTotal
(2)
It should be noted that AV is equal to: AV ¼ ðgm1 þ gm3 þ gm6 ÞRL
(3)
Noise of M 1 transistor Noise of M1 is equal to:
V 2n;out1;M1
Fig. 3. Half-circuit schematic of proposed circuit to show M1 noise cancellation by C1 and C2 capacitors in the gate of M5 and also M3 noise invertion and injection to the second output by M5 and C2 .
0commondrain z}|{ Rs B B 2 ¼B B Rs þ 1 @ 2 gm1
12
commonsource commongate
zfflffl}|fflffl{ gm6 RL
zffl}|ffl{ 1 gm3 1 Rs þ gm1
commongateC
zfflffl}|fflffl{ C 2 gm3 RL C C V n;M1 A
(4)
In order to match the input, it is assumed that 1 1 1 1 ¼ gm2 ¼ gm5 ¼ gm6 and for easy calculation gm3 ¼ gm4 . So M1 2Rs ¼ gm1 noise is as follows: V 2n;out1;M1 ¼
2 4KTγR2L gm6 2gm1 gm1 2 3
(5)
Given the assumption gm3 ¼ gm4 , M1 noise is not completely cancelled. In general, it has been assumed that in order to match the input impedance, gm3 ¼ gm4 , that the maximum power can be transmitted to the input, but the matching condition can be satisfied and the M1 can be cancelled, so that the following equation can be holds: gm6 2gm1 ¼0 2 3
(6)
So that, gm6 ¼ Fig. 4. Half circuit schematic to show M1 noise cancellation by M6 transistor and vice versa.
(7)
This means that the value of gm1 is slightly smaller than gm6 and that the values of gm1 and gm6 are chosen so that the input impedance matching is provided as follows:
by aforementioned paths. It should be noted that the gain of positive and negative paths should be exactly the same by selecting the good dimension for the transistors. It should be noted that the positive and negative paths in Figs. 3 and 4, mean the noise is non-inverted and inverted, respectively with respect to the common port of transistors.
1 1 k ¼ Rs gm1 gm6
(8)
Noise of M 3 transistor Given that C1 and C2 in Fig. 5 has created an ac path from the source to M1 and M2 drains. When the noise flows from drain to the source or vice versa, the C1 and C2 paths are the only way to transmit noise, and the gain of this path is approximately considered 1 with respect to the large chosen capacitors. Therefore, M3 noise is as follows at outputs 1 and 2:
3.2. Quantitative view of noise cancellation In order to demonstrate how to reduce noise quantitatively, according to Fig. 5, V 2n;out is first obtained for each transistor, then using formula (1) [9] and the sum of V 2n;out , noise factor (F) is obtained: 1 V 2n;out A @ FTotal ¼ 1 þ AV 4KTRs
4gm1 3
0
(1)
V 2n;out1;M3 ¼
RL Rout1 þ g R 1 1 m6 L Rout1 þ gm3 Rout1 þ gm3
!2 V 2n;M3
(9)
where Rs denotes the series resistance of input source and AV is gain. Another thing is the relation between noise factor and noise figure which can be expressed as follows:
0 commondrain
commondrain 12 zfflfflfflfflfflfflffl ffl{ 0 1 ffl}|fflfflfflfflfflfflffl commongate 1 zfflffl ffl }|fflffl ffl { z}|{ capacitor path commongateC k Rs B z}|{ RL 1 C g B C zfflffl}|fflffl{ C 2 þ m2 þ gm2 1 B C gm4 RL C C V n;M3 1 1 1 @ g m4 A A þ k Rs þ gm5 k R s gm2 gm5
commonsource
B zffl}|ffl{ B Rout1 V 2n;out2;M3 ¼ B BRout1 þ 1 1 @ gm3 g
m2
101
(10)
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Microelectronics Journal 88 (2019) 99–107
Fig. 5. A model for noise contribution in the proposed circuit.
To remove the M3 noise, the following condition must be met:
Given that an ac path has been created through two C1 and C2 capacitors, the Rout1 value can be considered as follows:
gm4 ¼
1 2 Rout1 Rs k ¼ Rs gm6 3
(11)
5 3Rs
(15)
Noise of M 5 transistor The noise related to M5 is as follows:
So:
0
commonsource
zfflfflfflfflfflfflffl ffl{ ffl}|fflfflfflfflfflfflffl 1 z}|{ k Rs RL g þ m2 1 1 1 k Rs þ gm5 k Rs þ gm5 gm2
commonsource
B B V 2n;out2;M5 ¼ B B 1 @ g
m2
V 2n;out1;M3
V 2n;out1;M3
4 RL ¼ 9 Rs þ 2g3m3
0 B B B @
commongate
capacitor path
z}|{ 1
zfflfflffl}|fflfflffl{ 1 þ gm2 gm4
4 RL 9 Rs þ 2g3m3
commongateC
C zfflffl}|fflffl{ C C gm4 RL A
C 2 CV C n;M5 A
(16)
!2 V 2n;M3
!2
4KTγ þ gm3
0
(12)
!2 2 4 RL Rs ðgm4 þ gm2 Þ 1 ¼ V 2n;m3 3 9 Rs þ 2gm3 6 4
V 2n;out1;M3 ¼
12
1
! 2 Rs ðgm4 þ gm2 Þ 1 4 6 4 9
V 2n;out2;m5
¼@
(13) V 2n;out2;m5 ¼
12 RL 2 A V n;m5 2 1 2 R þ gm5 R ðg þ gm2 Þ 1 3 3 s m4
2 19 RL 4KTγ 8 RS gm5
(14) To remove M5 noise, the following condition must be satisfied: 102
(17)
(18)
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Microelectronics Journal 88 (2019) 99–107
1 0 V 2n;out;M1;2 þ V 2n;out;M5;6 V 2n;out;M1;2 V 2n;out;M5;6 A¼1þ @ FTotal ¼ 1 þ þ 2 2 2 AV 4KTRs AV 4KTRs AV 4KTRs þ
V 2n;RL A2V
4KTRs (25)
On the other hand, mode 1 and Eq. (23) do not have any consistency with each other, and since input matching is more important, it is better to use Eq. (23). By using Eq. (23), M1;2 noise decreases significantly. To investigate this quantitatively, the second term of Eq. (25) is calculated: Fig. 6. A comparison between the ideal and the real inductors.
gm4 ¼
V 2n;out;M1;2
1 Rs
AV 2 4KTRs
(19)
V 2n;out;M5;6 AV 2 4KTRs
(20)
V 2n;RL 2
5 3Rs
AV 4KTRs
(21)
1 Rs
1 gm1:2:5;6
2g3m1
2
4KTRs ððgm1 þ gm3 þ gm6 ÞRL Þ2
¼
4KTγ gm5
19 RL 8 Rs
¼
γ 30
(26)
2
4KTRs ððgm1 þ gm3 þ gm6 ÞRL Þ2
¼
¼
γ 0:96
4KTRL 3 ¼ 4KTRs ððgm1 þ gm3 þ gm6 ÞRL Þ2 5RL
γ γ 3 þ þ FTotal ¼ 1 þ 2 60 0:96 5RL
(22)
(27)
(28)
(29)
Obtained Eq. (29) is resulted when the expressed conditions in the circuit and the relationships between the transconductance of transistors are fully met.
On the other hand, another condition had existed in the past that includes: gm3 ¼ gm4 2Rs ¼
2
The written value of FTotal in Eq. (25) is for half-circuit concept, so FTotal can be obtained by multiplying this equation in 2:
To cancel the of noise M5;6 : gm3;4 ¼
gm6
And the noise of tank circuit (RL ) is:
To cancel the noise of M3;4 : gm3;4 ¼
4KTγR2L gm1
On the other hand, the third term of Eq. (25) is equal to:
In short, there are three conditions for removing the circuit noise that include: To cancel noise M1;2 : 4 gm5;6 ¼ gm1;2 3
¼
(23) 4. Bandwidth enhancement technique
Conditions (21) and (22) cannot be hold simultaneously, so three modes can be done:
This method can be called “series inductor” which can be used to increase bandwidth by using its feature (real model) during the circuit fabrication. An ideal inductor is free from any parasitic element, meanwhile the fabricated inductors on the chip have a series resistance and a parallel capacitor as shown in Fig. 6, so that R is the inductance path resistance and C is created parasitic capacitor on two heads of inductor. If an inductor is placed on the output, the capacitor C becomes parallel with the output capacitance of the circuit and causes the circuit to resonate with inductor at a specific frequency, and high impedance is produced that increases the gain at the desired frequency. By sequencing several inductors, the bandwidth and resonance frequency can be extended and increased in the whole of the bandwidth (see Fig. 7). This is because of the fact that each time one of the inductors resonate with a parasitic capacitor on its two heads, it creates high impedance at each frequency and range of that frequency. By changing
1. Use condition (21) to calculate FTotal . 2. Use condition (22) to calculate FTotal . 3. Averaging the median of the two conditions to calculate FTotal . According to studies, the second mode is the best way to reduce noise. So FTotal is: 0 1 V 2n;out;M1;2 þ V 2n;out;M3;4 þ V 2n;out;M5;6 þ V 2n;RL A FTotal ¼ 1 þ @ AV 2 4KTRs
(24)
According to mode 2, V 2n;out;M3;4 is deleted. So we have:
Fig. 7. Schematic of real model of bandwidth enhancement technique that is name series inductors. 103
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Fig. 8. The IIP3 cancellation mechanism.
Fig. 9. S21 parameter in 4–11.5 GHz bandwidth in Pre-Layout and Post-Layout modes.
Fig. 10. NF parameter in 4–11.5 GHz bandwidth in Pre-Layout and Post-Layout modes. Also, the input impedance matching parameter (S11) in the whole of the bandwidth is shown in Fig. 11, which is less than 10dB. 104
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Fig. 11. S11 parameter in 4–11.5 GHz bandwidth in Pre-Layout and Post-Layout modes.
Fig. 12. IIP3 parameter at 5 GHz frequency with 10 MHz two tone space in Post-Layout mode.
Fig. 13. IIP3 value at 4–11.5 GHz bandwidth in Post-Layout mode.
the input frequency, the first inductor is removed from the circuit and the next inductor is added to the circuit so that it can maintain the resonance operation and the gain increases. With more inductors, the more resonant frequencies can be obtained, resulting the wider bandwidth. This is the case when the number of inductors does not lead to the noise increasing due to the existence of series resistors in each inductor. Because each time one of the inductors is in resonance mode and generates high impedance, the resistance of the other inductors is insignificant against the high created impedance. This impedance is parallel with the relatively lower impedance of LNA output, and in principle, the output resistance of the LNA has been the main resistance of the circuit
that causes the bandwidth of circuit to remain constant. In the proposed LNA, 6 inductors are used in each output, which is a total of 12 inductors. It is not necessary to run each inductor one after the other and it can be probable the first inductor act as the number one and then it follows with the inductor number three. For this reason, in order to get the best bandwidth, the inductors are tuned during simulation operation and its results are demonstrated in section 5. 5. IIP3 investigation Due to extra transistors (M5 and M6 ) structure, the IIP3 can be
105
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Fig. 14. Layout of circuit with occupied space of 731 μm 1816 μm.
6. Simulation results
Table 1 Element values and bias circuit voltages. parameter
Value
parameter
Value
M1;2
6μm =0:06μm
L6
M3;4
5μm =0:06μm
LS
M5:6 L1
28μm =0:06μm 6.7 nH @5 GHz (Q ¼ 11.1)
L2
3.37 nH @5 GHz (Q ¼ 14.8) 1.2 nH @5 GHz (Q ¼ 10.4) 1.38 nH @5 GHz (Q ¼ 11.02) 4.43 nH @5 GHz (Q ¼ 12.5)
C1;2 RB (OffChip) VB1
5.8 nH @5 GHz (Q ¼ 11.4) 2.1 nH @5 GHz (Q ¼ 11.6) 2.6 pF 50 kΩ
L3 L4 L5
The presented circuit in Fig. 2 is simulated using a 65 nm TSMC RF CMOS technology by a 1.2v supply voltage with cadence spectre tool. The simulated parameters include the S21, the noise figure (NF), S11, and IIP3 in the bandwidth of 4–11.5 GHz. The simulation results include the pre-layout and post-layout modes. The results of each case are reported in the simulation of these two modes. The S21 parameter is shown in Fig. 9. As shown in Fig. 9, the average gain value is 21.3 1 dB. The gain deviations are shown the switching of the inductors at different frequencies, which is very low deviation so that the gain can be considered as a flat range in the entire operating bandwidth. By assuming γ 1, the noise figure in the calculation is assumed to be less than 3 dB by considering the sub-micron feature of the technology. The NF value for the whole bandwidth is shown in Fig. 10 which indicates NF value is less than 3 dB. Also, the minimum NF is 2.75 dB. The IIP3 value of the circuit at a frequency of 5 GHz, which it is the highest gain, is 6.5 dB m. To simulate, 10 MHz frequency is considered for two tone space. The simulation results of the IIP3 are shown in Fig. 12. Also, in order to evaluate IIP3 in the whole band, the value of this parameter has been swept across the entire band (see Fig. 13), indicating that this parameter is high in the whole band. As shown in Fig. 13, the value of IIP3 at 5 GHz frequency has the minimum value. Fig. 14 is a view of the proposed LNA layout. As previously
300 mV
VB2 VB3
1.2 V 600 mV
Vdd
1.2 V
improved. As shown in Fig. 8, M1 and M2 produce intermodulation signals in the M5 and M6 gates. Gate-source voltages of extra transistors are formed from fundamental signals minus the intermodulation þ fundamental signals which are resulted intermodulation signals in output current of M5 and M6 . This currents are added to the output nodes to cancel the intermodulation signals in the main paths (M13 and M24 ) with opposite phase.
Table 2 A comparison between this work and conventional ones. Ref.
Tech. (μm)
BW (GHz)
S11 (dB)
S21 (dB)
NFmin (dB)
IIP3 (dBm)
Pdiss (mW)
Die size (mm2 )
FOM1 ðGHz =mWÞ
FOM2 ðGHz =mWÞ
AEU-2014 [12] MEJO-2015 [13] MEJO-2018 [14] MEJO-2017 [15] AEU-2015 [16] AEU-2017 [17] AEU-2018 [18] This work
0.13 0.09 0.18 0.18 0.18 0.18 0.18 0.065
2.35–9.37 2.4–10.4 0.6–3.15 2.8–7.5 2.3–4.8 0.8–10.4 0.3–3.5 4–11.5
<-8 <-11 <-13.5 <-8 <-10 <-9 <-10 <-10
10.31 9.2 20.2 13 24 13.7 14.6 21
3.68 3.5 2.8 3.6 2.8 3 2.9 2.75
4 13.1 4.2 10.5 3.2 10.3 1.2 6.5
9.97 14.8 6 3.8 13.1 7.2 14.8 5.15
0.39 0.437 0.026 0.77 0.34 0.19 0.275 1.32
3.15 1.26 4.82 4.32 3.33 6.48 1.21 18.49
1.26 25.72 1.83 0.39 1.59 69.46 1.59 82.65
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mentioned, 12 inductors were used in output to improve bandwidth. One of the advantages of this technique is that by adding more inductors, one can help considerably to increase the bandwidth, while not causing suffer from the increasing of noise figure of the proposed circuit. The only problem of this method is more occupied area which can be greatly reduced by the use of more advanced technologies. The occupied space of the drawn Layout is 731 μm 1816 μm. Table 1 shows the values of the used elements in the circuit, including bias-voltages of circuits that the values are obtained by an optimization. Also in Table 2, a comparison is done between this work and conventional works. It should be noted that the amount of occupied space has not changed significantly in comparison with conventional works. In Table 2, the value of FOM1 [10] and FOM2 [11] are reported by using the following formulas, which have been used in several papers.
GHz S21 BW½GHz ¼ FOM1 mW ðF 1Þ PD ½mW FOM2
GHZ s21 BW½GHZ ІІP3½mW ¼ ðF 1Þ pD ½mW mW
[8]
[9] [10]
[11]
[12]
[13]
[14]
(30) [15]
[16]
(31)
[17]
7. Conclusion [18]
In this paper, a UWB-LNA circuit is designed and simulated in a 65 nm TSMC CMOS RF technology using a 1.2v power supply with a power consumption of 5.15 mW with cadence spectre tool. Noise cancellation and bandwidth enhancements methods are presented in this work. By adding two transistors, in addition the noise of LNA is canceled, the LNA can cancel the noise of excess transistors. Furthermore, using series inductors can flat the bandwidth without any coupling between the inductors and switches to select the specified band. Noise cancellation method has reached the lowest noise figure of 2.75 dB in the differential cascode common gate. While the presented series inductors method offers a bandwidth of 4–11.5 GHz with gain of 21 dB. Another benefit of this technique is that can be used for higher bandwidth by adding more inductors. It should be noted that the minimum amount of IIP3 in the whole of bandwidth is 6.5 dB m. The occupied space is 731 μm 1816 μm and the results are reported in the Pre-Layout and Post-Layout modes.
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Hosein Seyedi was born in a historical city in KermanshahIran, in 1990. He received the B.sc and M.sc degrees in Electrical Engineering in 2012 and 2014 from Kermanshah and Science & Research Branches of Islamic Azad University respectively. He is now working toward Ph.D. thesis in Kermanshah Branch, Islamic Azad University. His fields of interest are CMOS and RFIC design circuits. Also, he has been the manager of a section related to communication devices and BTS mobile antennas during 2016–2018 years.
Ramin Dehdasht-Heydari was born in a beautiful city in Esfahan-Iran, in 1983. He received the Ph.D. degree in Electrical Engineering in 2013 from Science & Research Branch, Islamic Azad University, Tehran-Iran. He worked as a guest researcher at Aalborg University of Denmark during 2012. He currently is an assistant professor at the Telecommunication Group of Kermanshah Branch, Islamic Azad University, Kermanshah-Iran. Dr. Dehdasht-Heydari is the author of 4 books regarding electrical and IT engineering as well as some research papers. Also, he is the reviewer of Applied Computational Electromagnetics Society (ACES) and Transactions of the Institute of Measurement and Control journals. His principal fields of interest in research are UWB antennas, microwave and millimeter wave circuits, wireless, cellular & optical networks, and numerical electromagnetism methods.
Appendix A. Supplementary data Supplementary data to this article can be found online at https://do i.org/10.1016/j.mejo.2019.04.015. References [1] Jin-Fa Chang, Yo-Sheng Lin, A high-performance distributed amplifier using multiple noise suppression techniques, Microw. Wirel. Compon. Lett. IEEE 21 (9) (2011) 495–497. [2] Jin-Fa Chang, Yo-Sheng Lin, A DC-10.5-GHz CMOS distributed amplifier with 3.20.3 dB NF 10.51.4 dB gain and 13.8 ps Group delay variation, in: Radio and Wireless Symposium (RWS) 2011 IEEE, 2011, pp. 307–310. [3] T.Y. Chang, et al., A packaged and ESD protected inductorless 0.1 to 8 GHz wideband CMOS LNA, IEEE Microw. Wirel. Compon. Lett. 18 (No. 6) (2008) 416–418. [4] C.-F. Liao, S.-I. Liu, A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver, in: Proc. IEEE 2005 Custom Integrated Circuits Conf. (CICC), Sept. 18-21, 2005, pp. 160–163. [5] Yiming Yu, Kai Kang, Yiming Fan, Chenxi Zhao, Huihua Liu, Yunqiu Wu, YongLing Ban, Wen-Yan Yin, Analysis and design of inductorless wideband low-noise amplifier with noise cancellation technique, Access IEEE 5 (2017) 9389–9397. [6] Lanqi Liu, Zhaojing Lu, Kefeng Zhang, Zhixiong Ren, Ang Hu, Xuecheng Zou, Wideband balun-LNA exploiting noise cancellation and gm compensation technique, Electron. Lett. 52 (8) (2016) 673–674. [7] Kefeng Han, Liang Zou, Youchun Liao, Hao Mi, Zhangwen Tang, A wideband CMOS variable gain low noise amplifier based on single-to-differential stage for TV tuner
Saeed Roshani received the B.Sc. degree in Electrical Engineering from Razi University, Kermanshah, Iran in 2008, M.Sc. degree in Electrical Engineering from Shahed University, Tehran, Iran in 2011 and Ph.D. in Electrical Engineering from Razi University in 2015. His research interest includes the microwave and millimeter wave devices and circuits.
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A novel LNA with noise cancellation in 4–11.5 GHz bandwidth for UWB receivers Hosein Seyedi, Ramin Dehdasht-Heydari *, Saeed Roshani Department of Electrical Engineering, College of Engineering, Kermanshah Branch, Islamic Azad University, Kermanshah, Iran
A R T I C L E I N F O
A B S T R A C T
Keywords: Bandwidth enhancement CMOS LNA NF UWB
In this paper, an ultra wide band-low noise amplifier (UWB-LNA) is presented using two new noise cancellation and bandwidth enhancement techniques. The noise cancellation technique was performed using two additional transistors to a common-gate differential amplifier, while the presented amplifier provides a new concept of series inductors to increase the practical bandwidth. Simulation results demonstrate that the minimum noise figure and S21 are 2.75 dB and 21.3 1 dB, respectively. Meanwhile, the average IIP3 in the entire band is 7.5 dB m and the power consumption is 5.15 mW from a 1.2 V power supply. It should be noted that the circuit was simulated in a 65 nm TSMC RF CMOS technology at a bandwidth of 4–11.5 GHz with cadence spectre tool, and has an occupied area of 731 μm 1816 μm.
1. Introduction As the first class on the receiver's path, LNA has the most contribution on the receiver noise, and its design with low power and high gain can lead to a very cost-effective system, that all of its components along with digital parts are placed on a chip. Several factors are involved in the design of a low noise amplifier, which establishing consistency between them makes the design of such amplifier difficult [1]. The ultra-wideband LNAs structure has been considered as a proper solution to achieve ultra wideband that has attracted the attention of many designers and inventors for use in many applications such as mobile phones [1]. So far, many techniques have been proposed to increase bandwidth and noise reduction. One of these structures is distributed amplifier, which, has very good linearity and enough input-output matching in addition to ultra wide bandwidth and low noise, while these circuits have high power consumption due to sequential classes [1,2]. Further, another approach to increase bandwidth is to apply lots of resistors to increase bandwidth that is known as resistive shunt-feedback [3]. The use of common-gate arrays is another way to increase bandwidth. Although these classes have high noise, they provide a good match in the input. Also, in the conventional works [4–7], using this type of structure caused to increase power consumption significantly due to the use of sequential stages, which is an important issue when comparing the suitability and
superiority of circuits with each other. Approaches such as current-reused method has low power consumption, while it suffers from input impedance matching [8]. Accordingly, this paper targets the design of a differential cascode common-gate structure to reduce noise and increase bandwidth. To reduce LNA Noise, two transistors are used to reduce the noise figure that the noise of them can cancel by internal path of the LNA core. Another technique is used for flattening the gain by using series inductor. The rest of the paper is organized as follows. In section 2, a summary of the proposed designed circuit is expressed. In the third section, the noise cancellation technique is examined using two quantitative and qualitative views. In section 4, the bandwidth extension technique and its performance are described. Section 5 presents an explanation for IIP3 improvement. Finally in section 6, simulation results and comparison with previous related works are explained and this paper ends with conclusion in the last section. 2. Presented circuit Fig. 1 illustrates the schematic of conventional circuit that consists of the differential cascode common-gate amplifier. This circuit has input inductors of LS to eliminate the input of parasitic capacitance and increase the bandwidth in the input impedance matching as well as two LD inductors to resonate with parasitic capacitance output to increase the
* Corresponding author. E-mail addresses: [email protected] (H. Seyedi), [email protected], [email protected] (R. Dehdasht-Heydari), s_roshany@ yahoo.com (S. Roshani). https://doi.org/10.1016/j.mejo.2019.04.015 Received 26 December 2018; Received in revised form 6 April 2019; Accepted 19 April 2019 Available online 4 May 2019 0026-2692/© 2019 Elsevier Ltd. All rights reserved.
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discussed and then its quantitative and computational views will be examined.
3.1. Qualitative view of noise cancellation Proposed circuit in Fig. 2 shows the noise cancellation technique with using two transistors and four capacitors. C1 and C2 capacitors perform two acts as shown in Fig. 3: 1 Due to ac short between source and drain of M1 by C1 and C2 , Noise of M1 doesn't inject to the gate of M5 . C1 and C2 capacitors are considered equal. 2 A part of M3 noise is injected to the gate of M5 by C2 capacitors without any change in phase of noise (positive path of the noise). Fig. 1. Schematic of conventional circuit.
After noise injection, M5 inverts the noise and injects it to the second output. Beside, M3 inverts its noise to the first output, simultaneously. Therefore, noise of M3 has the same sign in the both outputs and according to the differential view, the noise of M3 can be cancelled. M1;3 can cancel the noise of M6 and vice versa. In order to determine the concept of how the noises can be eliminated by M1;3;5 , the presented concept in Fig. 3 can be used and is shown in Fig. 4. As can be seen in Fig. 4, the modeled noise in the gate of M1 injects to the output from two paths. The first one is M1 in common-source structure, and the second one is M1 in common-drain with M6 in common-gate structure. Both of these two paths are with a negative and positive signs, respectively. As a result, noise of M1 can be cancelled by aforementioned paths by selecting the appropriate transconductance for M1;3;5 transistors which is investigated in the next subsection. Also for M6 noise cancellation, there is two path. The first one is M6 in common-source structure, and the second path includes: common-drain path of M6 , M1 in common-gate structure and common-gate path of M3 . Both of these two paths are with a negative and positive signs, respectively. As a result, noise of M6 can be cancelled
gain. This circuit has high noise figure due to the presence of four inductors and four transistors. Also, output capacitor has a resonance frequency which causes the circuit acts the same as a narrow band circuit due to being fixed. Therefore, it can be mentioned that two main subjects in this circuit are very low bandwidth and very high noise figure. Fig. 2 shows the schematic view of the proposed circuit. In this circuit, two techniques have been used to increase the bandwidth (top dashed box) and improve the noise figure (bottom dashed box). These two techniques will be explained in detail qualitatively and quantitatively, in terms of the noise cancellation in 3.1 and 3.2 subsections respectively and bandwidth enhancement techniques is described section 4. 3. Noise cancellation technique This section is divided into qualitative and quantitative sections of noise cancellation technique. First, the qualitative perspective is
Fig. 2. Schematic of proposed circuit. 100
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NF ¼ 10logFTotal
(2)
It should be noted that AV is equal to: AV ¼ ðgm1 þ gm3 þ gm6 ÞRL
(3)
Noise of M 1 transistor Noise of M1 is equal to:
V 2n;out1;M1
Fig. 3. Half-circuit schematic of proposed circuit to show M1 noise cancellation by C1 and C2 capacitors in the gate of M5 and also M3 noise invertion and injection to the second output by M5 and C2 .
0commondrain z}|{ Rs B B 2 ¼B B Rs þ 1 @ 2 gm1
12
commonsource commongate
zfflffl}|fflffl{ gm6 RL
zffl}|ffl{ 1 gm3 1 Rs þ gm1
commongateC
zfflffl}|fflffl{ C 2 gm3 RL C C V n;M1 A
(4)
In order to match the input, it is assumed that 1 1 1 1 ¼ gm2 ¼ gm5 ¼ gm6 and for easy calculation gm3 ¼ gm4 . So M1 2Rs ¼ gm1 noise is as follows: V 2n;out1;M1 ¼
2 4KTγR2L gm6 2gm1 gm1 2 3
(5)
Given the assumption gm3 ¼ gm4 , M1 noise is not completely cancelled. In general, it has been assumed that in order to match the input impedance, gm3 ¼ gm4 , that the maximum power can be transmitted to the input, but the matching condition can be satisfied and the M1 can be cancelled, so that the following equation can be holds: gm6 2gm1 ¼0 2 3
(6)
So that, gm6 ¼ Fig. 4. Half circuit schematic to show M1 noise cancellation by M6 transistor and vice versa.
(7)
This means that the value of gm1 is slightly smaller than gm6 and that the values of gm1 and gm6 are chosen so that the input impedance matching is provided as follows:
by aforementioned paths. It should be noted that the gain of positive and negative paths should be exactly the same by selecting the good dimension for the transistors. It should be noted that the positive and negative paths in Figs. 3 and 4, mean the noise is non-inverted and inverted, respectively with respect to the common port of transistors.
1 1 k ¼ Rs gm1 gm6
(8)
Noise of M 3 transistor Given that C1 and C2 in Fig. 5 has created an ac path from the source to M1 and M2 drains. When the noise flows from drain to the source or vice versa, the C1 and C2 paths are the only way to transmit noise, and the gain of this path is approximately considered 1 with respect to the large chosen capacitors. Therefore, M3 noise is as follows at outputs 1 and 2:
3.2. Quantitative view of noise cancellation In order to demonstrate how to reduce noise quantitatively, according to Fig. 5, V 2n;out is first obtained for each transistor, then using formula (1) [9] and the sum of V 2n;out , noise factor (F) is obtained: 1 V 2n;out A @ FTotal ¼ 1 þ AV 4KTRs
4gm1 3
0
(1)
V 2n;out1;M3 ¼
RL Rout1 þ g R 1 1 m6 L Rout1 þ gm3 Rout1 þ gm3
!2 V 2n;M3
(9)
where Rs denotes the series resistance of input source and AV is gain. Another thing is the relation between noise factor and noise figure which can be expressed as follows:
0 commondrain
commondrain 12 zfflfflfflfflfflfflffl ffl{ 0 1 ffl}|fflfflfflfflfflfflffl commongate 1 zfflffl ffl }|fflffl ffl { z}|{ capacitor path commongateC k Rs B z}|{ RL 1 C g B C zfflffl}|fflffl{ C 2 þ m2 þ gm2 1 B C gm4 RL C C V n;M3 1 1 1 @ g m4 A A þ k Rs þ gm5 k R s gm2 gm5
commonsource
B zffl}|ffl{ B Rout1 V 2n;out2;M3 ¼ B BRout1 þ 1 1 @ gm3 g
m2
101
(10)
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Fig. 5. A model for noise contribution in the proposed circuit.
To remove the M3 noise, the following condition must be met:
Given that an ac path has been created through two C1 and C2 capacitors, the Rout1 value can be considered as follows:
gm4 ¼
1 2 Rout1 Rs k ¼ Rs gm6 3
(11)
5 3Rs
(15)
Noise of M 5 transistor The noise related to M5 is as follows:
So:
0
commonsource
zfflfflfflfflfflfflffl ffl{ ffl}|fflfflfflfflfflfflffl 1 z}|{ k Rs RL g þ m2 1 1 1 k Rs þ gm5 k Rs þ gm5 gm2
commonsource
B B V 2n;out2;M5 ¼ B B 1 @ g
m2
V 2n;out1;M3
V 2n;out1;M3
4 RL ¼ 9 Rs þ 2g3m3
0 B B B @
commongate
capacitor path
z}|{ 1
zfflfflffl}|fflfflffl{ 1 þ gm2 gm4
4 RL 9 Rs þ 2g3m3
commongateC
C zfflffl}|fflffl{ C C gm4 RL A
C 2 CV C n;M5 A
(16)
!2 V 2n;M3
!2
4KTγ þ gm3
0
(12)
!2 2 4 RL Rs ðgm4 þ gm2 Þ 1 ¼ V 2n;m3 3 9 Rs þ 2gm3 6 4
V 2n;out1;M3 ¼
12
1
! 2 Rs ðgm4 þ gm2 Þ 1 4 6 4 9
V 2n;out2;m5
¼@
(13) V 2n;out2;m5 ¼
12 RL 2 A V n;m5 2 1 2 R þ gm5 R ðg þ gm2 Þ 1 3 3 s m4
2 19 RL 4KTγ 8 RS gm5
(14) To remove M5 noise, the following condition must be satisfied: 102
(17)
(18)
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1 0 V 2n;out;M1;2 þ V 2n;out;M5;6 V 2n;out;M1;2 V 2n;out;M5;6 A¼1þ @ FTotal ¼ 1 þ þ 2 2 2 AV 4KTRs AV 4KTRs AV 4KTRs þ
V 2n;RL A2V
4KTRs (25)
On the other hand, mode 1 and Eq. (23) do not have any consistency with each other, and since input matching is more important, it is better to use Eq. (23). By using Eq. (23), M1;2 noise decreases significantly. To investigate this quantitatively, the second term of Eq. (25) is calculated: Fig. 6. A comparison between the ideal and the real inductors.
gm4 ¼
V 2n;out;M1;2
1 Rs
AV 2 4KTRs
(19)
V 2n;out;M5;6 AV 2 4KTRs
(20)
V 2n;RL 2
5 3Rs
AV 4KTRs
(21)
1 Rs
1 gm1:2:5;6
2g3m1
2
4KTRs ððgm1 þ gm3 þ gm6 ÞRL Þ2
¼
4KTγ gm5
19 RL 8 Rs
¼
γ 30
(26)
2
4KTRs ððgm1 þ gm3 þ gm6 ÞRL Þ2
¼
¼
γ 0:96
4KTRL 3 ¼ 4KTRs ððgm1 þ gm3 þ gm6 ÞRL Þ2 5RL
γ γ 3 þ þ FTotal ¼ 1 þ 2 60 0:96 5RL
(22)
(27)
(28)
(29)
Obtained Eq. (29) is resulted when the expressed conditions in the circuit and the relationships between the transconductance of transistors are fully met.
On the other hand, another condition had existed in the past that includes: gm3 ¼ gm4 2Rs ¼
2
The written value of FTotal in Eq. (25) is for half-circuit concept, so FTotal can be obtained by multiplying this equation in 2:
To cancel the of noise M5;6 : gm3;4 ¼
gm6
And the noise of tank circuit (RL ) is:
To cancel the noise of M3;4 : gm3;4 ¼
4KTγR2L gm1
On the other hand, the third term of Eq. (25) is equal to:
In short, there are three conditions for removing the circuit noise that include: To cancel noise M1;2 : 4 gm5;6 ¼ gm1;2 3
¼
(23) 4. Bandwidth enhancement technique
Conditions (21) and (22) cannot be hold simultaneously, so three modes can be done:
This method can be called “series inductor” which can be used to increase bandwidth by using its feature (real model) during the circuit fabrication. An ideal inductor is free from any parasitic element, meanwhile the fabricated inductors on the chip have a series resistance and a parallel capacitor as shown in Fig. 6, so that R is the inductance path resistance and C is created parasitic capacitor on two heads of inductor. If an inductor is placed on the output, the capacitor C becomes parallel with the output capacitance of the circuit and causes the circuit to resonate with inductor at a specific frequency, and high impedance is produced that increases the gain at the desired frequency. By sequencing several inductors, the bandwidth and resonance frequency can be extended and increased in the whole of the bandwidth (see Fig. 7). This is because of the fact that each time one of the inductors resonate with a parasitic capacitor on its two heads, it creates high impedance at each frequency and range of that frequency. By changing
1. Use condition (21) to calculate FTotal . 2. Use condition (22) to calculate FTotal . 3. Averaging the median of the two conditions to calculate FTotal . According to studies, the second mode is the best way to reduce noise. So FTotal is: 0 1 V 2n;out;M1;2 þ V 2n;out;M3;4 þ V 2n;out;M5;6 þ V 2n;RL A FTotal ¼ 1 þ @ AV 2 4KTRs
(24)
According to mode 2, V 2n;out;M3;4 is deleted. So we have:
Fig. 7. Schematic of real model of bandwidth enhancement technique that is name series inductors. 103
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Fig. 8. The IIP3 cancellation mechanism.
Fig. 9. S21 parameter in 4–11.5 GHz bandwidth in Pre-Layout and Post-Layout modes.
Fig. 10. NF parameter in 4–11.5 GHz bandwidth in Pre-Layout and Post-Layout modes. Also, the input impedance matching parameter (S11) in the whole of the bandwidth is shown in Fig. 11, which is less than 10dB. 104
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Fig. 11. S11 parameter in 4–11.5 GHz bandwidth in Pre-Layout and Post-Layout modes.
Fig. 12. IIP3 parameter at 5 GHz frequency with 10 MHz two tone space in Post-Layout mode.
Fig. 13. IIP3 value at 4–11.5 GHz bandwidth in Post-Layout mode.
the input frequency, the first inductor is removed from the circuit and the next inductor is added to the circuit so that it can maintain the resonance operation and the gain increases. With more inductors, the more resonant frequencies can be obtained, resulting the wider bandwidth. This is the case when the number of inductors does not lead to the noise increasing due to the existence of series resistors in each inductor. Because each time one of the inductors is in resonance mode and generates high impedance, the resistance of the other inductors is insignificant against the high created impedance. This impedance is parallel with the relatively lower impedance of LNA output, and in principle, the output resistance of the LNA has been the main resistance of the circuit
that causes the bandwidth of circuit to remain constant. In the proposed LNA, 6 inductors are used in each output, which is a total of 12 inductors. It is not necessary to run each inductor one after the other and it can be probable the first inductor act as the number one and then it follows with the inductor number three. For this reason, in order to get the best bandwidth, the inductors are tuned during simulation operation and its results are demonstrated in section 5. 5. IIP3 investigation Due to extra transistors (M5 and M6 ) structure, the IIP3 can be
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Fig. 14. Layout of circuit with occupied space of 731 μm 1816 μm.
6. Simulation results
Table 1 Element values and bias circuit voltages. parameter
Value
parameter
Value
M1;2
6μm =0:06μm
L6
M3;4
5μm =0:06μm
LS
M5:6 L1
28μm =0:06μm 6.7 nH @5 GHz (Q ¼ 11.1)
L2
3.37 nH @5 GHz (Q ¼ 14.8) 1.2 nH @5 GHz (Q ¼ 10.4) 1.38 nH @5 GHz (Q ¼ 11.02) 4.43 nH @5 GHz (Q ¼ 12.5)
C1;2 RB (OffChip) VB1
5.8 nH @5 GHz (Q ¼ 11.4) 2.1 nH @5 GHz (Q ¼ 11.6) 2.6 pF 50 kΩ
L3 L4 L5
The presented circuit in Fig. 2 is simulated using a 65 nm TSMC RF CMOS technology by a 1.2v supply voltage with cadence spectre tool. The simulated parameters include the S21, the noise figure (NF), S11, and IIP3 in the bandwidth of 4–11.5 GHz. The simulation results include the pre-layout and post-layout modes. The results of each case are reported in the simulation of these two modes. The S21 parameter is shown in Fig. 9. As shown in Fig. 9, the average gain value is 21.3 1 dB. The gain deviations are shown the switching of the inductors at different frequencies, which is very low deviation so that the gain can be considered as a flat range in the entire operating bandwidth. By assuming γ 1, the noise figure in the calculation is assumed to be less than 3 dB by considering the sub-micron feature of the technology. The NF value for the whole bandwidth is shown in Fig. 10 which indicates NF value is less than 3 dB. Also, the minimum NF is 2.75 dB. The IIP3 value of the circuit at a frequency of 5 GHz, which it is the highest gain, is 6.5 dB m. To simulate, 10 MHz frequency is considered for two tone space. The simulation results of the IIP3 are shown in Fig. 12. Also, in order to evaluate IIP3 in the whole band, the value of this parameter has been swept across the entire band (see Fig. 13), indicating that this parameter is high in the whole band. As shown in Fig. 13, the value of IIP3 at 5 GHz frequency has the minimum value. Fig. 14 is a view of the proposed LNA layout. As previously
300 mV
VB2 VB3
1.2 V 600 mV
Vdd
1.2 V
improved. As shown in Fig. 8, M1 and M2 produce intermodulation signals in the M5 and M6 gates. Gate-source voltages of extra transistors are formed from fundamental signals minus the intermodulation þ fundamental signals which are resulted intermodulation signals in output current of M5 and M6 . This currents are added to the output nodes to cancel the intermodulation signals in the main paths (M13 and M24 ) with opposite phase.
Table 2 A comparison between this work and conventional ones. Ref.
Tech. (μm)
BW (GHz)
S11 (dB)
S21 (dB)
NFmin (dB)
IIP3 (dBm)
Pdiss (mW)
Die size (mm2 )
FOM1 ðGHz =mWÞ
FOM2 ðGHz =mWÞ
AEU-2014 [12] MEJO-2015 [13] MEJO-2018 [14] MEJO-2017 [15] AEU-2015 [16] AEU-2017 [17] AEU-2018 [18] This work
0.13 0.09 0.18 0.18 0.18 0.18 0.18 0.065
2.35–9.37 2.4–10.4 0.6–3.15 2.8–7.5 2.3–4.8 0.8–10.4 0.3–3.5 4–11.5
<-8 <-11 <-13.5 <-8 <-10 <-9 <-10 <-10
10.31 9.2 20.2 13 24 13.7 14.6 21
3.68 3.5 2.8 3.6 2.8 3 2.9 2.75
4 13.1 4.2 10.5 3.2 10.3 1.2 6.5
9.97 14.8 6 3.8 13.1 7.2 14.8 5.15
0.39 0.437 0.026 0.77 0.34 0.19 0.275 1.32
3.15 1.26 4.82 4.32 3.33 6.48 1.21 18.49
1.26 25.72 1.83 0.39 1.59 69.46 1.59 82.65
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mentioned, 12 inductors were used in output to improve bandwidth. One of the advantages of this technique is that by adding more inductors, one can help considerably to increase the bandwidth, while not causing suffer from the increasing of noise figure of the proposed circuit. The only problem of this method is more occupied area which can be greatly reduced by the use of more advanced technologies. The occupied space of the drawn Layout is 731 μm 1816 μm. Table 1 shows the values of the used elements in the circuit, including bias-voltages of circuits that the values are obtained by an optimization. Also in Table 2, a comparison is done between this work and conventional works. It should be noted that the amount of occupied space has not changed significantly in comparison with conventional works. In Table 2, the value of FOM1 [10] and FOM2 [11] are reported by using the following formulas, which have been used in several papers.
GHz S21 BW½GHz ¼ FOM1 mW ðF 1Þ PD ½mW FOM2
GHZ s21 BW½GHZ ІІP3½mW ¼ ðF 1Þ pD ½mW mW
[8]
[9] [10]
[11]
[12]
[13]
[14]
(30) [15]
[16]
(31)
[17]
7. Conclusion [18]
In this paper, a UWB-LNA circuit is designed and simulated in a 65 nm TSMC CMOS RF technology using a 1.2v power supply with a power consumption of 5.15 mW with cadence spectre tool. Noise cancellation and bandwidth enhancements methods are presented in this work. By adding two transistors, in addition the noise of LNA is canceled, the LNA can cancel the noise of excess transistors. Furthermore, using series inductors can flat the bandwidth without any coupling between the inductors and switches to select the specified band. Noise cancellation method has reached the lowest noise figure of 2.75 dB in the differential cascode common gate. While the presented series inductors method offers a bandwidth of 4–11.5 GHz with gain of 21 dB. Another benefit of this technique is that can be used for higher bandwidth by adding more inductors. It should be noted that the minimum amount of IIP3 in the whole of bandwidth is 6.5 dB m. The occupied space is 731 μm 1816 μm and the results are reported in the Pre-Layout and Post-Layout modes.
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Hosein Seyedi was born in a historical city in KermanshahIran, in 1990. He received the B.sc and M.sc degrees in Electrical Engineering in 2012 and 2014 from Kermanshah and Science & Research Branches of Islamic Azad University respectively. He is now working toward Ph.D. thesis in Kermanshah Branch, Islamic Azad University. His fields of interest are CMOS and RFIC design circuits. Also, he has been the manager of a section related to communication devices and BTS mobile antennas during 2016–2018 years.
Ramin Dehdasht-Heydari was born in a beautiful city in Esfahan-Iran, in 1983. He received the Ph.D. degree in Electrical Engineering in 2013 from Science & Research Branch, Islamic Azad University, Tehran-Iran. He worked as a guest researcher at Aalborg University of Denmark during 2012. He currently is an assistant professor at the Telecommunication Group of Kermanshah Branch, Islamic Azad University, Kermanshah-Iran. Dr. Dehdasht-Heydari is the author of 4 books regarding electrical and IT engineering as well as some research papers. Also, he is the reviewer of Applied Computational Electromagnetics Society (ACES) and Transactions of the Institute of Measurement and Control journals. His principal fields of interest in research are UWB antennas, microwave and millimeter wave circuits, wireless, cellular & optical networks, and numerical electromagnetism methods.
Appendix A. Supplementary data Supplementary data to this article can be found online at https://do i.org/10.1016/j.mejo.2019.04.015. References [1] Jin-Fa Chang, Yo-Sheng Lin, A high-performance distributed amplifier using multiple noise suppression techniques, Microw. Wirel. Compon. Lett. IEEE 21 (9) (2011) 495–497. [2] Jin-Fa Chang, Yo-Sheng Lin, A DC-10.5-GHz CMOS distributed amplifier with 3.20.3 dB NF 10.51.4 dB gain and 13.8 ps Group delay variation, in: Radio and Wireless Symposium (RWS) 2011 IEEE, 2011, pp. 307–310. [3] T.Y. Chang, et al., A packaged and ESD protected inductorless 0.1 to 8 GHz wideband CMOS LNA, IEEE Microw. Wirel. Compon. Lett. 18 (No. 6) (2008) 416–418. [4] C.-F. Liao, S.-I. Liu, A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver, in: Proc. IEEE 2005 Custom Integrated Circuits Conf. (CICC), Sept. 18-21, 2005, pp. 160–163. [5] Yiming Yu, Kai Kang, Yiming Fan, Chenxi Zhao, Huihua Liu, Yunqiu Wu, YongLing Ban, Wen-Yan Yin, Analysis and design of inductorless wideband low-noise amplifier with noise cancellation technique, Access IEEE 5 (2017) 9389–9397. [6] Lanqi Liu, Zhaojing Lu, Kefeng Zhang, Zhixiong Ren, Ang Hu, Xuecheng Zou, Wideband balun-LNA exploiting noise cancellation and gm compensation technique, Electron. Lett. 52 (8) (2016) 673–674. [7] Kefeng Han, Liang Zou, Youchun Liao, Hao Mi, Zhangwen Tang, A wideband CMOS variable gain low noise amplifier based on single-to-differential stage for TV tuner
Saeed Roshani received the B.Sc. degree in Electrical Engineering from Razi University, Kermanshah, Iran in 2008, M.Sc. degree in Electrical Engineering from Shahed University, Tehran, Iran in 2011 and Ph.D. in Electrical Engineering from Razi University in 2015. His research interest includes the microwave and millimeter wave devices and circuits.
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