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A pipelined microprocessor for logic programming languages
Literature survey resulting difficult problem is further explored. The paper addresses a multiple objective optimization model to determine the file allocation and query routing assignment in a distributed information system. The problem is formulated as a zero-one integer nonlinear programming problem with multiple objectives. The optimization problem under consideration is shown to be NP-hard. The authors adopt an iterative improvement procedure, which gives the Pareto optimal solution. They further illustrate their methodology with a small sample system.
Lerch, R G, Lamkemeyer, M H, Fielder, H L, Bradinal, W and Becker, P. 'A monolithic EA A/D and D/A converter with filter for broad-band speech coding' IEEE 1. Solid-State Circuits Vol 26 No 12 (December 1991) pp 1920-1927 The authors present a 5-V-only 14-b, 16 ksamples/s linear codec suitable as the audio part of a CCITT G722 codec. The device uses second-order sigma-delta modulation for both analogue/digital (A/D) and digital/ analogue (D/A) conversion at 2.048 Msamples/s. A time-continuous modulator with integrated antialias filtering is used at the A/D side, obviating the need for an external antialiasing filter. The digital filter for decimation and interpolation are implemented with both a custom digital signal processor (DSP) and specialized hardware. The device was realized with 74000 transistors on a 31-mm 2 die in a 3-/~m SACMOS technology. A dynamic range of more than 80 dB and a passband ripple of 0.3 dB were attained with A/D and D/A paths in cascade.
Lombardi, Muzio, I
F,
Shen,
Y-N
and
'FFT architecture for WSI and concurrent error detection and fault location' lEE Proc. E. Comput~ Digit. Tech. Vo1139 No I (January 1992) pp 13-20 The paper presents a new approach for concurrent error detection in
166
homogeneous VLSI/WSI architectures for the computation of the complex N-point fast Fourier transform (FFT). The proposed approach is based on the relationship between the computations of cells at a given point distance. This relationship is analysed with respect to functional and physical faults. It is proved that a 100% probability of detection is possible. Overhead issues for hardware and timing are addressed. It is proved that hardware overhead is 50% compared to a fault intolerant complex 2-point implementation. Fault detection can be accommodated online and on a component basis (multiplier or adder/subtractor); full fault location is accomplished by a roving technique, which utilizes a reconfiguration approach at no significant time overhead. The proposed technique can be accommodated efficiently in a homogeneous layout for WSI implementation. A two-phase reconfiguration policy for the proposed architecture is presented. It is proved that switching and routing overheads are modest, while achieving a significant reliability improvement over previous approaches.
Milutinovic, V M, Fura, D A and Helbig, W A 'Pipeline design tradeoffs in a 32-bit gallium arsenide microprocessor' IEEE Trans. Comput. Vol 40 No 11 (November 1991) pp 1214-1224 The results of a study of the instruction pipeline design for a 32bit single-chip GaAs microprocessor are presented. The authors introduce nine candidate solutions for the instruction pipeline, define a set of technology-dependent and application-related parameters, and present the results of the comparative performance evaluation. Important differences between GaAs and silicon, which are relevant for the design of an instruction pipeline, are described. The authors determine the quantitative differences between various candidate solutions. The superb performance of the pipelined
memory pipeline in all environments is demonstrated.
Miyanaga, H and Yamauchi, H 'A 400 MFLOPS FFT processor VLSI architecture' IEICE Trans. Vol E74 No 11 (November 1991) pp 3845-3851 Proposes a single-chip 400 MFLOPS 2-D FFT processor VLSI architecture. This processor integrates 380000 transistors in an area of 11.58 X 11.58 mm 2 using 0.8/~m CMOS technology with a typical machine cycle time of 25 ns, and executes 2 n X 2 n point 2-D FFT in real time, e.g. 256 x 256 point FFT is executed in 14 ms. This excellent performance in terms of both speed and dynamic range makes real-time processing practical for video as well as speech processing.
Nakashima, H, Takeda, Y, Nakajima, K, Andou, H and Furutani, K 'A pipelined microprocessor for logic programming languages' Proc. 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA, 17-19 September 1990 (Los Alamitos, CA, USA: IEEEComput. Soc. Press 1990) pp 355-359 The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages. KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.
Microprocessors and Microsystems
Lerch, R G, Lamkemeyer, M H, Fielder, H L, Bradinal, W and Becker, P. 'A monolithic EA A/D and D/A converter with filter for broad-band speech coding' IEEE 1. Solid-State Circuits Vol 26 No 12 (December 1991) pp 1920-1927 The authors present a 5-V-only 14-b, 16 ksamples/s linear codec suitable as the audio part of a CCITT G722 codec. The device uses second-order sigma-delta modulation for both analogue/digital (A/D) and digital/ analogue (D/A) conversion at 2.048 Msamples/s. A time-continuous modulator with integrated antialias filtering is used at the A/D side, obviating the need for an external antialiasing filter. The digital filter for decimation and interpolation are implemented with both a custom digital signal processor (DSP) and specialized hardware. The device was realized with 74000 transistors on a 31-mm 2 die in a 3-/~m SACMOS technology. A dynamic range of more than 80 dB and a passband ripple of 0.3 dB were attained with A/D and D/A paths in cascade.
Lombardi, Muzio, I
F,
Shen,
Y-N
and
'FFT architecture for WSI and concurrent error detection and fault location' lEE Proc. E. Comput~ Digit. Tech. Vo1139 No I (January 1992) pp 13-20 The paper presents a new approach for concurrent error detection in
166
homogeneous VLSI/WSI architectures for the computation of the complex N-point fast Fourier transform (FFT). The proposed approach is based on the relationship between the computations of cells at a given point distance. This relationship is analysed with respect to functional and physical faults. It is proved that a 100% probability of detection is possible. Overhead issues for hardware and timing are addressed. It is proved that hardware overhead is 50% compared to a fault intolerant complex 2-point implementation. Fault detection can be accommodated online and on a component basis (multiplier or adder/subtractor); full fault location is accomplished by a roving technique, which utilizes a reconfiguration approach at no significant time overhead. The proposed technique can be accommodated efficiently in a homogeneous layout for WSI implementation. A two-phase reconfiguration policy for the proposed architecture is presented. It is proved that switching and routing overheads are modest, while achieving a significant reliability improvement over previous approaches.
Milutinovic, V M, Fura, D A and Helbig, W A 'Pipeline design tradeoffs in a 32-bit gallium arsenide microprocessor' IEEE Trans. Comput. Vol 40 No 11 (November 1991) pp 1214-1224 The results of a study of the instruction pipeline design for a 32bit single-chip GaAs microprocessor are presented. The authors introduce nine candidate solutions for the instruction pipeline, define a set of technology-dependent and application-related parameters, and present the results of the comparative performance evaluation. Important differences between GaAs and silicon, which are relevant for the design of an instruction pipeline, are described. The authors determine the quantitative differences between various candidate solutions. The superb performance of the pipelined
memory pipeline in all environments is demonstrated.
Miyanaga, H and Yamauchi, H 'A 400 MFLOPS FFT processor VLSI architecture' IEICE Trans. Vol E74 No 11 (November 1991) pp 3845-3851 Proposes a single-chip 400 MFLOPS 2-D FFT processor VLSI architecture. This processor integrates 380000 transistors in an area of 11.58 X 11.58 mm 2 using 0.8/~m CMOS technology with a typical machine cycle time of 25 ns, and executes 2 n X 2 n point 2-D FFT in real time, e.g. 256 x 256 point FFT is executed in 14 ms. This excellent performance in terms of both speed and dynamic range makes real-time processing practical for video as well as speech processing.
Nakashima, H, Takeda, Y, Nakajima, K, Andou, H and Furutani, K 'A pipelined microprocessor for logic programming languages' Proc. 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA, 17-19 September 1990 (Los Alamitos, CA, USA: IEEEComput. Soc. Press 1990) pp 355-359 The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages. KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.
Microprocessors and Microsystems