A review of hot-carrier degradation mechanisms in MOSFETs

~

Microelectron. Reliab., Vol. 36, No. 7/8, pp. 845-869, 1996 Copyright © 1996 Elsevier Science Ltd Printed in Great Britain. All rights reserved 0026-2714/96 $15.00+.00 PIhS0026-2714(96) 00022-4

lPe~amon

REVIEW PAPER A REVIEW OF H O T - C A R R I E R D E G R A D A T I O N M E C H A N I S M S I N M O S F E T s A L E X A N D R E A C O V I C , G I U S E P P E L A R O S A and Y U A N - C H E N S U N SRDC, I B M Microelectronics, Hopewell Junction, N Y 12533, U S A

[ABSTRACT] We review the hot-carrier effects and reliability problem in MOSFET. The mechanisms that produce the substrate and gate current are discussed, and the various mechanisms for hot-carrier degradation are presented. DC and AC lifetime models are summarized, and the effects on a CMOS circuit explained. The effects of scaling on the hot-carrier induced degradation are presented and the influence of processing steps and stress temperature discussed. Ways to improve the reliability of MOSIPETs are then presented. Finally the reliability of SOI MOSFETs is compared to that of bulk MOSFETs. Copyright © 1996 Elsevier Science Ltd I1) INTRODUCTION I Complementary Metal-oxide-Semiconductor (CMOS) has emerged as the dominant integrated circuit technology, due to it's high density, speed and low power. The basic building block of this technology

is

the

Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET).

Since

it's

introduction in the mid 1960s, thanks to tremendous progress in lithography technologies, the channel length of MOSFET's used in the state of the art CMOS IC technology has been reduced by a factor 0.7 every 3 years, allowing more and more complex functions on the chip. Today, in state of the art CMOS, MOSFET's with a LEFF---0.25pm are used [1]. This channel length reduction of the MOSFET has led to an increase 9f the switchable current (essentially inversely proportional to the channel length) available to discharge parasitic capacitances, and thus to an increase in the circuit speed [2]. At the same time, since the power supply voltage has remained constant at 5V and has only recently started to be lowered to 3.3V [3], this channel reduction has resulted in very high fields in the drain region of the MOSFET, giving rise to tht. so called hot-carrier induced reliability problem. As a result of this reliability concern, but also to reduce the power dissipation, some advanced CMOS technologies use 3.3V [3], 2.5V [1] or even 1.8V [4] power supplies. This paper is an attempt to summarize the status of the hot-carrier reliability in MOSFETs. Due to the extensive work done on the subject in the last 25 years, it is impossible to cover it exhaustively in one paper, and for details the reader is referred to the references [1-149]. I2) HOT CARRIERS IN THE MOSFET I The MOSFET is essentially a voltage controlled resistor, made by the inversion layer induced by the gate voltage. When the gate to substrate voltage (VG) is relatively high compared to the source 845

846

A. Acovic et al.

to drain voltage (VDs), the resistivity along the inverted channel is constant and the voltage varies linearly between the source and the drain. If however, the gate voltage is comparable to or lower than VDS, the inversion layer is much stronger on the source side than on the drain side (if VD>Vs) , and the voltage drop due to the channel current is concentrated on the drain side (Fig. 1). Carriers traveling from the source to the drain can gain a considerable amount of energy in this high field region. Indeed, the field can be so high (>104 V/cm) that carriers gain a significant amount of energy between two scattering events, They are called "hot" because if their kinetic energy is written as k. Te, T e may be as high as I'D00 to 10'000K, much higher than the lattice temperature T [5]. The majority of the hot-carriers simply continues toward the drain, but a small number of them gain enough energy (about 1,5. EGAP) to generate electrons and holes by impact ionization. In the case of the NMOSFET, the vast majority of the generated holes are collected by the substrate and give rise to the substrate current (Isus) , while the generated electrons enhance the drain current (I D ~ I S + I s o s , where I S is the source current, see Fig. 1). The substrate current is an indirect measurement of the drain electric field in a MOSFET and hence of the susceptibility of a MOSFET to hot-carriers. Photon emission that takes place during hot-carrier generation in the drain is also an indication of the intensity of hot-carrier generation [6-7]. At high VDS, the voltage drop on the substrate resistance due to the substrate current can become so important that it forward biases the source/substrate junction, turning on the parasitic bipolar device in parallel to the MOSFET. The resulting increased injection of carriers in the channel furnishes more candidates for impact ionization in the drain, and hence produces even more substrate current. Above a certain VDS, a self-sustaining mechanism exists, which results in the so called MOSFET's snapback breakdown. Hence, the substrate current plays an important role in the drain diode avalanche breakdown [8-10], and can also induce latch-up.

Generated defects: Interface states &

V~~2V Trapped charges

~G,~ / ]

High VDrain & small LEFF

High Drain Electric field

/

Hot-carriers Impa.ct ionization

]S~strate~

>

Snapback Breakdown

" k~) drain ~..," " ~ High+field

~

p\n

ISubstrale

Hot-carrier injection into oxide

}Gate Light

source~;~ n* / I

rapped Interface Oxide traps electrons, holes states

AIDrain, AVT, AGIDL, Alsua, ADIBL, hSS, AgDS, etc...

Figure h" Summary of the hot-carrier generation and degradation in MOSFETs. The inset shows a NMOSFET under the typical hot-carrier stress conditions and the resulting high-field region of the drain.

Hot-carrier degradation m e c h a n i s m s in M O S F E T s

847

Some of the hot-carriers gain so much energy (about 3.2eV for electrons and 4.7eV for holes) that they can surmount the energy barrier at the Si/SiO 2 interface and be injected into the oxide, producing a small gate currenl (IG). A small fraction of the injected carriers may remain trapped in the oxide or - if they are energetic enough- break some Si-H or similar weak bonds in the oxide or at the SiO 2 interface. If the hot-carrier injection lasts enough, the trapped charges or generated defects will permanently

modify

the electric field at the Si-SiO 2 interface and

characteristics of the M O S F E T

hence the electrical

(threshold voltage VT, subthreshold slope, etc...). These modifications

may ultimately affect the proper functioning of the integrated circuit itself(Fig. I).

[3) S U B S T R A T E

HOT-CARRIER

CURRENT

1

The substratc current is the easiest to measure and to model hot-carrier current in a M O S F E T . It can be written as the product of the source current IS (the source of carriers) arid of the probability of impact ionization [11], which depends on the lateral electric field in the drain

{gLAT'integrated over

the channel length L: L

ISUB=Is-/AIo N.exp{-~} 0

dx

(1)

where AIO N and Bio N are fitting parameters. BION can be interpreted in the lucky electron model as ¢I/(q" A), where ¢i is tbe minimum energy for impact ionization and A is the carrier mean free path [7]. The exponential term in (I) is the probability for a "lucky" electron to travel the distance necessary to gain the energy ¢I without suffering any scattering. The source current I s increases exponentially until VG reaches the threshold voltage VT, then it increases linearly. On the other hand, gLAT is maximum for low VG'S (MOSFET in saturation), and decreases at high VG'S (the MOSFET is in the linear regime) [11]. Consequently, at a given VDS and when V G increases, the suhstrate current Isu 8 first increases with I s until VG is between VD/3 and VD/2 and then it decreases due to the lower ffaLAT (Fig. 2a from I12]). The ratio I s u 8 / l s -which essentially measures the ionization probability and thus gLAT- is not very much channel length dependent at low VG'S, but it's decrease at higher VG'S is strongly reduced in short MOSFETs, because at high VG'S the MOSFET is closer to a uniform resistor case, in which gLAT ~ VD/L" For the same reason, the decrease of Isu B at high VG'S from its peak value is smaller in short MOSFET's. Due to the exponential, tile integral (1) is strongly dominated by the maximum of ~LAT (gMAX) so that the substrate current can be approximated by [13]: g2MAx • IS • exp{ - BISON ~ } d~LAT ~MAX ION'~ (X=L) Aio n '

ISUB----B

(2)

dgLAT For a MOSFET in saturation, 8MAx ~ A. (VD-VDsAT), ~ ~-, A 2. (VD-VDSAT), and A is given by:

A~ f

~o~

(3)

848

A. Acovic

Figure 2: a) Typical substrate of VG, for a constant change

after

various V,,

where T,, increases

(g,)

st:ess of the charge

for 60min. Reproduced

with a floating gate technique)

W=20nm, pumping

versus the gate bias applied

is the oxide thickness

LgpF=l.5jrm

NMOSFET.

(ICp), the threshold

voltage

as a function b) Normalized (V,)

and the

under stress. The stress was at V~~=6.5v

and

from [12] (0 IEEE 1986).

and Xj is the junction

when the oxide thickness

simplified

(measured

VDS=6.5V in a Tox=24nm,

a hot-carrier

transconductance

and gate current

et al.

or the junction

depth.

This simple model shows that

depth are reduced. These equations

ISUB

can be further

[14]:

‘(VD-V~~AT). I,. exp{

I sus=AION

_

*ION

BION A.

(4)

(VD-VDSAT)’

When the log of(I~~~/[Is.(VD-VDSAT)I)is plotted as a function of ~/(VD-VD~AT), A, AroN and BloN can be extracted or channel

for a given technology,

length [14], provided

so that IgUB can be calculated

VDSAT is known. The reference [14] also provides a graphical

to find VDSAT. Due to the lower impact

ionization

drain

is orders

junctions,

NMOSFETs

of the two-dimensional

only numerical

doping.

of magnitude

nature

current

step, then self-consistently

calculation,

- an impact

on

the

The current local

approximation)

electric

ionization

and

[lo]. At high drain

region is so rapid, with the crystal

in these simplified simulators field

compared

lattice.

on

the

voltages

with the carrier

Thus, the carrier

field and current

compared

term dependent

added

channel

to

is represented the

carrier

however,

the variation

concentration

continuity

of term dependent (drift-diffusion

of the electric field in the drain

mean free path that the carriers cannot

and drain

on the local electric field

as a combination

of

in the

- first as a post-

solution of the Poisson and current

gradient

transport

distribution

the effects of varying

early device simulators

(an the one used in eq. 1) to the usual two dimensional equations.

deeper and more graded

lower in PMOSFETs,

of the electric

models are precise enough to evaluate

To allow for substrate

processing

current

rate for holes and (usually)

method

[15].

Because dram,

the substrate

for any biasing condition

be described

are not in equilibrium

in terms of local parameters

Hot-carrier degradation m e c h a n i s m s in M O S F E T s

like the electric field and the carrier concentration gradient. For such cases, a solution of the Boltzmann transport equation is required. In the hydrodynamic approximation, the Boltzmann equation is solved by the moment method [16], so that in addition to the conservation of the current (continuity equation), equations for the conservation of the electron momentum and electron energy have to be solved [17-19]. To treat adequately impact ionization in regions with rapidly varying electric field, a non-local model for impact ionization is necessary [17, 20]. Although the hydrodynamic approximation requires some fitting parameters (the energy and momentum relaxation times) and it does not take into account the full band structure of silicon, it is relatively computationaly efficient, so that it is a good engineering compromise used in many device simulators (MINIMOS-3 [19], HFIELDS [21], IBM's FIELDAY, TMA's MEDICI, etc...). On the other hand, the Monte-Carlo method of solving the Boltzmann transport equation, which essentially follows each carrier as it moves in the electric field and is subject to scattering events is the most physically accurate, but it is also the most computationaly intensive, [21-26] and it is thus not (yet) practical for device design. All these simulation tools require a very careful calibration of their adjustable coefficients with hardware similar to the devices under simulation, so that the quantitative a ptlori predictive power of these models and simulators is still limited. Independently of the adequacy of the physical model, modeling the substrate current is made difficult by its sensitivity to the exact doping profile close to the drain, and the difficulty of measuring or predicting reliably the doping in 2 or 3 dimensions.

[4) G A T E

HOT-CARRIER

CURRENT

I

The gate current is essential from the device degradation point of view, because carriers which get into the oxide degrade the M O S F E T .

Notice that some carriersthat are injected into the oxide may

not have enough energy to complete their journey and thus may not be measured as the gate current, but may stillgenerate defects in the oxide or at the Si-SiO2 interface [27]). Because the gate current depends on the oxide electric field at the injection point and the potential barrier at the Si-SiO 2 interface,in addition to the carrierenergy and momentum, modeling of the gate current is much more complicated even than that of the substrate current. However, some intuitive insight is easy to gain. In the N M O S F E T ,

the oxide electric field is favorable to hole injection when V G < < V D ,

because the gate is at a more negative potential than the drain close to which the holes are generated [28]. However, because of the high potential barrier for holes (about 4.8 eV), the hole gate current usually cannot be measured directly, but only using special floating gate techniques [28-30]. For V G close to or gre~ter than VD, the oxide field becomes favorable to electron injection, and because of the lower potential barrier for electrons (about 3.2 eV), the electron gate current can easily be measured [31]. Fig. 2a shows a typical gate current in the NMOSFET [12]. In the PMOSFET, the situation is essentially symmetrical, with electron injection occurring at

849

850

A. Acovic et al.

low IVG[, and hole injection at V G close to V D. The electron gate current in the PMOSFET can be quite strong, because it occurs at the time where the lateral field is very strong (low VG, device in saturation), the oxide field very favorable to electron injection (the gate is much less negative that the drain), and the potential barrier for electrons is relatively low. On the other hand, the hole gate current is hardly measurable, even with a sensitive floating gate technique, for the lateral field is low [since V G ~ V D the MOSFET is close to the linear regime), the oxide field is not very favorable to hole injection (V G ~ VD) and the barrier height is high for holes. Using the phenomenological lucky electron model [32], the electron gate current for VG>V D can be written as

IG ~, P(Eox ) .I D • exp{

q ' A .~AX }

(5)

where P(Eox ) is the probability for an electron to arrive at the gate once injected into the oxide, eb is the effective potential barrier at the Si-SiO 2 interface, A the mean free path in silicon and gMAX the maximum

drain electric field [7]. If the substrate current is also written using the lucky electron model

(Isu B ~ C. I s • exp[ - ¢i/(q' A. ~aMAX)], where ¢i is the impact ionization threshold) [7], and the ratio of the gate to substrate current taken (assuming I s ~ ID), one obtains a convenient way to estimate the ratio of the oxide barrier to the ionization threshold, if plotted at a constant VGD (and EOX ) [7, 33]:

CB I~=C.~SUBI~iID j

(6)

where C mainly depends (weakly) on the oxide electric field. Although more precise than (6), even more complex 2-D numerical solutions of the Boltzmann transport equation in silicon and oxide [34-35], or the complex Monte-Carlo simulations [23] are difficult to match precisely to the hardware, due to the complex physics involved and the uncertainties in the 2-D doping profile. In particular, the carriers injected into the oxide are much more energetic than the one involved in the substrate current, and injection into the oxide and transport in the oxide are difficult to model [35-36]. In addition to the hot-carrier reliability problem, recent work on gate current modeling has been motivated by the application of hot-electron injection to the programming of EEPROM's.

15) MOSFET's DEGRADATION Since the maximum

electric field in a MOSFET

I

is localized close to the drain, the hot-carrier

degradation of the gate oxide is limited to the ~, 0.1/ira region around the drain junction. This localization of the degradation close to the drain makes the device parameters of stressed MOSFETs highly asymmetric when measured at high VD, with the highest degradation of their characteristics appearing usually when configuration [37].

measured swapping the source/drain biases with respect to the stress

Hot-carrier degradation m e c h a n i s m s in M O S F E T s The holes or electrons injected into the oxide can remain trapped or generate neutral traps in the oxide bulk or produce interface states. Holes are 3-4 orders of magnitude more effective at producing interface states than electrons (electron efficiency is about 5. life), and their trapping rate is very high (on the order of 10%), about 5 orders of magnitude higher than those of electrons [38-39]. Experiments using a nonavalanche injection technique allow to uniformly inject either electrons [40] or holes [39] and are easier to interpret that the localized degradation due to hot-carriers in a MOSFET, so that they are invaluable in understanding the effects of hot-carrier injection on oxide. It is beyond the scope of this paper to discuss the microscopic nature of the oxide degradation due to hot-carriers, and the reader is referred to existing excellent reviews on the subject [41]. It is sufficient to say that the interface states are probably produced when a Si-H bond is broken at the interface, and electrons or hole traps are, among others, due to dangling bonds in the bulk of the oxide [41]. There is a strong dependence of these bulk and interracial traps on the gate oxidation and subsequent process conditions, such as moisture, H contents of passivation layers and plasma induced damage. Both the nature of the oxide defects and their lateral position determine their effect of the IV characteristics of the MOSFET. From uniform injection experiments we know that interface states produce a change in the sub-threshold slope, while fixed charges uniformly shift the ID(VG) curve. However, simulations have shown that localized electron traps close to the drain can also produce a sub-threshold slope change [42, 43]. Both interface states and oxide traps can degrade the carrier mobility, and thus the linear ID(VG) slope and transconductance gin" Only an independent measurement of the interface state density, as provided by charge pumping, can help decide between oxide and interface traps. Charge pumping is a powerful -yet easy to implement- technique that Mlows to directly measure the interface states, and also, albeit less directly, trapped charges in a MOSFET, instead of their indirect consequences on the drain current [44]. It consists of applying voltage pulses on the gate to bring the MOSFET quickly alternatively in inversion and accumulation, and measure the current due to the recombination of electrons that filled the interface states during inversion with the holes brought to the surface in accumulation. Due to the non-uniformities of the VT and VFB close to the drain, caution must be exercised when interpreting charge pumping data from stressed MOSFETs [44]. Based on charge pumping measurements, the following model due to Heremans et al. emerges for the NMOSFET degradation [38]. In the NMOSFET, at low V G (close to VT) , only hole injection takes place producing interface states and trapped holes. In NMOSFETs, interface states are negatively charged during the measurement in strong inversion, so that their effect is partially masked by the (positively charged) trapped holes. However, the full effect of the interface states can be revealed by a subsequent electron injection. Depending on the relative importance of hole trapping and interface state generation, the NMOSFET is either shortened, due to the positive charge of the trapped holes, which results in a drain

851

852

A. Acovic et al.

current increase, or the drain current decreases due to the negatively charged interface states. Neutral electron traps may also play a role in stresses at low V G [45]. At higher VG'S , between VD/3 and VD/2 , the substrate current is close to its peak, and electron and probably some hole injection produce interface states. It is difficult to estimate the relative share of hole and electron injection on oxide degradation, since holes are very efficient at generating defects, but their number is much lower that those of electrons, which on the other hand are less efficient at generating defects [26, 38]. Due to the simultaneous injection of electrons, most of the the trapped holes are neutralized by the injected electrons. Some of the trapped holes are converted to interface states if they capture an electron [46], although the subject is still controversial. It was initially thought that the electron-hole recombination step is the main mechanism for interface state production [27, 46], but more recent experiments seem to indicate a rather small increase of interface states after electron injection on trapped holes, at least under the hot-carrier injection conditions in

a

MOSFET [38]. However, since the holes have a very high trapping rate, even if a smnll amount (5%) of them is converted to interface states by electron/hole recombination, that amount can still be comparable to the amount of interface states directly generated by hole or electron injection (separately) [391. The problem is complicated by the fact that in the NMOSFET hole and electron injection occur simultaneously most of the time. Independently of the details of the interface states creation, they are usually negatively charged when the NMOSFET is in inversion and the channel current is decreased after stress. During the measurement of the effects of the stress, if the drain voltage is high, so that the degraded zone is included in the drain depletion zone, the current decrease is reduced, compared to the low V o case or if the source and drain are swapped (Vs=high , VD=0 ). Finally, at high gate voltage, only electron injection takes place, producing negative trapped charge and some interface states [47]. The degradation of the current after a stress at V G ~ V D is usually much lower than under peak substrate current, unless the oxide has a lot of electron traps [48]. Fig. 2b summarizes the degradation of a typical NMOSFET versus the gate voltage [12]. In the PMOSFET, the situation is simpler than in the NMOSFET, because most of the degradation is due to electrons. The highest degradation occurs for low VG'S, where the electron gate is at its peak, and is mainly due to electron trapping, although interface states are also created. The localized electron trapping results in channel shortening [49], and hence an increase of the drain current [50] and indirectly a decrease of IVTI. Because of the channel shortening, the most direct way of measuring the PMOSFET degradation is by monitoring the change of the channel length [50]~ instead of the VT, which is an indirect measurement through the VT=f(L ) dependence. The Drain Induced Barrier Lowering (DIBL), which is a short-channel effect in weak inversion that can he measured by the change of V G necessary to keep a constant I D when V D varies, increases in a stressed PMOSFET especially when the source and drain are swapped after the stress, because then the effect of the degraded zone (which is now on the source side) is not reduced by the drain depletion zone. The increase of DIBL leads to an increase of the off-current in stressed PMOSFETs.

Hot-carrier degradation m e c h a n i s m s in M O S F E T s

Recent work showed that detrapping of electrons [51] a n d the addition of Coulomb repulsion between the already trapped electrons and the injected ones [52] may play an important role in modeling PMOSFET degradation. In PMOSFETs with thin gate oxide (<10am), electron trapping is reduced (because trapped electrons can tunnel easier out of the thin oxide), so that interface state creation becomes relatively more important. Indeed, under the stress conditions V G ~ VD/2 (peak well current), a decrease of the drain current was observed, similarly to the ce.se of the NMOSFET [53]. Early PMOSFETs were build using n + gates and were buried channel devices, contrary to modern PMOSFETs, which have a p+ gate and are surface channel devices. Surface channel MOSFETs are preferred, because they have a better short-channel behavior than buried devices. The gate current in buried and surface channel device seems to be comparable, while the substrate current is lower in the buried device [54]. The buried device is expected to have a worse short-channel effect (the channel is farther from the gate), so it is expected to have a higher change in VT and DIBL as a result of the channel shortening after a hot-carrier stress. The net result is that the reliability of the buried devices is comparable [54] or worse than that of the surface PMOSFET [55]. Modeling of the degradation of the IV characteristics of the MOSFET is relatively easy, if a given oxide degradation is assumed [37, 43], but is extremely difficult if the oxide degradation has to be calculated [34-35]. To all the difficulties in calculating the substrate and gate current are added the uncertainties in the physical models involved in the interface state generation and trap generation by hot-carriers and trapping of carriers in the oxide.

I6) OTHER EFFECTS OF THE HOT-CARPdER INJECTION l The drain current is not the only current affected by the hot-carrier injection into the oxide. The substrate and gate currents are also affected because the lateral electric field is altered. For instance, after a VC, ~ V D stress in a NMOSFET (e-injection), the sub6trate current slightly increases, because the channel has become less conductive close to the drain due to the electron trapping [56]. The substrate current slightly decreases after a VG ~ VT stress in a NMOSFET or a PMOSFET, because the hole or electron trapping, respectively, contribute to increase the channel conductance close to the drain, decreasing 8LAT. In a NMOSFET with a high VD and VG---0 or negative, the channel is not inverted or it is

A

accumulated with holes, and a high field region' exists in the drain, close to the Si-SiO 2 interface. Since the E G in silicon is l.leV only, this field may be sufficient for a either a band-to-hand or trap s/misted tunnel current between the highly doped drain region and the substrate close to the Si-SiO 2 interface [57-58, 1501. This so called "Gate Induced Diode Leakage~ (GIDL), is very sensitive to the field in the gate to drain overlap region. After a VG ~ Vv stress in a NMOSFET, the current is increased, because of the local increase of the electric field due to electron trapping [57-59]. Electron trapping reduces the GIDL current after a VG ~ VT stress in a PMOSFET [57, 59]. The GIDL is also influenced by an

853

A. Acovic etal.

854

increase in interface states generated during a hot-carrier stress, through an increase in interface state assisted tunneling, both in reverse [60] and forward diode bias [58]. In the NMOSFET, at high drain bias, holes that are left behind the electron tunneling from the valence band in the p doped region (or accumulation layer, for VG<0 ) to the conduction band in the drain are accelerated in the high field drain region (where tunneling occurs) and can be injected quite efficiently into the gate oxide, and thus modify the drain and GIDL current [61-62]. In the symmetric situation in the PMOSFET, electrons are injected into the oxide. Since the hot-carrier injection occurs in a rather localized region of the MOSFET, the current densities can be very high during a hot-carrier stress, so that the breakdown characteristics of the oxide is affected. Several studies have shown that the QBD of the oxide is reduced mainly after stresses where appreciable hole injection takes place [63-64], in accordance with oxide breakdown models involving holes [65]. Catastrophic gate-oxide breakdown can also occur as a result of a severe hot-carrier stress alone [66]. Finally, let us mention that the noise of a MOSFET is increased by a hot-carrier stress, which may be important for analog applications [67] and that the terminal capacitances of the MOSFET are also slightly modified by the hot-carrier stress [68].

17) DC DEGRADATION MODELS AND LIFETIME PREDICTION I In the NMOSFETs, a simple selni-empirical models links the lifetime r and the substrate Isu B and drain current I D [7]: 7". I D / W = C . [IsuB/ID] "m

(7)

although the simplified equations r = C . (IsuB/ID) "m or even v=C.I~r~B are often used. r can be defined at a given degradation of the drain current [7] or the threshold voltage or, for better results, at a given increase of the interface state density (measured by charge pumping, for instance) [38]. The "m" in (7) can be interpreted as the ratio of the threshold energies for interface state generation and impact ionization ~I [7]. The degradation of the drain current and the increase of interface states proceeds with t n, with n usually around 0.5 [7, 69]. These models generally work well for the worse stress conditions of V G ~ VD/3...VD/2 , but a different set of C and m may have to be chosen for the V G ~ V T stress conditions, and they are not well adapted for the V G ~ V D stress conditions, since under that stress condition electron trapping is the dominant degradation mechanism instead of

interface state creation. An improvement of the model (7) has been proposed in [70]. At higher degradation levels, the degradation saturates, instead of following the t n power law [71]~ because of the repelling effect of the already injected carriers, and probably because of the very concentrated degradation limited to the drain region. A number of models exist for PMOSFETs, but since the degradation of PMOSFETs is usually much smaller than the degradation of the NMOSFET, PMOSFETs are seldom the limiting factor in

855

Hot-carrier degradation mechanisms in M O S F E T s

the reliability of a CMOS technology [51, 53], unless the off-current increase becomes a major issue [72]. In the PMOSFET, the gate current, or the total injected charge is the determining parameter used in modeling, i'nstead of the substrate current [53, 73]. To estimate the DC worse case lifetime of a NMOSFET, the device has to be stressed at a number of different drain voltages higher than the nominal VD and VG ~ VD/3...VD/2 (or at peak ISUB), and r . 1D should be plotted versus IsuB/I D in a log-log plot. The ISUB/I D for a required lifetime r can be found by extrapolation. From the ISUB/I D curve versus VD for the nominal channel length device, the maximum drain voltage allowed for a given lifetime can be found. Sometimes, instead of ISUB/ID, ISUB is used also (Fig. 3). Note that if the drain current degradation is used to measure the lifetime % the stresses should be followed by a short electron injection at VG ~ VD, to make sure that all trapped holes are neutralized and thus obtain the worst drain current degradation [38].

18) CIRCUIT EFFECTS OF HOT-CARRIER DEGRADATION I Up to now, we have only considered the degradation of a single MOSFET under a DC bias. In a circuit, the MOSFET is subjected to a whole range of rapidly varying gate and drain biases. Some early work reported a substantial increase of the degradation under pulse stress conditions [74], however later it was shown that the degradation is actually very similar between AC and DC stress conditions,

10-5

1°' L :: : _ ' :::"_:' 10 years lOSfx\ \ o~ ,v [

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, ,,"~,

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Effective channel length [~m]

b)

Figure 3: a) Lifetime (at 20% degradation of drain current, with swapped S&D) versus substrate current in a 0.15pro CMOS technology, with Tox=5nm. The degradation at two drain voltages is shown, and for various effective channel length, b) Substrate current in a 0.15#m CMOS technology at VD=I.SV [4] compared to a 0.25pm technology at VD=2.SV [1]. Notice that at a channel length of 0.1pm (worst case of a 0.15pro nominal device), the substrate current is about 0.1pA/pm in the 0.15pin CMOS technology at VD=I.8V, which according to fig. 3a gives a 10 years DC lifetime. AC lifetime is even higher.

A. Acovic et al.

g56

and that there is no transient AC effect, provided proper grounding and clean AC pulses are used [?576]. Therefore, at moderate frequencies, the degradation of a MOSFET under AC stress conditions can be simulated quite well with an alternating hole (V G ~ VT) and electron injection (Vt~ ~ VD) DC stress in a NMOSFET (quasi-static approximation) [76]. Under such conditions a smaller decrease of the substrate current during stress is observed than under a (constant) low V o or peak substrate current stresses alone, which results in a somewhat faster degradation of the device than under the constant V G stress. It was concluded that this is due to trapping of electrons during the V o ~. V D phase on the holes injected during the V G ~ VT stress which slows the reduction of the drain electric field due to hole trapping [76].

Recently however, a small enhancement of the hot-carrier degradation in circuits operating at very high speed (>300Mhz) was observed [77]. Also, an increase of the degradation in NMOSFETs already stressed at V G ~. VT (hole injection), even after the stress conditions have been removed (VG-----VD=0) has been observed, albeit only in nitride paseivated or H-annealed samples [78]. In a PMOSFET, detrapping can help reduce the effect of a hot-carrier degradation [51]. All these observation indicates that MOSFETs do not behave rigorously quasi-statically, but the deviation is apparently relatively small. Several considerations reduce the effects of hot-carrier degradation on a digital circuit. For a NMOSFET in a circuit, degradation occurs only when V D is relatively high, and V G is in transition between VT and VD, with the worse degradation occurring close to VD/3...VD/2, so that the device is effectively under stress only a fraction (usually 1-10%) of the power-on time. Slowly rising gate voltages degrade the lifetime more than an increase of the capacitive load on the drain (which keeps the drain voltage high during the transitions) [79]. Furthermore, the gate delay may be much less affected than the linear on-current by hot-carrier degradation [80-81]. This is because the degradation of the DC parameters of the NMOSFET is usually measured in the linear regime (or in saturation but with the source and drain swapped) to increase the sensitivity of the measurement to the oxide degradation, while for MOSFETs operating in saturation, the degradation of the on-current is much smaller [37]. The effect of the hot-carrier degradation on the circuit delay are further reduced by the improvement of the on-current in a PMOSFET after stress, which partially compensates for the decrease of the current in the NMOSFET [81]. Measurements of the lifetime on real circuits have confirmed the relatively low sensitivity of the circuit speed to hot-carrier degradation [70-82], so that a more relaxed DC lifetime criterion should probably be used to realistically estimate the product lifetime, instead of the customary 10% degradation of the drain current or 1O0mV shift in VT. An important effect that may degrade the reliability of MOSFETs operating in a circuit is the the overvoltage resulting from the inductive noise due to the switching of currents in a CMOS circuit, or due to capacitive coupling between neighboring lines [83].

Hot-carrier degradation mechanisms in M O S F E T s To quickly estimate the hot-caxrier limited lifetime of a circuit, as a first step, a set of semianalytical approximate equations can be used [81, 84]. For in depth analysis, numerical simulation should be used. Most of the simulators calculate the age of a circuit using some simplified age functions based on equation 7 [81, 84-86]:

/

AgeNMOSFET---- (ID/W • Ha)" (Isua/ID) ran" dt and AgepMOSFET=

/ (1/HG)" (IG/W) rap- dt, (8)

where Hs, HG, mn and mp are empirically determined parameters - ideally measured for various gate and drain biases [87] - , and the hot-carrier currents Isu B and I G are calculated in the simulator using some analytical model whose fitting parametens are obtained from DC measurements [88]. A method to combine the various degradation mechanisms in a NMOSFET is explained in [89]. However, most of these simulators do not take into effect the already discussed combined effects of hole and electron injection [39, 79], post-stress generated interface states [78] and detrapping effects, and some neglect the degradation of PMOSFETs. To help identify the potential trouble spots on a chip, it has been proposed to use a sensitive microscope to locate MOSFETs which have the strongest hot-carrier generation by the light emission due to hot-carriers [7, 90]. Several studies have addressed the important issue of hot-carrier degradation in analog circuits [91], which are sensitive to VT mis-matching [92], increase of the output conductance [93] and noise

[67]. [9) SCALING EFFECTS ON HOT-CARRIER RELIABILITY] Hot-carriers are essentially a problem in short-channel MOSFETs, although the substrate and gate current can be easily observed in long channel devices also, and resulting stability problems can be a problem in some analog circuits [91]. Short-channel effects (SCE) (V T roll-off, DIBL) and the hot-carrier generation are linked by the fact that short-channel effects depend on the potential distribution, while hot-carrier depends on the electric field close to the drain. For instance, a MOSFET designed to have a reduced DIBL, will have a rapidly varying potential close to the drain, but that will also increase the drain electric field and the substrate current [94]. So any effort to reduce the short-channel-effect, by increasing the substrate doping, decreasing the oxide thickness, introducing halos around the drain [95] and reducing the junction depth, will also in principle increase the substrate current and thus reduce the hot-carrier limited reliability, in addition to the inevitable increase of the gLAT due to the channel shortening (if V D is kept constant). Furthermore, in short channel devices, the degraded zone of the channel becomes relatively a more important part of the channel, so that for a given oxide degradation, the current change is more important in a short channel device [96-97]. Indeed, fig. 4 shows that even when the

857

858

A. Acovic et al.

(as

oxide degradation

measured with charge pumping) is comparable in a LEFF=0.4pm and

LEFF=0.8pm NMOSFETs, the drain current degradation is nearly twice as big in the shorter device. Fortunately, in scaled down MOSFETs the reduction of the oxide thickness and of the power supply helps reducing the hot-carrier effect. Some authors claim that the gate oxide reduction is also helping by reducing the effect of a given oxide degradation in the NMOSFET [98, 99], but other studies show that when using the r . I D ~ (IsuB/ID) "m lifetime extraction method, the lifetime is not affected by the oxide thickness [91, 96]. In thin gate oxide PMOSFET's, the degradation is smaller, because of the reduced trapping rate. The power supply voltage is lowered to reduce the power consumption. Typically, in a LBFF=O.25pm technology, the power supply is 2.5V [11, and for a 0.15pro CMOS it is 1.8V only [4]. Fig. 3 shows that the reduction of the power supply voltage in a state of the art LBFF----0.15pm CMOS technology [4] lowers the substrate current sufficiently to more than compensate for the increase due to the channel length reduction, so that the hot-carrier problem becomes less of a concern.

It is interesting to note that in very short channel devices, a substrate current has been measured even at drain voltages below IV, where one would not expect carriers to have the energy

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Figure 4: Comparison of the change in charge pumping current (fig. a and b) and drain current (fig. c and d) for a LEFF-=0.Spm (fig. a and d) and for a LEFF=0.4/Jm (fig. h and d) NMOSFETs made with the same CMOS technology. The drain voltage was adjusted to have nearly the same substrate current I B in both devices. Charge pumping directly measures oxide degradation, which is similar in both devices, while the drain current degradation is twice as big in the shorter NMOSFET.

Hot-carrier degradation m e c h a n i s m s in M O S F E T s

required for impact ionization (>I.SV) [100]. However, since the energy distribution of the electrons is determined by the drain electric field and is broadened by various scattering mechanisms (notably phonons scattering), even at low drain voltages, a few of them will have sufficient energy to initiate impact ionization [100]. At low temperatures (77K), the thermal distribution of electrons is such that very few of them have an energy dose enough to the impact ionization threshold, so that the impact ionization is reduced at low VD, while it is slightly increased at higher VD's (compared to 300K) [20, 101-102]. Interestingly, the substrate current may be lower than expected in extremely short devices, because electrons do not have the time to thermalize in channel lengths comparable to the mean free path, so that their energy distribution is narrower, and there are fewer high-energy electrons that can cause problems [5, 103]. Similarly to the substrate current, no lower bound for the drain voltage at which hot-carrier degradation occurs has been observed, in spite of the 3.2eV potential barrier at the Si-SiO 2 interface [104]. This may be due to the energy gain in the drain electric field of a few very lucky hot-electrons helped by an Auger recombination mechanism providing the missing energy to be injected-into the oxide [105]. Fig. 3 also shows that there is a sizable NMOSFET degradation at the relatively low drain voltage of 2.3V. Concurrently with the channel length reduction, the channel width is also being reduced in modern MOSFETs. The parasitic very narrow edge device in Shallow Trench Insulation (STI) MOSFETs may degrade faster than the main channel device, but this effect should not be a problem except in devices with a very small W / L [106]. According to reference [106], the main (wide) device behaves similarly in LOCOS and STI MOSFETs.

[I0) EFFECTS Many

of the MOSFETs

OF TEMPERATURE]

parameters improve at low T (for instance 77K): the mobility

increases, the junction leakages decrease and the subthreshold slope improves, so that a reduction in temperature vastly improves the performance of a CMOS

integrated circuit, although it is not very

practical. The substrate current increases at low temperature

mainly because the drain current

increases, but ISUB/I s is fairly insensitive to temperature [20, 101-2, 107]. Above a crossover drain voltage VDX, ISUB/Is increases slightly, but below VDX , it decreases at low temperatures [101]~ as explained in section 9. The ratio of the gate current to the drain current IG/I s decreases more at low temperatures than ISUB/Is, and it has no cross-over voltage [102]. Due to an increase in electron trapping and a reduction of interface state generation in the NMOSFET

at low temperature, the degradation at V G ~ V D usually becomes more important than the

degradation at peak Isu B [108]. The effects of a given oxide degradation are increased at low temperature [42~ 109-110] probably because electrons have difficultiesovercoming the potential barrier due to the negatively charged degraded ~one, simply because their thermal energy is lower [100]. It is

859

860

A. Acovic et al.

also possible that a freeze-out of the impurities in the drain makes the NMOSFET more sensitive to electrons trapped deeper within the drain region [110]. As a result, NMOSFETs stressed at low temperature degrade much more than at room temperature. At higher temperatures, because of the decrease of I D and decrease of the mean free path, the substrate current decreases, and the degradation is expected to decrease [111]. A special case is the stres~ of MOSFETs at VG=0, because at high temperatures the off-current may become important and produce some hot-carrler induced degradation, similar in principle to the ordinary low V G stress conditions [112-113]. This effect could be important in PMOSFETs, because the off-current increases during stress. Also, at high temperatures, an increase of the degradation following a high VG ~, V D stress was observed, with some similarity to the Negative Bias Temperature Instability (NBTI) degradation mechanism [114]. Finally, at high temperatures, thermally generated minority carriers can be injected into the gate oxide from the reverse biased source or drain junctions

or the channel

depletion zone [40], degrading the junction and MOSFET's IV characteristics (substrate hot-carrier). This degradation mechanism can also happen at room temperature, by injection of minority carriers from neighboring forward bias junctions [40].

[11) E F F E C T S O F P R O C E S S I N G Processing of modern C M O S

ON HOT-CARRIER

DEGRADATION

I

circuits requires numerous plasma processing steps notably for

etching the polysilicon gates or metal lines [115-116] or depo6iting oxides by P E C V D

[117]. Because of

non-uniformities in the plasma, charging of the gates of the M O S F E T s can occur, resulting in tunneling of carriers through the oxide during processingl rendering the oxide more prone to damage due to hotcarriers and results in a larger dispersion of the degradation [118]. Anneals following the RIE steps are not very effective at removing the damage [119]. The best solution to reduce the charging problem appe~s to be improving the uniformity of the plasma, which can be achieved for instance by turning off the magnetic fieldsin the RIE tools [120] or using a protective dielectriclayer [121]. The reliability of P M O S F E T s

seems to be more sensitive to RIE charging than than that of N M O S F E T s

[118]. Ion

implantation of the gate and resistashing can also lead to charging during processing. X-ray lithography may be used to print 0.2pro or smaller MOSFET's gates. Initial work showed a degradation of the reliabilityof irradiated P M O S F E T s

[122] and N M O S F E T s

stressed at

V G ~ V T [123], in spite of the numerous thermal anneals following the X-ray irradiation, because of the remaining neutral traps. More recent work has shown that that problem is greatly relieved in advanced C M O S

technologies, because of the thin oxide required by device scaling, so that trapping is

greatly reduced [124-1251, and because of the reduced X-ray dose required for printing, thanks to the improved sensitivityof modern X-ray photo-resists. F~rly work [126] has shown that the SiN passivation layer that covers M O S F E T s

can also

degrade rellability~because it contains too much hydrogen that makes the oxide more vulnerable to

861

Hot-carrier degradation m e c h a n i s m s in M O S F E T s

hole injection. Humidity introduced in the metallisation and pnssivation level has been also shown to reduce the reliability of the MOSFETs, especially in the n-MOSFET [127-128]. Another concern is the mechanical stress that can be applied on a MOSFET by the pa~ivation layers, packaging or the use of nitrided oxides. Previous studies have shown that the stress due to pamivation can enhance hot-carrier induced degradation, which was attributed to the combined effect of H in the paseivation layer and the mechanical stress [129]. Recently, it was shown that the trapping and interface state generation rate by hot-carriers is unaffected by mechanical stress, but that hot-carrier generation is modified due to a piezoresistance effect through a mobility change [130]. Finally, in modern MOSFETs, due to the use of relatively low overlaps between the gate and the drain (to improve speed), care has to be exercised to keep sufficient overlap, to avoid injection of hot-carriers in the weakly overlapped region [131-133]. Also, in the case of a low overlap on the source side, the substrate current has an additional peak at V G ~. V D in addition to the ordinary peak close to V G ~ VD/2 and hot-carrier injection into the oxide may occur even on the source side (which is advantageously used in some EEPROMs) [133]. The angle of the implant, the profile of the polysilicon gate and the reoxidation after gate RIE have to be carefully designed to insure sufficient overlap, otherwise the reliability of the NMOSFET can be compromised.

[12) W A Y S

TO IMPROVE

HOT-CARRIER

To increase the reliabilityof a M O S F E T ,

L I M I T E D RELIABILITY[

the substrate current has to be reduced or the oxide

resistance to hot-carriers improved. There have also been suggestions of shifting the position of the maximum

drain electric field deeper in the channel, so that hot-carriers are generated farther away

form the Si-SiO 2 interface,which should reduce their probability to be injected into the oxide [134]. To reduce the substrate current, one can either use a more graded drain junction, by using P instead of, or in addition to As, or by using a so called Lightly-Doped-Drain (LDD), where part of the drain voltage is dropped in a relatively lightly doped drain extension not covered by the gate [135]. However, L D D

devices are more sensitive to hot-carriers injected above the lightly doped region,

because the oxide quality is usually worse in the spacer oxide above it, and this region is not controlled by the gate [131]. Gate-drain overlapped L D D ( G O L D ) and similar concepts try to avoid this problem by placing the L D D

region below the gate [136]. For an excellent review on LDD, see [137]. L D D

solutions are required for constant voltage scaling. For ideal constant field scaling [2], the reduction of the hot-carrier production due to the lower power supply is usually sufficientso that no additional steps are needed and simple abrupt junctions can be used, which also simplifies advantageously the process [1, 138]. Oxides annealed in NH3, reoxidized NH3, N 2 0 or N O or directly grown in N 2 0 or N O have been shown to be more resistant to interfacestate generation by hot-carriers,but somewhat more prone to electron trapping [139]. However, since interface state creation in a N M O S F E T

at peek substrate

862

A. Acovic et al.

current stress is usually the limiting factor, the increase in electron trapping which degrades the reliability of the PMOSFET and of the NMOSFET at V G ~. V D may not be a concern, so that nitridation is still beneficial. Various forms of furnace or RTP nitridation or even N implantation have been studied. RTA [140] or furnace N20 and NO seem to be some of the most promising solutions. Addition of F has also been shown to improve the oxide resistance to hot-carriers. In scaled PMOSFETs, the reduction of the oxide thickness naturally helps in reducing the trapping. Also, since the device degradation is due to channel shortening consecutive to electron trapping, any step that improves the short channel behavior of the PMOSFET also reduces the effect of a given oxide degradation, at least partially canceling the oegative effects of an increased high field in the drain consecutive to channel length reduction.

['!".3) HOT-CARRIER LIMITED RELIABILITY IN SOI MOSFETS[ SOl has recently gained popularity, due to improved starting materials, and an advantage in speed and density [141]. Estimation of reliability in SOI has been made difficult by the natural absence of a substrate contact, so that the substrate current cannot be measured. Since most of the lifetime estimate techniques in the NMOSFET use the substrate current, prediction of the SOl lifetime is difficult. Special structures can be designed to measure the substrate current, but they perturb the normal operation of a SOI MOSFET, and may not be representative of the majority of SOI MOSFETs which operate with a floating body [142]. A simple way around is to plot the log of the lifetime versus I/V D (because the substrate current -that cannot be measured- is roughly proportional to exp(A/VD) ), and extrapolate to the operating V D. It was also proposed to measure the light due to hotcarriers [6] and use it instead of the substrate current in the lifetime models [143]. Another possibility is to use the gate current even in the NMOSFET, although the gate current is hardly measurable under the worst stress conditions, and the degradation is small under the conditions where the gate current is measurable [142]. In a SOl PMOSFET, the gate current can easily be measured, so there are no problems with the PMOSFET lifetime estimate, but the PMOSFET reliability is anyway generally leas of a problem. In a SOI NMOSFET, the holes generated by the hot-carriers in the drain, accumulate in the floating substrate and can lead to the forward biasing of the source-substrate pn junction, and thus an additional current at low VG'S [144]. This can dramatically increase the off-current of the SOI NMOSFET. In properly designed SOI NMOSFETs this off-current is acceptable at the nominal VD, but the floating body problem can make accelerated testing at higher voltages and burn-in a problem. It also increases the degradation at low VG, by increasing the drain current at a time when the drain electric field is maximal [144]. Degradation can occur at the back oxide interface of SOl MOSFETs and by coupling to the front interface, it can also degrade the front channel current, especially in fully depleted SOl MOSFETs

Hot-carrier degradation m e c h a n i s m s in M O S F E T s

863

10 2 NMOSFET

~

• AI D / I D

DC str~

NMOSFET

AI D / I D

ring 9sc. stress /_

101

~

•-

10

C

Frequency degradation t._ ~lo lO-I

Stress Vdd =

8V

L e f f = 0 . 5 1 a m , T o × = 17.5nm

10 -2 10 0

........

(© IEEE 1994)

' ........ J ........ ' ........ ' ........ 101 10 2 10 3 10 4

105

Time (min.) Figure 5: NMOSFET linear drain current degradation and simulated ring-oscillator frequency degradation with PMOSFET degradation turned off. NTF and NSF are NMOSFET time and speed factors. Reproduced from [81] (© IEEE 1994).

[145-146]. This phenomenon is especially important in PMOSFETs [145-147]. The back gate stress can also change the intensity of the kink effect and the breakdown voltage of SOl MOSFETs [148]. It is still controversial whether the reliability of SOI MOSFETs is better or worse than their bulk counterparts [142, 147], but for low voltage applications, their reliability should not be a limiting factor, except for the problem of the burn-in.

114) CONCLUSIONSI Hot-carrier induced degradation has been studied now for nearly 25 years [149], but, due to the complexity of the device physics involved, is still a very active field, with many open questions. The detailed mechanisms that lead to oxide degradation are still controversial, and it is still not possible to predict ab imtZo the degradation of a MOSFET by simulation, although a lot of progress has been made.

The hot-carrler problem can be reduced by decreasing the drain voltage, but it will not disappear, even at very low voltages. Furthermore, the hot-carrier problem is exacerbated during burnin, as higher voltages are applied to the MOSFET, and in interface circuits between the internal 3.3V (or lower) and external bus at 5V. Together with the thermal dissipation considerations, the hot-cacrier problem determines the maximum power supply that can be applied on a CMOS chip, and thus directly influences the maximum performance that can be obtained from a given CMOS technology [1].

864

A. Acovic et al.

IREFERENCESI • [1] W.H. Chang, B. Davari, M.R. Wordeman, Y. Taur, C.C. Hsu, M.D. Rodriguez, "A high performance 0.25pm CMOS technology. 1. Design and characterization", IEEE Trans. El. Devices, Vol. ED-39, p. 959 (1992) • [2] R.H. Dennard, F.H. Gacnsslen, H.N. Yu, V.L. Rideont, E. Bassous, A. R. LeB[anc, "Design of ion-implanted MOSFETs with very small physical dimensions", IEEE J. Solid-State Circuits., Vol. SC-9, p. 256 (1974). • [3] D. Bursky, "ASIC family crams up to 1.2M usable gates/chip", Electronic Design, Vol. 41, p. i i i (1993). • [4] G.G. Shahidi, J. Warnock, A. Acovic, P. Agnello, C. Blair, T. Bucelot, A. Burghartz, E. Crabbe, J. Cressler, P. Coane, J. Comfort, B. Davari, S. Fischer, E. Ganin, S. Gittleman, J. Keller, K. Jenkins, D. K]aus, K. Kiewtniak, T. Lit, P.A. McFarland, T. Ning, M. Poicari, S. Subbana~ J.Y. Sun, D. Sunderland, A.C. Warren, C. Wong, "A high performance O.15pm CMOS', Tech. Dig. Syrup. VLSI Tech. 1993, p. 93 (1993). • [5]

J. Frey, "Where do hot-electrons come from?", IEEE Circuits~Devices Magazine, p. 31 (1991).

• [6] S. Tam, C. Hu, "Hot-electron-induced photon and photocarrier generation in silicon MOSFET's', IEEE Trans. Electron Devices, Vol. ED-31, p. 1264 (1984). • [7] C. Hu, S.C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, K.W. Terrill, ~Hot-electron-induced MOSFET degradation-Model, monitor, and improvement", IEEE Trans. Electron Devices, Vol. ED32, p. 375 (1985). • [8] W. Muller, L. Risch, A. Schutz, "Short-channel MOS transistors in the avalanchemultiplication regime", IEEE Trans. Electron Deviees~ Vol. ED-29, p.1778 (1982). • [9] F.-C. Hsu, P.-K. Ko, S. Tam, C. Hu, R.S. Muller, "An analytical breakdown model for shortchannel MOSFET's", IEEE Trans. Electron Devices, Vol. ED-29, p. 1735 (1982).

• [10] A. Schutz, S. Selberherr, H.W. Pntzl, "A two-dimensional model of the avalanche effect in MOS transistors", Solid State Electronics, Vol. 25, p.177 (1982). • [11]

S.M. Sze, "Physics of semiconductor devices", John Wiley & Sons, New York (1981).

• [12] P. Heremans, H.E. Maes, N. Saks, "Evaluation of hot-carrier degradation of n-channel MOSFETs with the charge pumping technique", IEEE Elec. Dev. Let., Vol. ED-7, p. 428 (1986). See also: G. Groeseneken, H.E. Maes, N. Beltran, R. F. De Keersmaecker, "A reliable approach to chargepumping measurements in MOS transistors", IEEE Trans. Electron Devices, Vol. ED-31, p.42 (1984). • [13] P.K. Ko, C. Hu, R.S. Muller, "A unified model for hot-electron currents in MOSFET's", in IEDM'81 Tech. Dig., p. 600 (1981). • [14] T.Y. Chan, P.K. Ko, C. Hu, "A simple method to characterize substrate current in MOSFET's", IEEE Electron Devices Lett., Vol. EDL-5, p. 505 (1984). • [15] E. Takeda, Y. Nakagome, 14. Kume, N. Suzuki, S. Asai, "Comparison of characteristics of nchannel and p-channel MOSFETs for VLSI', IEEE Trans. Electron Devices, Vol. ED-30, p. 675 (1983). • [16] K. Blotekjaer, "Transport equations for two-valley semiconductors", IEEE Trans. Electron Devices, Vol. ED-17, p. 38 (1970). • [17] B. Meinherzhagen, "Consistent gate and substrate current modeling based on energy transport and the lucky electron concept'~ Proc. IEDM'88, p. 504 (1988). • [18] W. H~nsch, M. Miura-Mattansch, "The hot-carrier problem in small semiconductor devices", J. Appl. Phgs, Vol. 60, p. 650 (1986). • [19] W. H~.nsch, S. Selberherr, "MINIMOS-3: a MOSFET simulator that includes energy balance", IEEE Trans. Electron Devices, Vol. ED-34, p. 1074 (1987). • [20] A.K. Henning, N.N. Chan, J.T. Watt, J.D. Plummet, "Substrate current at cryogenic temperatures: measurements and a two-dimensional model for CMOS technology, IEEE Trans. Electron Devices, Vol. ED-34, p. 64 (1985). • [21] W. Lee, S.E. Laux, M.V. Fischetti, G. Baccarani, A. Gnudi, J.M.C. Stork, J.A. Mandelman, E.F. Crabb~, M.R.. Wordemann, F. Odeh, "Numerical modeling of advanced semiconductor devices", IBM J. Res. Develop., Vol. 36, p. 208 (1992). • [22] E. Sangiorgi, M. R. Pinto, F. Venturi~ W. Fichtner, "A hot carrier analysis of submicrometer MOSFET's", IEEE Electron Devices Left., Vol. EDL-9, p. 13 (1988). • [23] E. Sangiorgi, B. Ricco, F. Venturl, "MOS2: An efficient MOnte Carlo ..qmulator for MOS devices~, IEEE Trans. Comp.- Aided Design, Vol. CAD-7, p. 259 (1988). • [24] M. Fischetti, S. Laux, "Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and zinc-blende structures-Part Ih submierometer MOSFET's", IEEE Trans. Electron Devices, Vol. ED-38, p. 650 (1991).

Hot-carrier degradation mechanisms in M O S F E T s • [25] F. Venturi, E. Sangiorgi, R. Brunetti, C. Jacoboni, B. [ticco, "Monte-Carlo simulation of electron heating in scaled deep submicron MOSFETs", Proc. 1EDM'89, p. 485 (1989). • [25] F. Venturi, C. Fiegna, A. Abramo, E. Sangiorgi, B. Ricco, "Hot-holes generation and transport in n-MOSFETs: a Monte-Carlo investigation", Proc. IEDM'90, p. 455 (1990). • [27] K.R. Hofmann, C. Werner, W. Weber, G. Dorda, "Hot-electron and hole emission effects in short n-channel MOSFET's ", IEEE Trans. Electron Devices, Vol. ED-32, p. 691 (1985). • [28] B. Eitan, D. Frohman-Bentchowsky, "Hot-electron injection into the oxide in n-channel MOS devices", IEEE Trans. Electron Devices, Yol. ED-28, p. 328 (1981). • [29] N.S. Saks, P.L. Heremans, L. Van der Hove, H.E. Maes, R.F. De Keersmacker, G.J. Declerck, "Observation of hot-hole injection in NMOS transistors using a modified floating gate technique", IEEE Trans. Electron Devices, Vol. ED-33, p.1529 (1986). • [30] Y. Nissan-Cohen, "A novel floating-gate method for measurement of ultra-low hole and electron gate currents in MOS transistors", IEEE Electron Devices Left., Vol. EDL- 7, p. 561 (1986).

• [31] P.E. Cotrell, R.R. Troutman, T.H. Ning, "Hot-electron emission in n-channel IGFET's', IEEE Trans. Electron Devices, Vol. ED-26, p. 520 (1979). • [32] S. Tam, P.K. Ko, C. Hu, "Lucky electron model of channel hot-electron silicon MOSFET's", IEEE Trans. Electron Devices, Vol. ED-31, p. 1116 (1984). • [33] S. Tam, P.-K. Ko, C. Hu, R..S. Muller, "Correlation between substrate and gate currents in MOSFET's", IEEE Trans. Electron Devices, Vol. ED-29, p. 1740 (1982). • [34] A. Schwerin, W. Haensch, "Gate currents and device degradation: carrier transport in gate oxides of MOSFET's ~, ESSDERC'88 (Montpellier), Proc. in Journal de physique, supplement to number 9, Vol 49, p. C4-647 (1988). • ~35] W. Haensch, M. Orlowski, W. Weber, "The hot-electron problem in submicron MOSFET ~, ESSDERC'88, Proc. in Journal de physique, suppl, to number 9, Vol 49, p. C4-597 (1988). • [36] W. HSzlsch, "Modeling hot-carrier reliability of MOSFETs: What is necessary and what is possible?",Proc. [EDM'92, p. 717 (1992). • [37] A.v. Schwerin, W. Haensch, W. Werner, "The relationship between oxide charge and device degradation: a comparative study of n- and p- channel MOSFET's", IEEE Trans. Electron Devices, Vol. ED-34, p. 2493 (1987). • [38] P. Heremans, R. Bellens, G. Groeseneken, H.E. Maes, "Consistent model for hot-carrier degradation in n-channel and p-channel MOSFET's", IEEE Trans. Electron Devices, Vol. ED-35, p. 2194 (1988). • [39] A.v. Schwerin, M.M. Heyns, W. Weber, "Investigation on the oxide field dependence of hole trapping and interface state generation in SiO 2 layers using homogeneous nonavalanche injection of holes", J. Appl. Phys., Vol. 67, p. 7595 (1990). • [40] T.H. Ning, "Hot-electron emission from silicon into silicon dioxide", Solid State Electr., Vol. 21, p. 273 (1978). • [41] C.T. Sah, "Models and experiments on degradation of oxidized silicon", Solid State Electronics, Vol 33, p. 147 (1990). • [42] J.Y.-C. Sun, M.R. Wordeman, "Degradation of 77K MOSFET characteristics due to channel hot-electron', IEEE Trans. Electron Devices, Vol. ED-31, p. 1970 (1984). • [43] N. Bergonzoni, B. Doyle, "Simulation of aging effects in MOS transistors", Proc. ESSDERC'87 (Bologna), G. Soncini (eds), p.721 (1987). • [44] P. Heremans, J. Witters, G. Groeseneken, H.E. Maes, "Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation", IEEE Trans. Electron Devices, Vol. ED-36, p. 1318 (1989). • [45] B.S. Doyle, M. Bourcerie, C. Bergonzoni, R. Benecchi, A. Bravis, K.R. Mistry, A. Boudou, "The generation and characterization of electron and hole traps created by injection during low gate voltage hot-carrier stressing of n-MOS transistors", IEEE Trans. Electron Devices, Vol. ED-37, p. 1869 (1990). • [46] S.K. Lai, "Two carrier nature of interface state generation in hole trapping and radiation damage", Appl. Phys. left., Vol. 38, p. 58 (1981). • [47] B.S. Doyle, M. Bourcerie, J.-C. Marchetaux, A. Houdou, "Interface state creation and charge trapping in the medium-to-high voltage range (VD/2 >_ V G >_ VD) during hot-carrier stressing of nMOS transistors", IEEE Trans. Electron Devices, Vol. ED-37, p. 744 (1990). • [48] J. Y Choi, P.K. Ko, C. Hu, W. Scott, ~Hot-carrier-induced degradation of metal-oxidesemiconductor field-effect transistors: oxide charge versus interface traps", J. Appl. Phys., Vol. 65, p.354 (1989). • [49] M. Koyanagi, A.G. Lewis, 3. Zhu, R.A. Martin, T.Y. Huang, J.Y. Chen, " Investigation and reduction of hot-electron induced punchthrough (HELP) effect in submicron PMOSFETs", in IEDM Tech. Dig., p. 722 (1986).

865

866

A. Acovic et al. • [50] R. Woltjer, G.M. Paulzen, "A new monitor to predict hot-carrier damage of PMOS transistors", Proc. IEDM'90, p. 561. • [51] M. Brox. E. Wohlrab, W. Weber, "A physical lifetime prediction method for hot-carrier stressed p-mos transistors", in IEDM'91 Tech. Dig., p. 625 (1991). See also: Q. Wang, M. Brox, W.H. Krautenschnieder, W. Weber, "Explanation and model for the logarithmic time dependence of pMOSFET degradation", IEEE Electron Devices Left., Vol. EDL-12, p. 218 (1991). • [52] R. Woltjer, G.M. Paulzen, "Oxide-charge generation during hot-carrier degradation of PMOSs', Proc. IEDM'93, p. 713. • [53] It. Woltjer~ A. Hamada, E. Takeda, "Time dependence of p-MOSFET hot-carrier degradation measured and interpreted consistently over ten orders of magnitude", IEEE Trans. Electron Devices, Vol. ED-40, p. 392 (1993). • [54] K. Mitsui, M. Inushui, S. Kusunoki, H. Oda, K. Tsukamoto, "Hot carrier degradation of O.5#m surface and buried channel PMOSFETs", Ext. Abstr. SSDM'89, p. 473 (1989). • [55] U. Schwalke, W. Hgnsch, A. Lill, "Comparative study of HC-degraation of NMOS and PMOS devices with n + and p+ gate: experiments and simulation", Ext. Abstr. SSDM'90, p. 307 (1990). • [56] Y. Nissan-Cohen, G.A. Franz, R.F. Kwasnick, "Measurement and analysis of hot-carrierstress effect on n-channel MOSFET's using substrate current characterization", IEEE Electron Devices Lett., Vol. EDL-7, p. 451 (1986).

• [57] A. Acovic, M. Ilegems, "Characterization of degradation due to hot-carriers in MOSFETs by the drain-substrate gate controlled tunnel diode", Solid State Devices, (ESSDEKC'87 Extend. Proc.) G. Soncini and P.U. Calzolari (eds.), (Elsevier, Amsterdam 1988). • [50] A. Acovic, M. Dutoit, M. Ilegems, "Characterization of hot-electron stressed MOSFETs by low temperature measurements of the drain tunnel current", IEEE Trans. El. Dev., Vol. 37, p. 1467 (1990). • [59] H. Sasaki, M. Saitoh, K. Hashimoto, "Hot carrier induced drain leakage current in n-channel MOSFETs", in IEDM Teeh. Dig., p.726 (1987). • [60] I.C. Chen, C.W. Teng, D.J. Coleman, A. Nishimura, "Interface-Trap enhanced gate-induced leakage current in MOSFET", IEEE Electron Devices Lett., Vol. EDL-1O, p. 216 (1989). • [61] Y. Igura, H. Matsuoka, E. Takeda, "New device degradation due to "cold" carriers created by band-to-band tunneling", IEEE Electron Devices Lett., Vol. EDL-1O, p. 227 (1989). • [62] I.C. Chen, D.J. Coleman, C.W. Teng, "Gate current injection initiated by electron band-toband tunneling in MOS devices", IEEE Electron Devices Left., Vol. EDL-10, p. 297 (1989). • [63] I.C. Chen, J.Y. Choi, T.Y. Chan, TY.C. Ong, C. Hu, "The effect of channel hot-carrier stressing on gate oxide integrity in MOSFET', IEEE Trans. El. Devices, Vol. ED-35, p. 2253 (1988). • [64] E. Itosenbaum, It. Rofan, C. Hu, "Effects of hot-carrier injection on n-and p-MOSFET gate oxide integrity", IEEE Electron Devices Lett., Vol. EDL-12, p. 599 (1991). • [65] K.F. Schuegraf, C. Hu, "Hole injection SiO 2 breakdown model for very low voltage lifetime extrapolation", IEEE Trans. Electron Devices, Vol. ED-41, p. 761 (1994). • [66] Y. Nishioka, Y. Ohji, T.P. Ma, "Gate-oxide breakdown accelerated by large drain current in n-channel MOSFET's", IEEE Electron Devices Lett., Vol. EDL-12, p. 134 (1991). • [67] K.K. Hung, P.K. Ko, C. Hu, Y.C. Cheng, "Flicker noise characteristics of advanced MOS technologies", Proe. IEDM'88, p. 34 (1988). • [68] C.T. Yao, M. Peckerar, D. Friedman, H. Hughes, "On the effects of hot-carrier stressing on MOSFET terminal capacitances", IEEE Trans. Electron Devices, Vol. ED-35, p.384 (1988). • [69] S.W. Sun, M. Orlowski, K.-Y. Fu, "Parameter correlation and modeling of the power law relationship in MOSFET hot-carrier degradation", IEEE Electron Devices Lett., Vol. EDL-11, p. 297 (1990). • [70] It. Woltjer, G.M. Paulzen, "Improved prediction of interface-trap generation in NMOSTs', IEEE Electr. Dev. Let., Vol. EDL-15, p. 4 (1994). • [71] C. Liang, H. Gaw, P. Cbeng, "An analytical model for self-limiting behavior of hot-carrier degradation in 0.25pro n-MOSFETs', IEEE Electron Devices Left., Vol. EDL-11, p. 569 (1992). • ['/2] H. Fang, P. Fang, J.T. Yue, "Hot-carrier-induced off-state current leakage in submicrometer PMOSFETs devices", IEEE Electron Devices Left., Vol. EDL-15, p.463 (1994). • [73] B.S. Doyle, K.it. Mistry, "A lifetime prediction method for hot-carrier degradation in surfacechannel p-mos devices", IEEE Trans. Electron Devices, Vol. ED-37, p. 1301 (1990). • [74] W. Weber, C. Werner, G. Dorda, "Degradation of n-MOS transistorss after pulsed stress", IEEE Electron Devices Left., Vol. EDL-5, p. 518 (1984). • ['/5] It. Bellens, P. Heremans, G. Grosseneken, H.E. Maes, W. Weber, "The influence of the measurement setup on enhanced ac hot-carrier degradation of MOSFET's", IEEE Trans. Electron Devices, Vol. ED-37, p. 310 (1990).

Hot-carrier degradation mechanisms in M O S F E T s • [76] M. Brox, W. Weber, "Dynamic degradation in MOSFET's- Part I: the physical effects", IEEE Trans. Electron Devices, Vol. ED-38, p. 1852 (1991). • [TIC] V.-H. Chan, T.E. Kopley, P. Marcoux, J. E. Chung, "High-frequency AC hot-carrier degradation in CMOS circuits", IEDM'94 Tech. Dig., p. 299 (1994). • [78] R. Bellens, E. de Schrijver, G. van den Bosch, G. Groeseneken, P. Heremans, H. E. Maes, "On the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors", [EEE Trans. Electron Devices, Vol. ED-41, p.413 (1994). • [19] W. Weber, M. Brox, T. Kunemuud, H.-M. Muhlhoff, D. Schmitt-Landsiedel, "Dynamic degradation in MOSFET's- Part II: applications in the circuit environment", IEEE Trans. Electron Devices, Vol. ED-38, p. 1859 (1991). • [80] J.A. van der Pol, J.J. Koomen, "Relation between the hot-carrier lifetime of transistors and CMOS SRAM products", Proc. IRPS'90, p. 178 (1990). • [81] K.N. Quader, P. Fang, J.T. Yue, P.K. Ko, P.K., C. Hu, "Hot carrier reliability design rules for translating device degradation to CMOS digital circuit degradation", IEEE Trans. Electron Devices, VoI.ED-41, p. 681 (1994). • [82] C. Duvvury, D. Redwine, H. Kitagawa, B.. Haas, Y. Chuang, C. Beydler, A. Hyslop, "Impact of hot-carriers on DRAM circuits", IEEE Proc. IRPS'87, p.201 (1987). • [83] K.R. Mistry, R. Hokinson, B. Gieseke, T.F. Fox, R.P. Preston, B. Doyle, "Voltage overshoot and N-MOSFET hot-carrier robustness in VLSI circuits", Proc. IEEE IRPS'9~, p.65 (1994). • [84] K.R. Mistry, T.F. Fox, R.P. Preston, N. D. Arora, B. Doyle, D. E. Nelsen, "Circuit design guidelines for n-channel MOSFET hot-carrier robustness", IEEE Trans. Electron Devices, Vol. ED-40, p.1284 (1993). • [85] P.M. Lee, M.M. Kuo, K. Seiki, P.K. Ko, C. Hu, "Circuit aging simulator (CAS)", IEDM'88 Techical Digest, p. 134 (1988). • [86] Y. Leblebici, S.-M. Kang, "Modeling and simulation of hot-carrler-induced device degradation in MOS circuits", IEEE I. Solid State Cir., Voh 28, p.585 (1993). • [87] M. Kuo, K. Seki, P.M. Lee, J.Y. Choi, P.K. Ko, C. Hu, "Quasi-static simulation of hotelectron-induced mosfet degradation under AC (pulse) stress", IEDM'87 Tech. Dig., p. 47 (1987). • [88] N.D. Arora, M.S. Sharma, "MOSFET suhstrate current model for circuit simulation", IEEE Trans. Electron Devices, VoI. ED-87, p. 1392 (1991). • [89] K.R. Mistry, B. Doyle, "AC versus DC hot-carrier degradation in n-channel MOSFET's", IEEE Trans. Electron Devices, Vol. ED-40, p.96 (1993). • [90] N. Tsutsu, Y. Uraoka, Y. Nakata, S. Akiyama, H. Esaki, "New detection method of hotcarrier degradation using photon spectrum analysis of weak luminescence on CMOS VLSI', Proc. IEEE 1990 Int. Conf. on Microelectronic test struciures", p. 143 (1990). • [91] T.Y. Chan, C.L. Chiang, H. Gaw, "New insight into hot-electron-induced degradation of nMOSFET's', in IEDM Tech. Dig., p. 196 (1988). • [92] J. Chung, K.N. Quadder, C. G. Sodini, P.-K. Ko, C. Hu, "The effects of hot-electron degradation on analog MOSFET performance", Proc. IEDM'90, p. 553 (1990). • [93] P~. Thewes, M. Brox, G. Tempel. W. Weber, "Hot-carrier degradation of p-MOSFET's inanalog operation: the relevance of the channel length-independent drain conductance degradation", Proc. IEDM'92, p. 531 (1992). • [94] F. Bauer, S. C. Jain, J. Korec, V. Lauer, M. Offenberg, P. Balk, "Incompatibility of requirements for optimizing short channel behavior and long term stability in MOSFETs', Solid-State Electronics, Vol. 31, p. 27 (1988). • [95] C.F. Codella, S. Ogura, "Halo doping effects in suhmicron DI-LDD device design", Proc. IEDM'85, p. 230 (1985). • [96] P. Woerlee, P. Damink, M. van Dort, C. Juffermans, C. de Kort, H. Lifka, W. Manders, G. Paulzen, H. Pomp, J. Slootboom, G. Streuker, R. Woltjer, "The impact of scaling on hot-carrier degradation and supply voltage of deep-submicron NMOS transistors", Proc. IEDM'91, p. 537 (1991). • [97] T.Y. Chan, H. Gaw, "Performance and hot-carrier reliability of deep-submicrometer CMOS', in IEDM'89 Tech. Dig., p. 71 (1989). • [98] M. Yoshida, D. Tohyama, K. Maeguchi, K. Kanazaki, "Increase of resistance to hot-carriers in thin oxide MOSFETs", Proc. IEDM'85, p. 254 (1985). • [99] Y. Toyoshima, H. Iwai, F. Matsuoka, H. Hayashida, K. Maeguchi, K. Kanzaki, "Analysis of gate-oxide thickness dependence of hot-carrier induced degradation in thin gate oxide uMOSFETs", IEEE Trans. Electron Devices, Vol. ED-37, p.1498 (1990). • [I00] S. Tam, F.-C. Hsu, C. Hu, I~.S. Muller, P.-K. Ko, "Hot-electron currents in very short channel MOSFET's', IEEE Electron Devices Lett., Vol. EDL-4, p. 249 (1983). • [101] B. Eitan, D. Frohman-Bentehowsky, J. Shappir, "Impact ionization at very low voltages in silicon", J. Appl. Phys., Vol.53, p.1244 (1982).

867

868

A. Acovic et al. • [102] D. Esseni, L. Selmi, It. Bez, E. Sangiorgi, B. Pdcco, ~Bias and temperature dependence of gate and substrate currents in n-MOSFETs at low drain voltage", Proc. IEDM'94, p. 307 (1994). • [103] G.G. Shadidi, D.A. Antoniadis, H.I. Smith, "Reduction of channel hot-electron generated substrate current in sub-150 nm channel length Si MOSFET's", IEEE Electron Devices Left., Vol. EDL-9, p. 497 (1988). • [104] J. Chung, M.-C. Jeng, J.E. Moon, P.K. Ko, C. Hu, "Low-voltage hot-electron currents and degradation in deep submicrometer MOSFETS', Proc. IEDM'89, p. 92 (1989). • [105] E. Sangiorgi, B. Ricco, P. Olivo, "Hot electrons and holes in MOSFET's biased below the SiSIO 2 interfacial barrier", IEEE Electron Devices Leit., Vol. EDL-6, p. 513 (1985). • [106] B. Doyle, It.S. O'Connor, K.it. Mistry, G.J. Grula, "Comparison of shallow trench and LOCOS isolation for hot-carrier resistance", IEEE Electron Devices Lett., Vol. EDL-12, p.673 (1991). • [107] J.H. Huang, G.B. Zhang, Z.H. Liu, J. Duster, S.J. Wann, P. Ko, C. Hu, "Temperature dependence of MOSFET substrate current", IEEE Electron Devices Left., Vol. EDL-14, p. 268 (1993). • [108] P. Heremans, Y.-C. Sun, G. Groeseneken, H.E. Maes, "Evaluation of channel hot carrier effects in n-MOS transistors at 77 K with the charge pumping technique", Appl. Surface Science, Vol. 30, p.313 (1987). • [1091 P. Heremans, G. van den Bosch, It. Bellens, G. Groeseneken, H. E. Maes, "Understanding of the temperature dependence of channel hot-carrier degradation in the range 77 to 300K",Proc. IEDM'89, p. 67 (1989). • [110] A. Acovic, M. Dutoit, M. llegems, "A study of the increase of the effects of hot-carrier stress on NMOSFETs at low temperature", IEEE Trans. Electron Dev., Vol. 36, p. 2603 (1989). • [111] F.-C. Itsu, K.Y. Chiu, "Temperature dependence of hot-electron induced degradation in MOSFET's', IEEE Electron Devices Lett., Vol. EDL-5, p. 148 (1984). • [112] J. Chen, T.Y. Chan, P.K. Ko, C. Hu, "Gate current in OFF-state MOSFET", IEEE Electron Devices Left., Vol. EDL-10, p. 203 (1989). • [113] B.S. Doyle, K.it. Mistry, "Hot-carrier stress damage in the gate "offf-state in n-channel transistors", IEEE Trans. Electron Devices, Vol. ED-39, p. 1774 (1992). • [114] B.S. Doyle, B.J. Fishbein, K.It. Mistry, "NBTI-enhanced hot-carrier damage in p-channel MOSFET's', Proe. IEDM'91, p. 529 (1991). • [115] C.T. Gabriel, J.P. McVittie, "How plasma etching damages thin gate oxides", Sol. State Tech., Vol. 35, p. 81 (1992). • [116] H. Shin, N. Jha, X-Y. Qian, G. W. Hills, C. Hu, "plasma etching charge-up damage to thin oxides", Solid State Tech., Vol 35, p. 29 (1993). • [117] F. Shone, K. Wu, J. Shaw, E. Hokelek, S. Mittal, A. Haranahalli, "Gate oxide charging and its elimination for metal antenna capacitor and transistor in VLSI CMOS double layer metal technology", Tech. Dig. Syrap. VLSI Tec. 1989, p. 73 (1989). * [118] K.It. Mistry, B.J. Fishbein, B.S. Doyle, "Effect of plasma-induced charging damage on nchannel and p-channel MOSFET hot-carrier reliability", Proc. IEEE IRPS'94, p.42 (1994). • [119] J.C. King, C. Hu, "Effects of low and high temperature anneal on process-induced damage of gate oxide", IEEE Electron Devices Lett., Vol. EDL-15, p. 475 (1994). • [120] M.It. Lin, P. Fang, F. Heiler, R. Lee, R. l~kkhit, L. Shen, "Characterization and optimization of metal etch processes to minimize charging damage to submlcron transistor gate oxide", IEEE Electron Devices Lett., Vol. EDL-15, p. 25 (1994). • [121] C.T. Gabriel, M.G. Weling, "Gate oxide damage reduction using a protective dielectric layer", IEEE Electron Devices Lett., Vol. EDL-15, p. 269 (1994). • [122] C.C.-H. Hsu, L.K. Wang, M.It. Wordeman, T.It. Ning, "Hot-electron induced instability in O.5/~m p-channel MOSFET's patterned using synchrotron lithography", IEEE Electron Devices Left., Vol. EDL-10, p. 327 (1989). • [123] J.Y.-C. Sun, J.It, Maldonado, M.D. Rodriguez, J. Laskar, D.S. Zicherman, "Effects of X-ray irradiation on the channel hot-carrier reliability of thin oxide n-channel MOSFETs", Proc. SSDM'1986, p. ~79 (1986). • [124] M. Waiters, A. Iteisman, "The distribution of radiation-induced charged defects and neutral electron traps in SIO2, and the threshold voltage shift dependence on oxide thickness", J. Appl. Phys., Vol. 67, p.2992 (1990). • [125] A. Acovic, C.C.H. Hsu, L.C. Hsia, J.M. Aitken, "Reduced hot carrier reliability degradation of X ray irradiated MOSFETs in a 0.25pm CMOS technology with ultra thin gate oxide", Solid State Electr., Vol.36, p.1353 (1993) • [126] It.B. Fair, It.C. Sun, "Threshold voltage instability in MOSFET's due to channel hot-hole emission", IEEE Trans. Electron Devices, Vol. ED-28, p. 83 (1981). • [127] Y.H. Lee, S. Hut, B. Sabi, "Evaluation of moisture induced hot-carrier degradation of n- and p-MOSFETs using steam stress", IEDM'98 Techical Digest, p. 523 (1993).

Hot-carrier degradation mechanisms in M O S F E T s • [128] N. Shimoyama, K. Machide, J.-I. Takahashi, K. Murase, K. Minegishi, T. Tsuchiya, "Enhanced hot-carrier degradation due to water-related components in TEOS/O 3 oxide and water blocking with ECR-SIO 2 film", [EEE Trans. Electron Devices, Vol. ED-40, p. 1682 (1993). • [129] J. Mitsushashi, S. Nakao, T. Matsukawa, "Mechanical stress and hydrogen effects on hotcarrier injection", IEDM'86 Teehical Digest, p. 386 (1986). • [130] R. Degraeve, I. de Wolf, G. Groseneken, H.E. Maes, "Analysis of externally imposed mechanical stress effects on the hot-carrier induced degradation of MOSFETs", Proc. IRPS'9i, p. 29 (1994). • [131] F.-C. Hsu, H.R. Grinolds, "Structure-enhanced MOSFET degradation due to hot-electron injection", IEEE Electron Devices Lett., Vol. EDL-5, p. 71 (1984). • [132] F.-C. Hsu, J. Hut, K.Y. Chiu, "Hot electron degradation in submicron VLSI"", Proc. IEDM'85, p. 48 (1985). • [133] P.K. Ko, T.Y. Chan, A.T. Wu, C. Hu, "The effects of weak gate-to-drain (source) overlap on MOSFET characteristics", in IEDM Teeh. Dig., p. 292 (1986). • [134] S. Bampi, J.D. Plummet, "Modified LDD device structures for VLSI", in IEDM Tech. Dig., p.234 (1985). • [135] S. Ogura, P.J. Tsang, W.W. Walker, D. Critchlow, J.F. Shepard, "Design and characteristics of the lightly doped drain-seurce (LDD) insulated gate field-effect transistor", IEEE Trans. Electron Devices, Vol. ED-27, p. 1359 (1980). • [133] R. Izawa, T. Kure, S. Iijima, E. Takeda, "The impact of gate-drain overlapped LDD (GOLD) for deep submicron VLSI's", in IEDM Tech. Dig., p. 32 (1987). • [137] J.J. Sanchez, K.K. Bsueh, T.A. DeMassa, "Drain-engineered hot-electron-resistant device structures: a review", IEEE Trans. Electron Devices, Vol. ED-36, p.1125 (1989). • [133] A. Bryant, B. E1-Jareh, T. Furukawa, W.P. Noble, E.J. Nowak, W. Schwittek, W. Tonti, "A fundamental performance limit of optimized 3.3V sub-quarter-micrometer fully overlapped LDD MOSFET's", IEEE Trans. Electron Devices, Vol. ED-39, p. 1208 (1992). • [139] H.S. Momose, T, Morimoto, Y. Ozawa, M. Tsuchiaki, M. Ono, K. Yamabe, H. Iwai, "Very lightly nitrided oxide gate MOSFETs for deep-sub-micron CMOS devices", IEDM'91 Teehical Digest, p. 359 (1991). • [140] H. Hwang, W. Ting, D.-L. Kwong, J. Lee, "Improved reliability characteristcs of submicrometeter nMOSFET's with oxynitride gate dielectric prepared by rapid thermal oxidation in N20", IEEE Electron. Dev. let., Vol. EDL-12, p. 495 (1991). • [141] G.G. Shahidi, T.H. Ning, T.I. Chappell, J.H. Comfort, B.A. Chappell, R. Franch, C.J. Anderson, P.W. Cook, S.E. Schuster, M.G. Rosenfield, M.H. Polcari, R.H. Dennard, B. Davari, "SOl for a 1-volt CMOS technology and application to a 512 Kb SHAM with 3.5 ns access time", Proc. IEDM'93, p. 813 (1993). • [142] Z.J. Ma, H.J. Wann, M. Chan, J. King, Y.C. Cheng, P.K. Ko, C. Hu, "Characterization of hot-carrier effects in thin-film fully depleted SOI MOSFETs", Proc. IRPS'9~, p. 52 (1994). • [143] T. Makino, S. Kawamura, "A study of hot-carrier effects in SOI MOSFETs using photon emission", Ext. Abs. of ~he 1991 Int. Conf. on Solid State Devices and Mat., p. 20 (1991). • [144] ILJ.T. Bunyan, M.J. Uren, N.J. Thomas, J.R. Davis, "Degradation in thin-film SO1 MOSFET's caused by single-transistor latch", IEEE Electron Devices Left., Vol. EDL-11, p.359 (1990). • [146] T. Ouisse, S. Cristoloveanu, G. Borel, "Hot-carrier-induced degradation of the back interface in short-channel Silicon-on-Insulator MOSFET's", IEEE Electron Devices Lett., Vol. EDL-12, p. 290 (1991). • [146] T. Ouisse, A.J. Auberton Herv~, B. Giffard, G. Reimbold, "Hot-carrier-induced degradation mechanisms in short-channel SIMOX p-MOSFET's", Microelectronies Eng. (Proc. ESSDERC'92), Vol. 19, p. 473 (1992). • [147] T. Tsuchiya, T. Ohno, Y. Kado, J. Kai, "Hot-carrier induced degradation in ultra-thin, fullydepleted, deep submlcron NMOS and PMOS SOl transistors", Proe. IRPS'9~, p. 57 (1994). • [148] B. Zhang, T.P. Ma, "Back-cahhenl hot-electron effects on the front channel characteristics in thin-film SOl MOSFET's', IEEE Electr. Dev. Let., Vol. EDL-12, p. 699 (1991). • [149] H. Hara, Y. Okamoto, H. Ohnuma, "A new instability in MOS transitor caused bu hot electron and hot hole injection from drain avalanche plasma into gate oxide", ,lap. J. of Appl. Phys., Vol. 9, p. 1103, (1970). • [154}] T.Y. Chan, J. Chen, P.K. Ko, C. Hu, "The impact of gate-induced drain leakage current on MOSFET scaling", Proc. IEDM'87, p. 718 (1987).

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