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A review of safe operation area
Microelectronics Journal 37 (2006) 661–667 www.elsevier.com/locate/mejo
A review of safe operation area Zhilin Sun, Weifeng Sun*, Longxing Shi National ASIC System Engineering Research Center, Southeast University, Jiangsu, Nanjing 210096, China Received 30 May 2005; received in revised form 24 July 2005; accepted 26 July 2005 Available online 12 September 2005
Abstract For designing LDMOS, SOA is an important and complex parameter which is defined by current, voltage, waveform, pulse time, etc. In this paper, short-term and long-term factors that determine the SOA boundary are demonstrated. Methods to improve SOA are enumerated. q 2005 Elsevier Ltd. All rights reserved.
1. Introduction With the feature size reducing, power devices benefit a lot from decreasing device area. But they are not on the same evolutionary curve as logic or mixed-signal. This is mainly because of breakdown voltage and power density limits, as dictated by device physics, demanding a nearly constant minimum device size. This means that only the modest area decrease can be made as line widths and contact dimensions are made smaller, which makes the power devices dominate in the whole chip area. To reduce the cost and save the chip area, it is a paramount for the power device designer to have a thorough understanding of what is needed to meet the applications, which are the main limitation factors of reducing the power device area. As the most important member of power device, lateral double-diffused MOS (LDMOS) has been widely used in many power electronic applications, such as power converters, motor controllers, and automotive electronics, due to not only their high switching speed, high input impedance and good thermal stability, but the compatibility for integration into a modern BiCMOS technologies. Traditionally, the tradeoff between breakdown voltage (BVdss) and on-resistance (Rdson) is familiar and frequently used to choose the LDMOS area, using RdsonZ Rsp/A, where Rsp is the specific on-resistance and A is * Corresponding author. Tel.: C86 25 379 5811x8401; fax: C86 25 335 2764. E-mail address: [email protected] (W. Sun).
0026-2692/$ - see front matter q 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2005.07.006
the device area (The top of the triangle in Fig. 1). However, the area achieved by this approach may or may not meet SOA requirements. Then another criterion must be added to the traditional tradeoff design of LDMOS forming Fig. 1 [1], the LDMOS design triangle. In traditional designs, increasing BVdss can improve SOA and increase Rdson simultaneously. This is shown by the aiding arrow on the left and the conflicting arrow on the right. Adding a region, whose impurity concentration is higher than the drift region while lighter than the drain region, between the drift and the drain, a more rectangular SOA and a reduced Rdson can be achieved, which is represented by the conflicting arrow on the left side and the aiding arrow on the right side. The term ‘Safe Operation Area’ is used to describe the region in the IdKVds plane through which the device can switch without suffering damage. Fig. 2 shows a sketch of an Id vs. Vds curve for fixed Vgs. As the operating point approaches the SOA boundary, the slope of the curve increases and eventually becomes infinite at the boundary. Beyond this ‘snapback’ point, the device exhibits negative resistance and fulmination occurs, usually with accompanying damage to the device. The determination of SOA is not a simple matter. Current, voltage, waveform, stress time, and temperature are all involved in defining the SOA. Furthermore, the usual reliance on experimental data as a design check is complicated by the fact that measurements are nearly always destructive. Fig. 1 represents a much larger set of modeling, simulation, and measurement complexity than do BVdss or Rdson. In this paper, all kinds of factors limiting the SOA are enumerated. The methods for solving all these problems are demonstrated.
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Fig. 1. LDMOS design triangle showing tradeoffs that affect device area.
2. Short-term SOA 2.1. Electrical effect 2.1.1. Kerk effect At high current density, the moving carriers influence the depleted charge, which result in higher electric field near n/nC junction. This is called Kirk Effect. Fig. 3 [2] demonstrates this phenomenon. In the on-state, significant amount of negative charge adds to the positive space charge of the n-type drift region. It leads to a shift of the potential lines towards the drain. For application, the effect means the use of a longer drift region or less current per gate width. Several methods have been proposed to alleviate Kirk effect. Adding an n buffer region, whose concentration is higher than the drift region while lighter than the drain region, has been well-know [3–6]. A much more effective method, linearly doped drift region, is put forward in [7]. The graded dopant with the increasing concentration toward the drain makes the electric field uniform in the drift region. The graded doped drift is implemented by implanting only one time. The mask and the impurity concentration after diffusion is show in Fig. 4. In [8], a Double RESURF technology (Seen in Fig. 5) was put forward to improve SOA. An nC buried layer, which is externally tied to the drain terminal, is added to the conventional LDMOS, which is used to share the carrier in the on-state. Consequently, with about 60% decrease of the current density, Kirk effect is alleviated.
Fig. 3. Shift of potential lines by Kirk effect at 250 V in 500 V-LDMOS. (a) low Ids (b) high Ids.
Fig. 4. Demostration of achieving linearly graded doped drift region.
develops across the body–source junction. The forward bias is due to Ib supplied by the carrier generation mechanisms indicated in Fig. 6. And Ib can be written as: Ib Z ðMn K1Þ !Is C Idiff C Igen
(1)
Where Is is the on-state drain current, Idiff is the reverse leakage current and Igen is the generation current. (MnK1)Is
2.1.2. Intrinsic parasitic triode In all MOS transistors, there is a parasitic triode that can be turned on when a sufficient ‘base-emitter’ voltage
Fig. 2. Schematic of the SOA boundary. The SOA boundary is defined by the onset of negative resistance at Id vs. Vds curve.
Fig. 5. Schematic cross-section and current flowline of (a) single RESURF LDMOS with substrate grounded and (b) double RESURF with NBL externally tied to drain terminal.
Z. Sun et al. / Microelectronics Journal 37 (2006) 661–667
Fig. 6. Circuit model of LDMOS showing the intrisic triode.
is the current due to impact ionization. It arises from channel primary current Is producing secondary carriers in the drift region, which then drift backward to the source. Mn depends on electric field. Three peak electric fields along Si/SiO2 interface (Seen in Fig. 7) determine the magnitude of Mn. The leftmost peak electric field in Fig. 7 is determined by the impurity concentration of n-well. The other two peak ones are determined by the impurity concentration of drift region as is well-known. When one of the three peak values is close to critical electric field, the first term in the right hand of (1) dominates. Fig. 8 shows Vbe of parasitic triode that is sufficient to turn-on the triode. Vbe is the combination of impact ionization, channel current Is, and shunting resistor R. With the increase of Vds, three peak electric fields in Fig. 7 dominate successively. The parasitic triode turns on when one of the peak electric field reaches critical electric field and Mn is sufficient that the voltage drop in the resistor is equal to or lager than Vbe. Simultaneously, the IdsKVds curve snapbacks. Unless some protect measures are implemented, second breakdown happens and irresistible damage is done to the device. Abundant research has been done on the turning on of the parasitic triode. LDMOS with the gate extended over field oxide has an enhanced SOA [9] The raised up gate field
Fig. 7. Electric field profile along Si/SiO2 interface of LDMOS.
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Fig. 8. Substrate-source voltage or Base-emitter voltage of parasitic triode vs. Vds (supposing temperature is constant).
plate lowers the middle peak electric field in Fig. 7. Therefore, Mn is reduced and the SOA enhanced. And it is also shown that the gap between the edge of the gate and the nC drain has a significant effect on SOA. One effective way to improve SOA is to reduce Rb. Moving the heavily doped ohm contact closer to the poly gate will of course reduce Rb. But this extreme case will restrict channel current and increase Rdson. In [10], a simple layout improvement is proposed. By alternating sources and drains, checkerboarddesigned arrays are put forward (Seen in Fig. 9). The X-shaped pC contact can overlap the gate in the corners minimizing any increase in Rdson. For snapback is usually irresistible, measures are necessary to implement to protect the device. A selfprotection DMOS is proposed in [11], which can be seen in Fig. 10. With the additional pC body diffusion, Zener diode is formed at the bottom of the p-type body region. Firstly, the heavily doped pC region lowers the base resistance of Rb. Secondly, the breakdown voltage is controlled by the Zener diode independent of other DMOS characteristics. Consequently, when high voltage is applied to the device, breakdown occurs only at the bottom of p-body region. Avalanche current flows through the low resistivity pC body region, not passing through the high resistivity rim of the p-body region, which protect the device from second breakdown. In [12], a self-protect device is improved by adding a field ring, which enhanced the avalanche capability.
Fig. 9. Layout of checkerboard sources and drains for a conventional pC contanct (left) and X shaped pC contact (right). The X-shaped pC array has improved SOA due to reduced body resistance Rb, while minimizing lost gate width.
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the source. The temperature at which the device shown in Fig. 7 fails must be reached about 725 K [16]. With the increase of the intrinsic carrier concentration, leakage current of a reverse-biased p–n junction increases dramatically. At a reverse-bias greater than a few tenths of a volt and temperature below 1000 K, the I–V character of a p–n diode is approximated by [17]: " rffiffiffiffiffiffi # Dp W ni (3) Idiff ZKQAni C 2t ND t
Fig. 10. Cross-section views of the rugged DMOS.
2.2. Electrical–thermal effect 2.2.1. Thermal effect With temperature increase, a number of factors inside and outside the semiconductor limit the operation of the electronic devices and circuits [13]. Every semiconductor has a certain number of thermal electron and hole carriers presented in the crystal. The concentration of these intrinsic carriers is exponentially dependent upon the temperature of the semiconductor [14]: pffiffiffiffiffiffiffiffiffiffiffi ni Z Nc Nv eKEG =2KT (2)
Together with (2), we get that the reverse-biased junction leakage current harmful to devices and circuits operation increases exponentially with temperature. Another fundamental leakage mechanism in devices is the transport carriers that gain sufficient energy to go over or tunnel through an energy barrier in a device structure. The current due to carrier emission as a function of temperature and applied voltage is approximated by [18] Igen ZKAK T 2 eKqfB =KT
(4)
where fB is the potential barrier height of the junction and K* is the effective Richardson constant of the semiconductor. This process called emission, increases with temperature as carriers gain more thermal energy.
where T is the temperature (in Kelvin), K is the Boltzmann constant, EG is the energy bandgap of the semiconductor measured in electronvolts, and Nc and Nv are the effective electron and hole density of states, respectively. The temperature dependence of the intrinsic carrier concentration calculated from (2) is shown in Fig. 11. Some authors [15] associate the fail of the semiconductor device with the intrinsic temperature of the substrate, which is defined by solving ni(T)ZNsub. For NsubZ5!1015 cmK3, this gives TfailZ603 K. In fact, if it comes to the device shown in Fig. 7, it is not until the intrinsic concentration exceeds the n-well concentration that the drain punches through
2.2.2. Electrical–thermal coupling The circuit model is much more complex when the thermal effect is concerned. Fig. 12 follows a similar format to Fig. 6, but in a much more accurate way concerning the thermal effect. As is shown in Fig. 12, the solid black lines represent the normal operation path. The gray dashed lines are added when the device temperature is high. As temperature is increased well above room temperature, there are three distinct differences between Figs. 6 and 12. Firstly, the ability of carriers to move through a semiconductor crystal decreases. This arises because atoms in the crystal lattice have more thermal vibrational energy that results in more collisions with carriers moving through the crystal in response to an electric field. The increase in semiconductor device resistance with
Fig. 11. Semiconductor intrinsic carrier concentration versus temperature.
Fig. 12. Circuit model of LDMOS including electrical–thermal effect.
Z. Sun et al. / Microelectronics Journal 37 (2006) 661–667
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temperature follows the formulation: R Z R0 ð1 C T x Þ
(5)
where R0 is the value of semiconductor device resistance R in room temperature and x is usually between 1.5 and 2.5 for most semiconductor [19]. Consequently, Rb, Rs and Rd in Fig. 12 increase with the temperature increase in the following formula: Rb Z Rb0 ð1 C T x Þ
(6)
Rs Z Rs0 ð1 C T x Þ
(7)
x
Rd Z Rd0 ð1 C T Þ
(8)
Secondly, the last tow terms on the right hand of (1) will dominate gradually at high temperature described by (3), (4). Lastly, base-emitter voltage needed to turn on the parasitic triode has a negative temperature coefficient in the range of 1.6–2 mV/K as the following formula kT Jc Vbe Z ln (9) q JsðTÞ where Jc is the collector current density, which is presumed fixed, Js is the saturation current density. The snapback voltage, at which the parasitic diode turns on, is difficult to be predicted due to all these thermal effects. A rough tendency is demonstrated in Fig. 13. On the left of the peak vale, the first term on the right hand of (1) dominates. With the increase of temperature, Rs and Rd decrease inducing current decrease even if the drain voltage increases [20]. The impact ionization current is decreased due to the lowered source to drain current and the decreased mean free path. Accordingly, the snapback voltage increases. On the right side of the peak vale, the last two terms on the right hand of (1) dominate. Therefore, the snapback voltage decreases with the increase of temperature. At about 800 K got by solving (9)Z0, the device can no longer work. 2.2.3. Self-heating In the nonisothermal consideration of LDMOS, selfheating is essential to understand the operation limit of LDMOS. Self-heating refers to the condition when charge carriers are not able to transfer their excess energy to the lattice efficiently [21]. A temperature difference is created between electrons and the lattice resulting in localized
Fig. 13. Snapback voltage of LDMOS versus ambient temperature. Presuming the device is isothermal.
Fig. 14. Substrate-source or Base-emitter voltage vs. temperature of the parasitic triode.
heating in the active area of the device. The localized heating is maximum, where electric field is maximum. When a voltage lower than the breakdown voltage is applied to the drain, the second peak electric field in Fig. 7(b) is the maximum one. Hot spot locates in the nwell–drift junction (Seen in Fig. 7(a)). Compared to this hot spot, temperature rise in other area of the device is neglectable [22] In this case, Idiff, Igen and Rb increase dramatically for the hot spot is near the p–n junction and the channel, whereas the change of Rd (Fig. 12) is neglectable. Combining (3), (4), (6) and (9), Fig. 14 is got to show qualitatively how the parasitic triode turns on in response to an increasing temperature of self-heating. The two lower curves (the solid, where Mn is one and dashed curve, where there is significant impact ionization) represent the voltage drop in the base resistor of the parasitic triode due to Ih. The device fails at Tcrit, where the Vbe and IhRb curves across (Fig. 14). Fig. 15 [23,24] shows the transient behavior with the change of the input power at an ambient temperature of 300 K. At higher starting current, the rate of the temperature rise is much larger and eventually, the parasitic triode turns on and the device fails, whereas the device with lower starting current reaches the steady state. Consequently, SOA of LDMOS will decrease dramatically because of selfheating.
Fig. 15. Transient eletrothermal simulation with different starting current levels for a given ambient temperature.
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Until now it has been state of the art to deal with electrical–thermal effects. The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development. But technology challenges impede the realization of the beneficial wide bandgap high temperature electronics, including material growth, contacts, and packaging [13]. SOI approach decreases the leakage area of the junction, which should have enable SOI LDMOS operate in higher temperature. However, the silicon dioxide has a very low thermal conductivity (1.4 W/mK) compared to silicon (148 W/mK) and acts as a barrier to heat diffusion in the device, which deteriorates the self-heat effects. Partial SOI device is suggested to overcome some of the inherent deficiencies of bulk Si and full SOI LDMOS [25,26]. Power Copper technology (optional thick copper metal on the top of the power device) is introduced to enhance the device performance. The thick copper is designed to absorb the thermal energy and increase the time to snapback in transient operation [27]. Another way to solve the problem is to decrease power density by using more area which is the problem demonstrated by Fig. 1.
3. Long-term SOA 3.1. Hot-carrier effect As the electric field increases, electrons and holes traveling in the channel and drift region may gain kinetic energy high enough to be injected to silicon dioxide and cause permanent changes in the silicon dioxide interface charge distribution. This defines the well-known hot-carrier effects, which is one of the major failure mechanisms affecting long-term reliability. In the case of LDMOS applied with high voltage to the gate and drain, hot-carriers impose severe limitations to long-term SOA (LT SOA). Hot-carrier effects induce the degradation Vt, Rdson, Isat, and even the gate breakdown. It is put forward that the gate breaks down when the charge injected to the oxide reaches a critical trap density in [28]. The life time determined by the hot-carrier effects is described by the empirical function [29]: V0 V1 t Z t0 exp C (10) VG Vd KV2 Setting t equal to the target life-time of the designed device and solving for Vd as a function of VG defines a curve in the (VG, Vd) plane which is the boundary of the hot electron limited safe operating area (seen in Fig. 16). LT SOA has nothing to do with the short term SOA limited by electrical and thermal effects. The LT SOA is just an additional restriction to overall SOA of the device. A method of improving SOA by using two peaks of the body current was proposed in [30] (seen in Fig. 17). By
Fig. 16. Hot-carrier determined SOA.
optimizing the doping concentration of channel and drift region, the two peaks of body current can be reduced. The numbers in Fig. 17 corresponds to the ones in Fig. 16. Increasing LDMOS layout spacing [31], adding p-field under the edge of the gate plate [32] can also improve LTSOA. As a matter of fact, hot-carrier effects are induced by high electric field. Consequently, any action devoted to reduce the peak/plateau of the electric field in the channel and the drift region can improve the ruggedness of LDMOS and increase the corresponding LT-SOA. By analyzing, the electric field profile along the Si/SiO2 interface, submicron LDMOS hot-carrier effects are studied in detail in [33]. Guidelines to suppress the hot-carrier effects involving the two lightly doped regions of the device not overlapped by the gate electrode are provided.
4. Discussion and conclusion Changing the gate voltage of Fig. 17 to drain current and together with Fig. 2, an overall SOA is displayed in Fig. 18. The safe operation area is defined by the inner boundary of the three curves. Each of the three SOAs is related to electric field. Consequently, reducing electric field moves the three SOA curves toward right. In [34], the electric field along the Si surface of LDMOS was analyzed in detail. In the design of LDMOS, every peak electric field should be reduced in order that the electric field profile inclines to flat. Increasing the device area reduces the current density, not only dose the Kirk effect is alleviated, but the thermal dissipation per area is reduced. Accordingly, the three curves move right when
Fig. 17. Body current measured at drain voltage at each step.
Z. Sun et al. / Microelectronics Journal 37 (2006) 661–667
Fig. 18. The overall SOA of LDMOS.
the device area increases. With the increase of ambient temperature, the impact ionization decreases. At the same time, thermal effect and hot-carrier effects are aggravated. Therefore, with the temperature increase, the electrical SOA curve moves toward left while the thermal SOA and LT SOA curve move toward right. In the case of LT SOA, longer lifetime determines decreased SOA. To date, it is the state of the art to improve SOA in the designing of LDMOS. We can expect to see and learn about new structures and other features that will achieve SOA improvement consistent with demands on the device performance as time progresses.
References [1] Philip L.Hower, Safe Operating Area-a New Frontier in LDMOS Design, ISPSD’02 p1-8. [2] A. Ludikhuize, Kirk effect limitations in HV IC’s, ISPSD 1994 p.249-252. [3] IK-Seok Yang, Yun-Hak Koh, Jae-Hoon, et al., An Improvement of SOA on n-channel SOI LDMOS Transistors, ISPSD’98, p.379-382. [4] Jongdae Kim, Tae Moon Toh, Sang-Gi Kim et al., High Voltage Power Integrated Circuit Technology Using SOI for Driving Plasma Display Panels, IEEE Transactions on Electron Devices, Vol. 48, No.6, 2001, p.1256-1263. [5] Kenya Kobayashi, Hiroshi Yanagigawa, KKazuhisa Mori, et al., High Voltage SOI CMOS IC Technology for Driving Plasma Display Panels, ISPSD’99 p. 141-144. [6] K. Kinoshita et al., New RESURF concept for 20V LDMOS without BV degradation, ISPSD1998, p.81-84. [7] Zhang Shengdong, Han Ruqi, Tommy Lai, et al., Development of High Voltage Thin Film SOI Device with Linearly Doped Drift Region, ACTA Electronic SINICAT, Vol. 29, No.2, 2001, p.164-167. [8] Vijay Parthasarathy, Vishnu Khemka, Ronghua Zhu, et al., SOA Improvement by a Double RESURF LDMOS Techniue in a Power IC Technology, IEDM 00, p.75-77. [9] P.L. Hower, J. Lin, and Steve Merchant, Snapback and Safe Operating Area of LDMOS Transistors, IEDM99, p.193-196. [10] Andy Strachan, Doug Brisbin, Optimization of LDMOS Array Design for SOA and Hot Carrier Lifetime, ISPSD’03, p.84-87. [11] Masakatsu Hoshi, Teruyoshi Mihara, Tsutomu Matsushita, et al., A KMOSFET Having A Cell Array Field Ring fro Improving Avalanche Capability, ISPSD’93, p141-145.
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[12] Masakatu Hoshi, Teruyoshi Mihara, Tsutomu Matsushita, et al., ADMOSFET Hanving A Cell Array Field Ring for Improving Avalanche Capability, ISPSD’93, p.141-145. [13] PHILIP G.NEUDECK, ROBERT S.OKOJIE, LIANG-YU, High Temperature Electronics-A Role for Wide Bandgap Semiconductor? Proceedings of the IEEE, Vol. 90, No. 6, 2002: p.1065-1076. [14] R.F.Pierret, Advanced Semiconductor Fundamentals. Reading, MA: Addison -Wesley, 1987, Vol. 6, Ch. 5, p.91-134. [15] S. Clemente, Transient thermal response of power semiconductors to short pweor pulses, IEEE Trans. Power Electronics 8 (4) (1993) 337–341. [16] S. Merchant R. Baird, P. Bennett et al., Energy Capability of Lateral and Vertical DMOS Transistors in an Advanced Automotive Smart Power Technology, ISPSD’98, p.317-320. [17] G.W. Neudeck, The PN Junction Diode, Modular Series on Solid State Devices 2 (1989) 2. [18] E.H. Rhoderick and R.H. Williams, Metal-Semiconductor Contacts. Oxford, U. K.:Clarendon, 1998. [19] S.M. Sze Physics of Semiconductor Devices, 2nd ed. New York: Wiley 1981. [20] Yang S.Chung, Ofelia Valenzuela and Bob Baird, Mechanism of Power Dissipation Capability of Power MOSFET Devices: Comparative Study between LDMOS and VDMOS Transistors, ISPSD’01, p.275-278. [21] A. Raman, D.G. Walker, T.S. Fisher, Simulation of nonequilibrium thermal effects in power LDMOS transistors, Solid-State Electronics 47 (2003) 1256–1273. [22] H.T. Lim, F. Udea, K.M. Garner, Modelling of self-heating effect in thin SOI and Partianl SOI LDMOS power device, Solid-State Electronics 43 (1999) 1267–1280. [23] S. Young, Chung and Bob Baird, Power capability limits of power MOSFET devices, Microelectronics Reliability 42 (2002) 211–218. [24] Young S. Chung and Bob Baird, Electrical Thermal Coupling Mechanism on Operating Limit of LDMOS Transistor, IEDM 00-83. [25] Udrea F, Milne W, Popescu A, Lateral insulated gate bipolar transistor (LIGBT) structure based on partial isolation SOI technology, Electronics Letters 1997, 33 (10), p.907-909. [26] Udrea F, Milne W, Popescu A, Breakdown analysis in JI, SOI and Partial SOI power structures. Proceeding of IEEE International SOI Conference, 1997, p.102-103. [27] V. Dwyer, A. Franklin, D. Campbell, Thermal failure in semiconductor device, Solid State Electron 33 (1990) 553–560. [28] R. Degraeve, G. Groeseneken, R. Bellens, J.L. Ogier, et al. IEEE Trans, Electron Dev., 45, 904(98). [29] S. Manzimi and C. Contiero, Hot Electron Induced Degradation in High Voltage Submicron DMOS Transistors, ISPSD ’96 May 1996, p.65-68. [30] S.K. Lee, C.J. Kim, Y.C. Choi, et el., Optimization of Safe-Operating -Area Using Two Peaks of Body-Current in Submicron LDMOS Transistors, ISPSD’01 p.287-290. [31] Douglas Brisbin, Andy Strachan, Prasad Chaparala, et al., Hot Carrier Reliability of N-LDMOS Transistor Arrays for Power BiCMOS Applications, IRPS’02, p.105-110. [32] S. Manzimi and C. Contiero, Hot Electron Induced Degradation in High Voltage Submicron DMOS Transistors, ISPSD ’96 May 1996, p.65-68. [33] Roberto Versari and Augusto Pieracci, Experimental Study of HotCarrier Effects in LDMOS Transistors, IEEE Transactions on Electron Devices, Vol. 46, No 6, 1999. p.1228-1233. [34] Sang-Koo Chung and Seung-Youp Han, Analytical Model for the Surface Field Distribution of SOI RESURF Devices, IEEE Transactions on Electron Devices, Vol. 45, No. 6, 1998, p.1374-1376.
A review of safe operation area Zhilin Sun, Weifeng Sun*, Longxing Shi National ASIC System Engineering Research Center, Southeast University, Jiangsu, Nanjing 210096, China Received 30 May 2005; received in revised form 24 July 2005; accepted 26 July 2005 Available online 12 September 2005
Abstract For designing LDMOS, SOA is an important and complex parameter which is defined by current, voltage, waveform, pulse time, etc. In this paper, short-term and long-term factors that determine the SOA boundary are demonstrated. Methods to improve SOA are enumerated. q 2005 Elsevier Ltd. All rights reserved.
1. Introduction With the feature size reducing, power devices benefit a lot from decreasing device area. But they are not on the same evolutionary curve as logic or mixed-signal. This is mainly because of breakdown voltage and power density limits, as dictated by device physics, demanding a nearly constant minimum device size. This means that only the modest area decrease can be made as line widths and contact dimensions are made smaller, which makes the power devices dominate in the whole chip area. To reduce the cost and save the chip area, it is a paramount for the power device designer to have a thorough understanding of what is needed to meet the applications, which are the main limitation factors of reducing the power device area. As the most important member of power device, lateral double-diffused MOS (LDMOS) has been widely used in many power electronic applications, such as power converters, motor controllers, and automotive electronics, due to not only their high switching speed, high input impedance and good thermal stability, but the compatibility for integration into a modern BiCMOS technologies. Traditionally, the tradeoff between breakdown voltage (BVdss) and on-resistance (Rdson) is familiar and frequently used to choose the LDMOS area, using RdsonZ Rsp/A, where Rsp is the specific on-resistance and A is * Corresponding author. Tel.: C86 25 379 5811x8401; fax: C86 25 335 2764. E-mail address: [email protected] (W. Sun).
0026-2692/$ - see front matter q 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2005.07.006
the device area (The top of the triangle in Fig. 1). However, the area achieved by this approach may or may not meet SOA requirements. Then another criterion must be added to the traditional tradeoff design of LDMOS forming Fig. 1 [1], the LDMOS design triangle. In traditional designs, increasing BVdss can improve SOA and increase Rdson simultaneously. This is shown by the aiding arrow on the left and the conflicting arrow on the right. Adding a region, whose impurity concentration is higher than the drift region while lighter than the drain region, between the drift and the drain, a more rectangular SOA and a reduced Rdson can be achieved, which is represented by the conflicting arrow on the left side and the aiding arrow on the right side. The term ‘Safe Operation Area’ is used to describe the region in the IdKVds plane through which the device can switch without suffering damage. Fig. 2 shows a sketch of an Id vs. Vds curve for fixed Vgs. As the operating point approaches the SOA boundary, the slope of the curve increases and eventually becomes infinite at the boundary. Beyond this ‘snapback’ point, the device exhibits negative resistance and fulmination occurs, usually with accompanying damage to the device. The determination of SOA is not a simple matter. Current, voltage, waveform, stress time, and temperature are all involved in defining the SOA. Furthermore, the usual reliance on experimental data as a design check is complicated by the fact that measurements are nearly always destructive. Fig. 1 represents a much larger set of modeling, simulation, and measurement complexity than do BVdss or Rdson. In this paper, all kinds of factors limiting the SOA are enumerated. The methods for solving all these problems are demonstrated.
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Fig. 1. LDMOS design triangle showing tradeoffs that affect device area.
2. Short-term SOA 2.1. Electrical effect 2.1.1. Kerk effect At high current density, the moving carriers influence the depleted charge, which result in higher electric field near n/nC junction. This is called Kirk Effect. Fig. 3 [2] demonstrates this phenomenon. In the on-state, significant amount of negative charge adds to the positive space charge of the n-type drift region. It leads to a shift of the potential lines towards the drain. For application, the effect means the use of a longer drift region or less current per gate width. Several methods have been proposed to alleviate Kirk effect. Adding an n buffer region, whose concentration is higher than the drift region while lighter than the drain region, has been well-know [3–6]. A much more effective method, linearly doped drift region, is put forward in [7]. The graded dopant with the increasing concentration toward the drain makes the electric field uniform in the drift region. The graded doped drift is implemented by implanting only one time. The mask and the impurity concentration after diffusion is show in Fig. 4. In [8], a Double RESURF technology (Seen in Fig. 5) was put forward to improve SOA. An nC buried layer, which is externally tied to the drain terminal, is added to the conventional LDMOS, which is used to share the carrier in the on-state. Consequently, with about 60% decrease of the current density, Kirk effect is alleviated.
Fig. 3. Shift of potential lines by Kirk effect at 250 V in 500 V-LDMOS. (a) low Ids (b) high Ids.
Fig. 4. Demostration of achieving linearly graded doped drift region.
develops across the body–source junction. The forward bias is due to Ib supplied by the carrier generation mechanisms indicated in Fig. 6. And Ib can be written as: Ib Z ðMn K1Þ !Is C Idiff C Igen
(1)
Where Is is the on-state drain current, Idiff is the reverse leakage current and Igen is the generation current. (MnK1)Is
2.1.2. Intrinsic parasitic triode In all MOS transistors, there is a parasitic triode that can be turned on when a sufficient ‘base-emitter’ voltage
Fig. 2. Schematic of the SOA boundary. The SOA boundary is defined by the onset of negative resistance at Id vs. Vds curve.
Fig. 5. Schematic cross-section and current flowline of (a) single RESURF LDMOS with substrate grounded and (b) double RESURF with NBL externally tied to drain terminal.
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Fig. 6. Circuit model of LDMOS showing the intrisic triode.
is the current due to impact ionization. It arises from channel primary current Is producing secondary carriers in the drift region, which then drift backward to the source. Mn depends on electric field. Three peak electric fields along Si/SiO2 interface (Seen in Fig. 7) determine the magnitude of Mn. The leftmost peak electric field in Fig. 7 is determined by the impurity concentration of n-well. The other two peak ones are determined by the impurity concentration of drift region as is well-known. When one of the three peak values is close to critical electric field, the first term in the right hand of (1) dominates. Fig. 8 shows Vbe of parasitic triode that is sufficient to turn-on the triode. Vbe is the combination of impact ionization, channel current Is, and shunting resistor R. With the increase of Vds, three peak electric fields in Fig. 7 dominate successively. The parasitic triode turns on when one of the peak electric field reaches critical electric field and Mn is sufficient that the voltage drop in the resistor is equal to or lager than Vbe. Simultaneously, the IdsKVds curve snapbacks. Unless some protect measures are implemented, second breakdown happens and irresistible damage is done to the device. Abundant research has been done on the turning on of the parasitic triode. LDMOS with the gate extended over field oxide has an enhanced SOA [9] The raised up gate field
Fig. 7. Electric field profile along Si/SiO2 interface of LDMOS.
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Fig. 8. Substrate-source voltage or Base-emitter voltage of parasitic triode vs. Vds (supposing temperature is constant).
plate lowers the middle peak electric field in Fig. 7. Therefore, Mn is reduced and the SOA enhanced. And it is also shown that the gap between the edge of the gate and the nC drain has a significant effect on SOA. One effective way to improve SOA is to reduce Rb. Moving the heavily doped ohm contact closer to the poly gate will of course reduce Rb. But this extreme case will restrict channel current and increase Rdson. In [10], a simple layout improvement is proposed. By alternating sources and drains, checkerboarddesigned arrays are put forward (Seen in Fig. 9). The X-shaped pC contact can overlap the gate in the corners minimizing any increase in Rdson. For snapback is usually irresistible, measures are necessary to implement to protect the device. A selfprotection DMOS is proposed in [11], which can be seen in Fig. 10. With the additional pC body diffusion, Zener diode is formed at the bottom of the p-type body region. Firstly, the heavily doped pC region lowers the base resistance of Rb. Secondly, the breakdown voltage is controlled by the Zener diode independent of other DMOS characteristics. Consequently, when high voltage is applied to the device, breakdown occurs only at the bottom of p-body region. Avalanche current flows through the low resistivity pC body region, not passing through the high resistivity rim of the p-body region, which protect the device from second breakdown. In [12], a self-protect device is improved by adding a field ring, which enhanced the avalanche capability.
Fig. 9. Layout of checkerboard sources and drains for a conventional pC contanct (left) and X shaped pC contact (right). The X-shaped pC array has improved SOA due to reduced body resistance Rb, while minimizing lost gate width.
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the source. The temperature at which the device shown in Fig. 7 fails must be reached about 725 K [16]. With the increase of the intrinsic carrier concentration, leakage current of a reverse-biased p–n junction increases dramatically. At a reverse-bias greater than a few tenths of a volt and temperature below 1000 K, the I–V character of a p–n diode is approximated by [17]: " rffiffiffiffiffiffi # Dp W ni (3) Idiff ZKQAni C 2t ND t
Fig. 10. Cross-section views of the rugged DMOS.
2.2. Electrical–thermal effect 2.2.1. Thermal effect With temperature increase, a number of factors inside and outside the semiconductor limit the operation of the electronic devices and circuits [13]. Every semiconductor has a certain number of thermal electron and hole carriers presented in the crystal. The concentration of these intrinsic carriers is exponentially dependent upon the temperature of the semiconductor [14]: pffiffiffiffiffiffiffiffiffiffiffi ni Z Nc Nv eKEG =2KT (2)
Together with (2), we get that the reverse-biased junction leakage current harmful to devices and circuits operation increases exponentially with temperature. Another fundamental leakage mechanism in devices is the transport carriers that gain sufficient energy to go over or tunnel through an energy barrier in a device structure. The current due to carrier emission as a function of temperature and applied voltage is approximated by [18] Igen ZKAK T 2 eKqfB =KT
(4)
where fB is the potential barrier height of the junction and K* is the effective Richardson constant of the semiconductor. This process called emission, increases with temperature as carriers gain more thermal energy.
where T is the temperature (in Kelvin), K is the Boltzmann constant, EG is the energy bandgap of the semiconductor measured in electronvolts, and Nc and Nv are the effective electron and hole density of states, respectively. The temperature dependence of the intrinsic carrier concentration calculated from (2) is shown in Fig. 11. Some authors [15] associate the fail of the semiconductor device with the intrinsic temperature of the substrate, which is defined by solving ni(T)ZNsub. For NsubZ5!1015 cmK3, this gives TfailZ603 K. In fact, if it comes to the device shown in Fig. 7, it is not until the intrinsic concentration exceeds the n-well concentration that the drain punches through
2.2.2. Electrical–thermal coupling The circuit model is much more complex when the thermal effect is concerned. Fig. 12 follows a similar format to Fig. 6, but in a much more accurate way concerning the thermal effect. As is shown in Fig. 12, the solid black lines represent the normal operation path. The gray dashed lines are added when the device temperature is high. As temperature is increased well above room temperature, there are three distinct differences between Figs. 6 and 12. Firstly, the ability of carriers to move through a semiconductor crystal decreases. This arises because atoms in the crystal lattice have more thermal vibrational energy that results in more collisions with carriers moving through the crystal in response to an electric field. The increase in semiconductor device resistance with
Fig. 11. Semiconductor intrinsic carrier concentration versus temperature.
Fig. 12. Circuit model of LDMOS including electrical–thermal effect.
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temperature follows the formulation: R Z R0 ð1 C T x Þ
(5)
where R0 is the value of semiconductor device resistance R in room temperature and x is usually between 1.5 and 2.5 for most semiconductor [19]. Consequently, Rb, Rs and Rd in Fig. 12 increase with the temperature increase in the following formula: Rb Z Rb0 ð1 C T x Þ
(6)
Rs Z Rs0 ð1 C T x Þ
(7)
x
Rd Z Rd0 ð1 C T Þ
(8)
Secondly, the last tow terms on the right hand of (1) will dominate gradually at high temperature described by (3), (4). Lastly, base-emitter voltage needed to turn on the parasitic triode has a negative temperature coefficient in the range of 1.6–2 mV/K as the following formula kT Jc Vbe Z ln (9) q JsðTÞ where Jc is the collector current density, which is presumed fixed, Js is the saturation current density. The snapback voltage, at which the parasitic diode turns on, is difficult to be predicted due to all these thermal effects. A rough tendency is demonstrated in Fig. 13. On the left of the peak vale, the first term on the right hand of (1) dominates. With the increase of temperature, Rs and Rd decrease inducing current decrease even if the drain voltage increases [20]. The impact ionization current is decreased due to the lowered source to drain current and the decreased mean free path. Accordingly, the snapback voltage increases. On the right side of the peak vale, the last two terms on the right hand of (1) dominate. Therefore, the snapback voltage decreases with the increase of temperature. At about 800 K got by solving (9)Z0, the device can no longer work. 2.2.3. Self-heating In the nonisothermal consideration of LDMOS, selfheating is essential to understand the operation limit of LDMOS. Self-heating refers to the condition when charge carriers are not able to transfer their excess energy to the lattice efficiently [21]. A temperature difference is created between electrons and the lattice resulting in localized
Fig. 13. Snapback voltage of LDMOS versus ambient temperature. Presuming the device is isothermal.
Fig. 14. Substrate-source or Base-emitter voltage vs. temperature of the parasitic triode.
heating in the active area of the device. The localized heating is maximum, where electric field is maximum. When a voltage lower than the breakdown voltage is applied to the drain, the second peak electric field in Fig. 7(b) is the maximum one. Hot spot locates in the nwell–drift junction (Seen in Fig. 7(a)). Compared to this hot spot, temperature rise in other area of the device is neglectable [22] In this case, Idiff, Igen and Rb increase dramatically for the hot spot is near the p–n junction and the channel, whereas the change of Rd (Fig. 12) is neglectable. Combining (3), (4), (6) and (9), Fig. 14 is got to show qualitatively how the parasitic triode turns on in response to an increasing temperature of self-heating. The two lower curves (the solid, where Mn is one and dashed curve, where there is significant impact ionization) represent the voltage drop in the base resistor of the parasitic triode due to Ih. The device fails at Tcrit, where the Vbe and IhRb curves across (Fig. 14). Fig. 15 [23,24] shows the transient behavior with the change of the input power at an ambient temperature of 300 K. At higher starting current, the rate of the temperature rise is much larger and eventually, the parasitic triode turns on and the device fails, whereas the device with lower starting current reaches the steady state. Consequently, SOA of LDMOS will decrease dramatically because of selfheating.
Fig. 15. Transient eletrothermal simulation with different starting current levels for a given ambient temperature.
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Until now it has been state of the art to deal with electrical–thermal effects. The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development. But technology challenges impede the realization of the beneficial wide bandgap high temperature electronics, including material growth, contacts, and packaging [13]. SOI approach decreases the leakage area of the junction, which should have enable SOI LDMOS operate in higher temperature. However, the silicon dioxide has a very low thermal conductivity (1.4 W/mK) compared to silicon (148 W/mK) and acts as a barrier to heat diffusion in the device, which deteriorates the self-heat effects. Partial SOI device is suggested to overcome some of the inherent deficiencies of bulk Si and full SOI LDMOS [25,26]. Power Copper technology (optional thick copper metal on the top of the power device) is introduced to enhance the device performance. The thick copper is designed to absorb the thermal energy and increase the time to snapback in transient operation [27]. Another way to solve the problem is to decrease power density by using more area which is the problem demonstrated by Fig. 1.
3. Long-term SOA 3.1. Hot-carrier effect As the electric field increases, electrons and holes traveling in the channel and drift region may gain kinetic energy high enough to be injected to silicon dioxide and cause permanent changes in the silicon dioxide interface charge distribution. This defines the well-known hot-carrier effects, which is one of the major failure mechanisms affecting long-term reliability. In the case of LDMOS applied with high voltage to the gate and drain, hot-carriers impose severe limitations to long-term SOA (LT SOA). Hot-carrier effects induce the degradation Vt, Rdson, Isat, and even the gate breakdown. It is put forward that the gate breaks down when the charge injected to the oxide reaches a critical trap density in [28]. The life time determined by the hot-carrier effects is described by the empirical function [29]: V0 V1 t Z t0 exp C (10) VG Vd KV2 Setting t equal to the target life-time of the designed device and solving for Vd as a function of VG defines a curve in the (VG, Vd) plane which is the boundary of the hot electron limited safe operating area (seen in Fig. 16). LT SOA has nothing to do with the short term SOA limited by electrical and thermal effects. The LT SOA is just an additional restriction to overall SOA of the device. A method of improving SOA by using two peaks of the body current was proposed in [30] (seen in Fig. 17). By
Fig. 16. Hot-carrier determined SOA.
optimizing the doping concentration of channel and drift region, the two peaks of body current can be reduced. The numbers in Fig. 17 corresponds to the ones in Fig. 16. Increasing LDMOS layout spacing [31], adding p-field under the edge of the gate plate [32] can also improve LTSOA. As a matter of fact, hot-carrier effects are induced by high electric field. Consequently, any action devoted to reduce the peak/plateau of the electric field in the channel and the drift region can improve the ruggedness of LDMOS and increase the corresponding LT-SOA. By analyzing, the electric field profile along the Si/SiO2 interface, submicron LDMOS hot-carrier effects are studied in detail in [33]. Guidelines to suppress the hot-carrier effects involving the two lightly doped regions of the device not overlapped by the gate electrode are provided.
4. Discussion and conclusion Changing the gate voltage of Fig. 17 to drain current and together with Fig. 2, an overall SOA is displayed in Fig. 18. The safe operation area is defined by the inner boundary of the three curves. Each of the three SOAs is related to electric field. Consequently, reducing electric field moves the three SOA curves toward right. In [34], the electric field along the Si surface of LDMOS was analyzed in detail. In the design of LDMOS, every peak electric field should be reduced in order that the electric field profile inclines to flat. Increasing the device area reduces the current density, not only dose the Kirk effect is alleviated, but the thermal dissipation per area is reduced. Accordingly, the three curves move right when
Fig. 17. Body current measured at drain voltage at each step.
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Fig. 18. The overall SOA of LDMOS.
the device area increases. With the increase of ambient temperature, the impact ionization decreases. At the same time, thermal effect and hot-carrier effects are aggravated. Therefore, with the temperature increase, the electrical SOA curve moves toward left while the thermal SOA and LT SOA curve move toward right. In the case of LT SOA, longer lifetime determines decreased SOA. To date, it is the state of the art to improve SOA in the designing of LDMOS. We can expect to see and learn about new structures and other features that will achieve SOA improvement consistent with demands on the device performance as time progresses.
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