A study of analog decision feedback equalization for ADC-Based serial link receivers

Integration, the VLSI Journal xxx (2018) 1–13

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Integration, the VLSI Journal journal homepage: www.elsevier.com/locate/vlsi

A study of analog decision feedback equalization for ADC-Based serial link receivers Azad Mahmoudi, Pooya Torkzadeh *, Massoud Dousti Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

A R T I C L E I N F O

A B S T R A C T

Keywords: Analog-to-digital converter Analog decision feedback equalization Bit-error-rate Flash ADC Serial link receiver

High-speed serial link receivers based on analog-to-digital converters (ADCs) provide better programmability with different channel characteristics and the possibility of employing powerful signal equalization techniques in the digital domain. However, complexity and power consumption are still major issues in adopting such receivers in high-speed applications when compared to traditional binary or mixed-signal approaches. Embedded decision feedback equalization (DFE) before ADC quantization can relax the design requirements of both the ADC and postADC digital processing. This paper studies the impact of embedded analog DFE on voltage margin improvement of an ADC-based receiver through worst-case analysis. An analytical expression for the link bit-error-rate (BER) with analog DFE is derived and validated through simulations. An empirical study is conducted that evaluates the achievable BER of embedded analog DFE as a function of the channel inter-symbol interference (ISI) and ADC resolution. A channel-dependent parameter is introduced and employed to quantify the BER improvement achieved by embedding analog DFE in a receiver. A prototype receiver with embedded DFE is designed and laid out in a 130 nm CMOS process and achieves 4.64-bits peak ENOB and 4.08 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. The BER performance of the receiver over high-loss FR4 channels at 1.6 Gb/s is evaluated and used to validate the simulation results.

1. Introduction With the aggressive scaling of CMOS technology, incorporating analog-to-digital converters (ADCs) as the front-end stage of high-speed serial link receivers has attracted growing interest as it allows the possibility of implementing advanced signal processing algorithms in the digital domain and adopting advanced modulation formats beyond binary PAM2 [1–4]. Despite the advantages of an ADC-based receiver, power consumption imposes a limit in its application when competing with conventional binary receivers [5–8]. Fig. 1 shows the structure of a conventional ADC-based serial link receiver. The transmitted data pattern after passing through the channel is received by a switched-capacitor network and then is converted into digital form by the ADC. The digital signal processor (DSP) computes and subtracts the appropriate amount of offset from the ADC output based on the prior symbol decisions and uses a digital slicer to retrieve the transmitted bit. Although the power dissipation in such receivers is dominated by the ADC, the DSP block can also have a considerable energy consumption even comparable to the ADC [7,8].

Analog equalization before ADC quantization, as subtraction of an offset voltage from the received input in the analog domain, can partially remove post-cursor inter-symbol interference (ISI) components and results in both a low-complexity DSP and a lower ADC resolution requirement, leading to a lower overall power consumption for the receiver [9,10]. At a target BER, relaxing the number of output bits of a flash ADC will exponentially save area and power consumption, while a lower resolution for a successive approximation register (SAR) ADC leads to a higher sampling rate. These two structures with resolutions in the range of 4–6 bits have emerged as the dominant choices for digital receivers [11–13]. Several power-efficient implementations of analog equalization inside high-performance ADC-based receivers have been reported in recent years [14–19]. In this work, the effectiveness of embedded analog decision feedback equalization (DFE) in performance improvement of the ADC-based receivers is evaluated in terms of BER as one of the best information-based metrics to describe the capability of the ADC in the preservation of the information content. The equivalence between subtraction of DFE tap coefficients (DTCs) from the analog input and reduction in the number of

* Corresponding author. E-mail address: [email protected] (P. Torkzadeh). https://doi.org/10.1016/j.vlsi.2018.09.003 Received 12 April 2018; Received in revised form 31 July 2018; Accepted 12 September 2018 Available online xxxx 0167-9260/© 2018 Published by Elsevier B.V.

Please cite this article in press as: A. Mahmoudi, et al., A study of analog decision feedback equalization for ADC-Based serial link receivers, Integration, the VLSI Journal (2018), https://doi.org/10.1016/j.vlsi.2018.09.003

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Fig. 1. Block diagram of a typical ADC-based serial link receiver.

channel taps is used to derive an expression for BER of DFE receivers. Thus, it allows for estimation of the link BER with no need for expensive Monte-Carlo simulations and time consuming time-domain simulations. Moreover, since the implementation of multi-tap analog DFE could be accompanied by prohibitive overheads, the presented empirical results can be used for equalizer optimization. The rest of this paper is organized as follows. Section 2 briefly reviews the structures of ADC-based receivers with analog DFE and through worst-case analysis describes the impact of the DFE on the receiver voltage margins. In Section 3, an analytical expression for the BER performance of the receivers with embedded DFE is derived. Achievable BER improvement via analog DFE in link receivers with different channel characteristics and different ADC resolutions is discussed in Section 4. In Section 5, the design of a 1.6 GS/s, 5-bit ADC-based receiver with embedded DFE in a 130 nm CMOS process is described and both standalone ADC and link simulation results are summarized. Conclusions are drawn in Section 6.

power and area penalties at the expense of a lower sampling rate [19]. For a signaling system with memory length L from bit stream of b ¼ ½b0 ; :::; bL1 , a noise-free channel output u for a transmitted bit bn 2 f1g ð 0  n  L  1Þ over a channel with discrete-time impulse response of h ¼ ½h0 ; h1 ::::; hL1  can be expressed as:

2. ADC-based DFE receivers

u ¼ up þ hn bn þ ud þ ur

Fig. 3. Loop-unrolling DFE.

(1)

where hn is the main cursor of the channel response, up is the ISI contribution from n pre-cursor bits, ud is the ISI part from the first N postcursor bits which can be canceled by DFE, and ur is the ISI contribution from the post-cursor bits outside the DFE range. Each possible pre-cursor ISI due to interference from bits ½b0 ; ::; bn1  can be expressed as:

DFE can selectively remove the post-cursor ISI components without noise or crosstalk enhancement. Fig. 2 shows the architecture of a typical ADC-based receiver with analog embedded DFE in which an offset voltage is subtracted from the sampled signal based on the prior bit decisions. The resulting signal is then compared to threshold values to regenerate the binary data. The main issue associated with analog DFE is that the subtraction of the ISI offset from the current input should be accomplished before the arrival of the next input. Meeting such timing constraint is challenging, especially at high data rates. Loop-unrolling DFE mitigates this issue by pre-computing all possible offset values and simultaneously comparing the received input with each of the offsets [20–22]. Based on the previous detected symbol decisions, the digitized result from one of these comparisons is selected by a multiplexer as the correct decision, as illustrated in Fig. 3. Hence, in this scheme, the feedback equalizer is completely located in the digital domain, meeting the timing requirement around the loop within one-bit period becomes easier. The main problem with this approach is the exponential increase in the number of comparators with the number of DFE taps. Note that the speculative comparisons of loop-unrolling DFE can be realized through several sequential cycles, thus avoiding the

up;i ¼

n1 X

ð  1Þinl :hl

i ¼ 0; ::::; 2n  1

(2)

l¼0

where inl is the ðn  lÞth bit of the n  bit binary representation of i. Similarly, post-cursor ISI levels, which represent the influence of the two bit subsequences ½bnþ1 ; ::; bnþN  and ½bnþNþ1 ; ::; bL1 , are obtained as follows: ud;j ¼

nþN X

ð  1ÞjNþnþ1l ⋅ hl

j ¼ 0; ::::; 2N  1

(3)

l¼nþ1 L1 X

ur;k ¼

ð  1ÞkLl ⋅ hl

k ¼ 0; ::::; 2LðnþNþ1Þ  1

(4)

l¼nþNþ1

where the subscripts N þ n þ 1  l and L  l respectively denote the corresponding bit in N  bit and L  ðn þ N þ 1Þ  bit binary representations of j and k. With these definitions, the elements of the sets ud ¼ fud;j g2j¼01 and ur ¼ fur;k g2k¼0 N

LðnþNþ1Þ 1

are sorted in ascending order of j and

k, respectively. The elements are also constrained to appear in symmetric pairs such that ud;j ¼ ud;2N 1j and ur;k ¼  ur;2LðnþNþ1Þ 1k . The ISI contribution from the adjacent bits ½bnþ1 ; ::; bnþN  , represented by elements of the set ud , can be removed by an N  tap DFE. In order to predict the worst-case eye diagram through pulse response the peak distortion analysis is used. Accordingly, the worst-case logic-“1” (logic-“0”) is the summation of a bn ¼ 1 ðbn ¼ 1Þ with all the negative (positive) ISI components. The difference between these two critical channel outputs is the worst-case eye height ew and can be expressed as: Fig. 2. An ADC-based receiver with analog embedded DFE. 2

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  ew ¼ uw;1  uw;0 ¼ 2 hn þ up;0 þ ud;0 þ ur;0   ¼ 2 hn  up;2n 1  ud;2N 1  ur;2LðnþNþ1Þ 1

(5)

where uw;1 ¼ hn þ up;0 þ ud;0 þ ur;0 and uw;0 ¼ hn þ up;2n 1 þ ud;2N 1 þ ur;2LðnþNþ1Þ 1 are the worst-case “1” and “0”, respectively. The eye height opening improvement via employing N  tap DFE is obtained through 2 1 elimination of all the elements of the set ud ¼ fud;j gj¼0 including ud;0 N

and ud;2N 1 , and is given by:   Δew;N ¼ ud;2N 1  ud;0 ¼ 2ud;2N 1 ¼ 2ud;0 

(6)

A simulation setup with a loop-unrolled DFE receiver was used in order to further illustrate the impact of the DFE on the eye height opening. The receiver was simulated with 106 test samples transmitted over a 1300 -long Nelco backplane channel [23] whose frequency response and simulated single-bit response at 10 Gb/s are shown in Fig. 4(a) and (b), respectively. The channel has 22.3 dB loss at the Nyquist frequency. Fig. 5 shows simulated eye diagrams at the input of the receiver without any equalization and with 3-tap DFE. From equations (2)–(6) and channel response h ¼ ½300; 106; 39; 22; 12; 8; 6  103 with n ¼ 0, the ISI levels and improvement in eye height with embedded DFE are obtained as follows, respectively:ud ¼ f  167; 123; 89; 45g  103 ,ur ¼ f  26; 14; 10; 2g 103 , up ¼ f0g, Δew ¼ 2ud;2N 1 ¼   2ud;0  ¼ 0:33 V. It can be seen in Fig. 5(b) that the improvement in the eye opening at the input of critical comparator which bit decision is made based on the result from its comparison, fairly matches the estimated value of 0.33 V. Fig. 6(c) compares the simulated and estimated eye height openings for three backplane channels [23] at different number of DFE taps. The channels are analyzed for 10 Gb/s operation with 107 samples and have a range of 19 dB–28 dB loss at the 5 GHz. The magnitude and 10-Gb/s pulse responses of the channels are shown in Fig. 6(a) and (b), respectively. The presented results assume 1-V transmit swing, 2-mVrms receiver input-referred thermal noise, and receiver sampling jitter with a 0.02 unit interval (UI) deterministic component (DJ) in the form of duty cycle distortion and a 0.02 UIrms random component (RJ). As can be seen in Fig. 6(c), increase in eye opening with increasing N, tends to be fixed as amplitudes of the channel responses are decreasing.

Fig. 5. Impact of DFE on eye height opening. (a) Simulated eye diagram with no equalization at 10 Gb/s over the 13-inch backplane. (b) Simulated eye diagram with 3-tap DFE.

signal in order to retrieve the transmitted data reliably. Using BER as one of the information-based metrics to quantify the performance of a serial link may relax some ADC requirements [24,25]. In this section, an explicit analytical expression for the BER of a conventional uniform ADC with analog DFE is derived that enables designers to decide on the degree of the DFE by creating a compromise between implementation costs and required BER level. Subtraction of an offset value from the sampled input and comparing the resultant signal with a uniform threshold level is equivalent to comparing the input with the sum of the offset and the uniform level as a

3. Achievable BER of an ADC-Based receiver with analog DFE Design of an ADC-based receiver based on signal fidelity metrics such as signal-to-noise-and-distortion-ratio (SNDR) or effective-number-ofbits (ENOB) imposes unduly resolution requirement on the ADC as they ignore the role of the ADC in preserving the data content of the input

Fig. 4. (a) Magnitude and (b) simulated 10-Gb/s single-bit responses of a 13-inch Nelco channel. 3

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BERu ¼

2M X

(7)

BERu;k

k¼1

Assuming that the elements of noise-free channel output set u are divided into two ordered subsets of uþ and u such that u ¼ f uþ [ u g and conditioned on the transmitted bit bn taking the value þ1 and  1, respectively. However, for each interval Iu;k ¼ ½tu;k1 ; tu;k  there is a critical R noise-free output uk 2 uþ ðuk 2 u Þ that maximizes Nðxc ; uk ; σ n Þdx if the Iu;k

decision for the interval is 1 ðþ1Þ where pffiffiffiffiffiffiffiffiffiffi Nðxc ; uk ; σ n Þ ¼ ð1= 2πσ n Þ  expððxc  uk Þ2 =2σ 2n Þ and σ n denotes the standard deviation of additive white Gaussian noise at the receiver's input. Thus the probability of wrong detection of an ADC output representation level for the interval Iu;k can be well approximated as follows [26]: slicer's

BERu;k 

  1 du;k Q L 2 σn

(8)

where Qð⋅Þ is the right tail probability of the standard normal distribution and du;k ¼ minðtu;k1  uk ; uk  tu;k Þ is the minimum distance of uk from the boundaries of the kth interval Iu;k . Substituting (8) into (7) yields: BERu 

  2M X 1 d u;k Q 2L σn k¼1

(9)

At high signal-to-noise-ratio (SNR) conditions which correspond to du;k ≫ σ n , the exponential approximation for the Q-function ðQðxÞ  pffiffiffiffiffiffi ð1=x 2π Þ expð  x2 =2Þ; for x > 0Þ, the relationship QðxÞ ¼ 1  QðxÞ P for x < 0, and the approximation of eðxk Þ  eminðxk Þ can be applied to k

obtain an approximation of the BERu as follows: 8 > > > > > d 2 ! > > σn 12 u;min > σn > 2L pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi e ; > > > 2π du;min > > < BERu  2ðLþ1Þ ; > > > > du;min 2 ! > 1 > σn L > > pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffie2 σn 2 1 þ ; > > > 2π du;min > > > :

if du;min > 0 if du;min ¼ 0

(10)

if du;min < 0

2M 1

where du;min ¼ minfdu;k gk¼1 is the minimum distance for a uniform ADC. By subtraction of offset values equal to the elements of the set ud from the channel outputs, an N  tap DFE reduces the number of elements of the set u to 2LN and changes the critical noise-free outputs of the intervals Iu;k . In fact, an L  tapchannel after applying N  tap DFE is converted to an ðL  NÞ  tapone. Therefore, BER for an M  bit ADC withN  tap DFE at high SNR conditions is given by:

Fig. 6. Improvement in eye height for different DFE tap numbers. (a) Frequency and (b) simulated 10-Gb/s single-bit responses of three different backplane channels. (c) Comparison between ew from simulation ðewðsim:Þ Þ and estimated ew using (6) ðewð6Þ Þ versus N.

BERu;N 

non-uniform quantization level. Therefore, an ADC-based receiver with analog DFE could be considered as an ADC with non-uniform quantization levels. Alternatively, such a receiver could be viewed as a uniform ADC in which the contribution of some post-cursor ISI elements is removed from the channel outputs. The latter point of view opens the possibility of deriving an equation for the BER estimation in a method similar to that used for a conventional uniform ADC. BER for an M  bitconventional uniform ADC with thresholds tu ¼ ½tu;1 ; tu;2 ; :::; tu;2M 1  is the sum of the probabilities of detecting each of ADC output representation levels incorrectly that each ADC output level is created by comparing a received input with all the threshold levels and each input xc is an element of the set u distorted by noise nðtÞ (see Fig. 1). Thus, the BER can be expressed as:

  2M X 1 dd;k LN Q σn 2 k¼1

8 > > > > > d 2 ! > > σn > 12 d;min ðLNÞ > σn > pffiffiffiffiffi 2 e ; if du;min > 0 > > > 2π dd;min > > > > <  2ðLNþ1Þ ; if du;min ¼ 0 > > > > > > d 2 ! > > σ 12 d;min > σn > 2ðLNÞ 1 þ pffiffiffiffiffi n e if du;min < 0 > > > 2π dd;min > > > > :

4

(11)

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where

dd;k ¼ min ðtu;k1  uk;N ;

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uk;N  tu;k Þ

and

dd;min ¼

2M 1

min ðfdd;k gk¼1 Þ have similar definitions to du;k and du;min , respectively and uk;N is the critical noise-free channel output of the kth ADC threshold belonging to the reduced-element setu  ud . It can be found from Eq. (11) that BERu;0 ¼ BERu . Fig. 7 schematically illustrates the model used to derive the BER expression. A part of the conditional probability density functions (PDFs) corresponding to the marginal PDF of the channel outputs conditioned on the transmitted bit forh ¼ ½0:08; 0:07; 0:1; 0:04 without and with on-tap DFE are shown in Fig. 8(a) and (b), respectively. Assuming a 6-bit ADC with a full-scale range of ½  0:4; þ 0:4, the corresponding du;9 u9 , dd;9 , and u9;1 are illustrated for the interval Iu;9 ¼ ½0:05;0:1. As can be seen in Fig. 8(b), DFE leads to increase in dd;9 by removing the elements of the set ud from the u  set of the channel. From Eqs. (10) and (11), the BER ratio is obtained as: BERRN ¼

BERu BERu;N

8 ! d2 d2 d;min u;min > > N dd;min 2σ 2 > n 2 > e ; if du;min > 0 > > du;min > > > > > > > > > > > < N if du;min ¼ 0  2 ; > > >   > du;min 2 > 1 σn > > > 1 þ pffiffiffiffiffi e2 σn > > 2 d π > u;min > > 2N dd;min 2 ; if du;min < 0 > > 1 σn > > p ffiffiffiffiffi 1 þ e2 σn : 2π dd;min

(12)

Eq. (12) indicates that BERRN increases with d2d;min or d2d;min  d2u;min and can be predicted for a known channel h with SNR given by SNRh ¼ PL1 2 2 i¼0 jhi j =σ v . In order to validate the derived expressions, a receiver with embedded DFE for SNRh ranging from 16 dB to 38 dB for channels h ¼ ½112; 92; 84; 51  103 and h ¼ ½215; 105; 91; 61; 32103 was simulated with 108 (for SNRh  34dB) or 1012 (for SNRh > 34dB) samples. Fig. 9 shows that the analytical expressions (11) and (10) can predict the results from Monte-Carlo simulations for BERu;0 and BERu;1 with the maximum error less than an order-of magnitude. Moreover, this error decreases with increasing SNRh as the exponential approximation for Qfunction becomes more accurate. Furthermore, Fig. 9(b) (Fig. 9(d)) indicates that a 5-bit (6-bit) uniform ADC with one-tap DFE achieves a BERR1 ¼ 40 ðBERR1 ¼ 11Þ at SNRh ¼ 30 dB. It is worth mentioning that the presented approach can be used to derive BER expression of a receiver with a different embedded analog

Fig. 8. An illustrative example of du;k , dd;k , uk and uk;N for channel h ¼ ½0:08; 0:07; 0:1; 0:04. (a) Conditional PDFs with no equalization and (b) conditional PDFs with 1-tap DFE.

equalization scheme if the modification of the channel output set through that equalization is known. 3.1. BER improvement versus channel ISI In this subsection, an empirical study is conducted to evaluate the BERRN achieved by analog DFE as a function of the channel ISI. The expression in (11) indicates that the achievable BER for an M  bit conventional uniform ADC for a given noise condition BERu;N ðM; SNRh Þ depends on the distances of the critical noise-free outputs from the borders of the ADC threshold levels, which in turn, depend on the placement sequence of elements of the uþ and the u within each of the intervals

Fig. 7. The model of the ADC-based receiver with pre-ADC DFE. 5

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Fig. 9. Comparison between BER calculated from the analytical expression and obtained from simulation. (a) BERu;0 from simulation ðBERu;0 ðsim:Þ Þ and BERu;0 estimated using (10) ðBERu;0ð10Þ Þ for channel h ¼ ½215; 105; 91; 61; 32  103 with a 5-bit ADC ðM ¼ 5Þ and (b) BERu;1 ðsim:Þ versus BERu;1ð11Þ . (c) BERu;0 ðsim:Þ and BERu;0ð10Þ for channel h ¼ ½112; 92; 84; 51  103 with a 6-bit ADC ðM ¼ 6Þ and (d) BERu;1 ðsim:Þ versus BERu;1ð11Þ .

Iu;k ðk ¼ 1; :::; 2M Þ. For a known channel with impulse response h, number of transitions mh in its u  set can be used as a metric for assessing the severity of the channel ISI where a utransition occurs when an element of the set uþ is followed by an element of the set u or vice versa [26]. For channels with large ISI, the number of these transitions is higher. In other words, presence of an element of the set uþ ðu Þ among elements of the set u ðuþ Þ leads to a smaller du;k for the interval Iu;k and hence increases the probability of a wrong decision. Fig. 10 (a) shows an illustrative example of the transitions of the u  set of channel h ¼ ½157; 93; 56; 34; 13  103 . The reduction in the number of the channel outputs as a result of embedding analog DFE leads to a lower mh , as shown in Fig. 10 (b). The DFE effectiveness metric Nw is defined as the number of required taps in order to reduce mh to 1. Consider two channels with impulse responses of h1 ¼ ½117; 65; 47; 35; 21; 12  103 and h2 ¼ ½124; 68; 43; 31; 18  103 which have almost similar SNRh s in the same noise condition but with different numbers of transitions (mh1 ¼19 and mh2 ¼ 7). Fig. 11 compares simulated BERu;N ðM; SNRh Þ for a link over the two above channels with different resolutions when SNRh ¼ 28 dB, indicating corresponding mh at each value of N. Fig. 11 shows that for channel h1 the number of required taps in order to reach the so-called “waterfall” regime of the BER is equal to 3 while this is reached by h2 at N ¼ 2. Furthermore, it can be seen in Fig. 11 that 6-bit receiver with 3-tap DFE over channel h2 achieves a BERu;3 ð6; 28Þ of 1.17  104 while the same with channel h1 is 2.24  102 and h2 has a faster BER decreasing rate over N > Nw . Finally, Fig. 11 indicates that the minimum required number of N in which links experience an exponential decay in BER is equal toNw . The obtained results verify that for a given ADC resolution, employing N  tap DFE with N < Nw may have a slight impact on BER improve-

Fig. 10. An illustrative example of mh as a metric describing the channel ISI. Noise-free channel outputs for h ¼ ½157; 93; 56; 34; 13103 (a) with no equalization and (b) with one-tap analog DFE.

ment, as well as implementation of DFEs with N > Nw taps, which is inevitably accompanied with some overheads, may reduce the BER to a level lower than the application requirement. 3.2. BER improvement versus ADC resolution In order to minimize link BERs, the SNR of the ADC should be maximized. Hence, increasing the ADC resolution is usually regarded as a 6

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Fig. 11. Simulated link BER in different resolutions (M) when SNRh ¼ 28dB ðBERu;N ðM; 28ÞÞ versus N and mh (upper axis) for (a) h1 ¼ ½117; 65; 47; 35; 21; 12  103 and (b) h2 ¼ ½124; 68; 43; 31; 18  103 .

4. Implementation of an ADC-based DFE receiver

straightforward approach to improve the receiver BER performance. This approach may be accompanied by significant hardware and power penalties. The simulation results verify that with a low tap-count DFE (especially when N < Nw ) one or even two-bits increase in the ADC resolution may have insignificant impact on the BER improvement. Thereby, it supports the claims that the higher values of signal fidelity metrics, which can potentially be enhanced by the increase in the number of the ADC bits [27], do not necessarily result in a lower BER. Fig. 12 shows simulated BERu;N curves for three FR4 channels versus ADC resolution for different number of DFE taps at SNRh ¼ 25 dB. These results indicate that for all the three channels there are cases in which BERu;N ðM þ 1; SNRÞ  BERu;N ðM; SNRÞ and thus confirm that the obtained BER may remain constant despite the increase in M. For example, it can be seen in Fig. 12(a) and (b) that BERu;3 ð6; 25Þ ¼BERu;3 ð7; 25Þ and BERu;2 ð5; 25Þ ¼ BERu;2 ð6; 25Þ respectively. The simulated results also verify that the required number of ADC bits needed to achieve a given BER can be reduced by increasing the DFE tap numbers (for an example, see Fig. 12(c) whereBERu;4 ð5; 25Þ < BERu;3 ð6; 25Þ.

In order to further investigate the BER performance of an ADC-based receiver with embedded DFE, a prototype receiver with one-tap direct DFE is designed and implemented in a 130-nm 1P8M CMOS process. The receiver uses a 5-b flash converter as the core ADC and a reconfigurable embedded DFE to retrieve the transmitted data stream, designed to operate at 1.6 GHz. A simplified single-ended schematic of the receiver with one-tap DFE is shown in Fig. 13, which consists of a track-and-hold (T/H) circuit, a switched-capacitor voltage-mode summer for partial ISI cancellation [28], comparator stage, SR latches and a digital encoder. In order to improve the dynamic performance over broadband input signals, incorporating a T/H circuit in the analog front-end is critical. It largely reduces errors due to skews in the input signal distributed to the multiple comparators, signal-dependent nonlinearity and aperture jitter [29]. In this design, T/H circuit consists of an NMOS sampling switch and a dummy switch followed by a well-tied PMOS source-follower buffer, as shown in Fig. 13. The pseudo differential buffer drives a metal-insulator-metal capacitor Cs and isolates the input sampling

Fig. 12. Simulated link BERs in different DFE taps N for SNRh ¼ 25dB versus number of ADC bits for channels (a) h1 ¼ ½138; 84; 53; 37; 11; 6  103 , (b) h2 ¼ ½109; 61; 30; 18; 9; 5  103 and (c) h3 ¼ ½187; 113; 57; 34; 19; 8  103 .

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Fig. 13. Simplified schematic of the implemented ADC-based receiver with one-tap embedded DFE.

Fig. 14. Schematic diagram of the dynamic comparator.

network from the comparators’ input while drawing 3.8 mA from a 1.2-V supply. Simulation results show that with a 0.35-V input common-mode

voltage, 5-bit linearity at the Nyquist sampling rate for a 1-Vpp input swing is easily achieved by the front-end T/H. In this T/H architecture 8

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falling edge at the Di nodes. M13 and M14 as the input transistors of the second stage are used to enhance the comparator sensitivity through increasing the gain of the latch, while pre-charging the inverters. The offset of the comparator due to the mismatch between the Xi nodes is reduced by turning on M11 and M12 in the reset phase. The comparator shows a delay of 136 ps at 1.6 GHz for a 1-mV differential input with a common-mode voltage of 0.75 V. A Monte-Carlo simulation including both process corners and mismatch variations is used to evaluate the offset error voltage distribution of the comparator. Fig. 15 shows the simulated results of 700 iterations. The simulated standard deviation of the offset voltage is 12.8 mV, which is significantly lower than the conventional double-tail comparator [31]. A careful layout design using common-centroid configuration and multiple interleaving fingers along with the use of dummies for matching critical transistors was utilized to avoid significant SNR degradation due to the offset error. A 96-Ω serpentine structure of Metal 4 is used to generate the reference voltages for the comparators and a simple adjustable current source with resistive load is used to generate each of the DTCs [28]. Fig. 16 shows the timing diagram of the receiver. During the tracking phase, the input signal is stored on the CS capacitor through switch S1. In this period, switch S1d connects the right terminal of capacitor CS to a fixed common-mode voltage VCM . Hence, during the tracking period the voltage across CS is Vi  VCM and the voltage at the input of the comparators is equal to VCM . The switches S1 and S1d are turned ON with clock phases Φs and Φsd respectively. The falling edge of the Φsd triggers the clock of the D flip-flop Φeq and detected MSB of the previous symbol passes through the flip-flop. The outputs of the flip-flop are directly connected to the switches Seq0 and Seq1 to select the correct DTC. Therefore, in the equalize phase, the selected switch connects the left side of CS to VCM  α orVCM þ α. α and α represent the two possible DFE tap values.

the sampling capacitor is the ~40-fF parasitic capacitance at the buffer input which allows a large input sampling bandwidth as the sampling capacitor is significantly smaller than the 110-fFCs and the added capacitive loading due to the comparators. A detailed schematic of the comparator used in the receiver is shown in Fig. 14. This dynamic latch-type comparator offers a fairly high operating speed while consuming no static power [30]. In the reset phase when CLK is low, the differential pair is disabled and M3 and M4 pull up the Di nodes to the supply voltage, VDD and hence transistors M5 and M6 discharge both of the output nodes to ground. During regeneration phase, CLK turns to VDD , transistor M0 turns on and M3 and M4 turn off and an input-dependent differential voltage will build up between the two Di nodes. The second stage start to regenerate the voltage difference on the

Fig. 15. Simulated comparator offset (700 Monte-Carlo).

Fig. 16. Timing diagram of the receiver.

Fig. 18. Layout of the test chip.

Fig. 17. Input clock buffer. 9

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Fig. 19. DNL/INL plots with fin ¼ 1 MHz at 1.6 GS/s.

In this design, α is set to the first post-cursor channel response value. A delayed version of the flip-flop clock signal activates the flash comparators. Then, the partially equalized signal Vin  α or Vin þ α is compared with the reference voltages and results of these comparisons are stored in set-reset (SR) latches. Next, an array of 2-input NAND gates converts the thermometer code to a 1-of-N code as well as fixes any

bubble errors and finally a ROM-based encoder converts the result into a 5-bit Gray code. The main challenge in implementation of such a direct embedded DFE involves meeting the 1-UI critical feedback delay path tFF þ tsum þ tADC < 1 UI

(13)

where tADC is the conversion time of the ADC, tsum is the summer delay, and tFF is the flip-flop clock-to-output delay. This implies that conversion of the previous sample should be completed before being sampled by the flip-flop hence imposing a challenging feedback delay requirement. In this design, the summer circuit is designed to settle to 1% of the final value within 80 ps ( 0.13 UI). Therefore, four times the RC delay of the summer should be less than this timing constraint where C is the total capacitance of the summer output node and R is the ON-resistance of the selected switch (Seq0 or Seq1). PMOS pass-gates with minimum channel lengths are used to implement the switches while the transistor widths are sized to meet the speed requirements of the receiver. As shown in the timing diagram in Fig. 16, S1d is turned off slightly earlier than the main NMOS switch S1. By floating the bottom plate of capacitor CS , the signaldependent charge injection from switch S1 does not disturb the sampled charge. The charge injection on CS due to the switching of S1d is constant and can be eliminated by using the differential structure. Moreover, the sampling duration of the input signal ends when switch S1d is turned off so the signal-dependent track-to-hold switching time of S1 is not critical. The clock generation circuit has not been implemented in the

Fig. 20. Simulated SNDR/SNFR versus input frequency at 1.6 GS/s.

Fig. 21. (a) Frequency and (b) simulated 1.6-Gb/s pulse responses of two FR4 backplane channels. 10

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as a CML to CMOS conversion stage. AC-coupling removes any DC component and shifts the voltage level at the input of the inverter, which is DC biased to its trip point by using the feedback resistor. Tapered CMOS inverters are then used to provide enough drive strength to globally distribute the CMOS clock CLK=CLK to the circuit blocks. The sampling clock signal with 25% duty cycle, as needed in the ADC design, is provided using pass gates. Relative to conventional clock generation techniques, like using divider, transmission gates have less timing delay, leading to less clock skew among the stages [33]. 5. Simulation results This section summarizes the simulation results of both the standalone ADC chip and the ADC-based DFE receiver. Fig. 18 shows the chip layout that occupies an active area of 0.11 mm2. The circuit operates at a supply voltage of 1.2 V. In order to ensure that the core ADC performance is sufficient to support link operation, the functionality of the receiver as a conventional flash ADC is evaluated by simply disabling the D flip-flop clock. The simulated DNL/INL characteristics that are extracted from histograms of the ADC output in response to a low frequency sine wave at the sampling rate of 1.6 GHz are shown in Fig. 19. The DNL and INL remain below 0.62 LSB and 0.65 LSB, respectively. The dynamic performance of the ADC at 1.6 GS/s is shown in Fig. 20. The ADC achieves an SNDR of 29.7 dB (4.64 ENOB) and SFDR of 36.2 dB at 17-MHz input signal. The effective resolution bandwidth (ERBW) is equal to 732 MHz. The power consumption of the converter is 163 mW. Therefore, with a figure-of-merit (FOM) defined by FoM ¼

Power fs  2ENOB

½pJ=conv:- step

(14)

the corresponding FOM is 4.08 pJ/conv.-step at low input frequencies. The performance of the circuit as an ADC-based receiver with embedded one-tap DFE was evaluated at 1.6 Gb/s over a 46-inch highloss FR4 backplane channel with 1-Vpp 218–1 PRBS data. The channel behavior was emulated through its measured S-parameters to incorporate ISI into the signal. The channel loss at Nyquist bandwidth is about 14 dB with an impulse response of h ¼ ½151; 66; 38; 18; 11; 9; 6; 4 mV, as shown in Fig. 21. The eye diagram at the receiver output after reconstruction of the digital output word is shown in Fig. 22 with and without DFE enabled. The DFE tap coefficient α is set to the first post-cursor channel response h1 ¼ 66 mV. While the ISI subtraction through enabling the DFE improves the eye opening by 7 LSB, the estimated improvement using Eq. (6) is Δew;1 ¼ 2h1 ¼ 2  66 ¼ 132 mV ’ 4:5 LSB. This indicates that simple removing of the positive

Fig. 22. Simulated ADC output for a 1-Vpp 1.6 Gb/s 218–1 PRBS input with no TX equalization over a 46-in FR4 channel with 14 dB loss at the Nyquist frequency (a) without and (b) with one-tap DFE enabled.

receiver. A previously designed phase generator with slight modifications is used as the master clock source for the receiver. Fig. 17 shows the input clock buffer [32]. The first CML buffer stage uses DC suppression and provides some gain to maximize the CML output signal swing. An AC-coupled inverter with resistive feedback proceeding the buffer is used

Fig. 23. Simulated bathtub curves with and without one-tap DFE for the (a) 46-inch FR4 channel with mh ¼ 3 and (b) the 32-inch channel with mh ¼ 1, for a 214–1 PRBS input with 1-Vpp TX swing. 11

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Fig. 24. Comparison between simulated BER performance of the receiver with the one-tap DFE at 1.6 GS/s and estimated BER using (11) ðBERu;1ð11Þ Þ for the (a) 46inch and (b) 32-inch FR4 channels.

channels with low ISI and a higher tap-count for channels with larger ISI may supply the receiver with adequate BER performance without the need to post-ADC equalization. It was shown that an embedded DFE with an appropriate number of taps may compensate for increases in ADC resolution while achieving even better BER performance than that obtained through resolution enhancement.

and negative post-cursor ISI contributions through the worst-case analysis cannot accurately predict the eye opening improvement. BER bathtub curve for different phase error of the sampling clock over the FR4 channel is shown in Fig. 23(a). The simulated bathtub plot was produced with 1Vpp 214 1 PRBS input without any transmit equalization. The procedure was repeated for a 32-inch channel with ~11 dB loss at the 0.8-GHz Nyquist frequency and a discrete-time impulse response of h ¼ ½258; 76; 36; 18; 10; 9; 4 mV. The magnitude and 1.6-Gb/s pulse responses of the channel are shown in Fig. 21. The link BER performance over the channel is shown in Fig. 23(b). While for the first channel, the DFE opens the fully closed eye and results in ~0.2-UI timing margin at a BER ¼ 109, the horizontal eye opening for the lower-loss channel after applying the DFE improves to near 0.3 UI at the same BER level. The obtained results can be explained in terms of different channel ISI profiles. The number of the transitions in the 32-inch channel output ðmh Þ is equal to 1 which means no overlap between the elements of the set uþ and u . Thus, the applied DFE further extends the distance between the two subsets, and as can be seen in Fig. 23(b), the bathtub curve shows a rapid decay in BER as the clock phase error starts to decrease. The other channel has 3 transitions in its output set and the DFE reducesmh from 3 to 1. Fig. 23(a) indicates that with the one-tap DFE, a clock phase error less than ~0.25 UI is required to fall off the BER in the regime of rapid descent. The BER performance of the receiver over the two channels for different SNR conditions is shown in Fig. 24. The different SNR scenarios are created by adding a random noise component to the sampled input. Fig. 24 indicates that the analytical expression (11) can predict the BER achieved by the ADC-based DFE receiver with the maximum error of less than one and a half order of magnitude at all SNR conditions.

Declarations of interest None. References [1] J. Lee, M.S. Chen, H.D. Wang, Design and comparison of three 20-Gb/s backplane transceivers for duobinary, PAM4, and NRZ data, IEEE J. Solid State Circ. 43 (2008) 2120–2133. [2] A. Sheikholeslami, R. Payne, SE3: will ADCs overtake binary frontends in backplane signaling?, in: 2009 IEEE Int. Solid-state Circuits Conf. - Dig. Tech. Pap., 2009, pp. 514–514. [3] H. Chung, G.Y. Wei, Design-space exploration of backplane receivers with highspeed ADCs and digital equalization, in: Proc. Cust. Integr. Circuits Conf., 2009, pp. 555–558. [4] M. Harwood, N. Warke, R. Simpson, T. Leslie, A. Amerasekera, S. Batty, D. Colman, E. Carr, V. Gopinathan, S. Hubbins, P. Hunt, A. Joy, P. Khandelwal, B. Killips, T. Krause, S. Lytollis, A. Pickering, M. Saxton, D. Sebastio, G. Swanson, A. Szczepanek, T. Ward, J. Williams, R. Williams, T. Willwerth, A 12.5Gb/s serdes in 65 nm CMOS using a baud-rate ADC with digital receiver equalization and clock recovery, in: Dig. Tech. Pap. - IEEE Int. Solid-state Circuits Conf., 2007. [5] J. Cao, B. Zhang, U. Singh, D. Cui, A. Vasani, A. Garg, W. Zhang, N. Kocaman, D. Pi, B. Raghavan, H. Pan, I. Fujimori, A. Momtaz, A 500 mW ADC-Based CMOS AFE with digital calibration for 10 gb/s serial links over kr-backplane and multimode fiber, IEEE J. Solid State Circ. 45 (2010) 1172–1185. [6] A. Varzaghani, C.K.K. Yang, A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter, IEEE J. Solid State Circ. 41 (2006) 935–944. [7] E.H. Chen, C.K.K. Yang, ADC-based serial I/O receivers, IEEE Trans. Circuits Syst. I Regul. Pap. 57 (2010) 2248–2258. [8] E.H. Chen, R. Yousry, C.K.K. Yang, Power optimized ADC-based serial link receiver, IEEE J. Solid State Circ. 47 (2012) 938–951. [9] K. Hassan, T.S. Rappaport, J.G. Andrews, Analog equalization for low power 60 GHz receivers in realistic multipath channels, in: GLOBECOM - IEEE Glob. Telecommun. Conf., 2010. [10] A. Shafik, K. Lee, E.Z. Tabasy, S. Palermo, Embedded equalization for ADC-based serial I/O receivers, in: 2011 IEEE 20th Conf. Electr. Perform. Electron. Packag. Syst. EPEPS-2011, 2011, pp. 139–142. [11] B. Abiri, A. Sheikholeslami, H. Tamura, M. Kibune, A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS, in: Dig. Tech. Pap. - IEEE Int. Solid-state Circuits Conf., 2011, pp. 436–437. [12] Y. Frans, J. Shin, L. Zhou, P. Upadhyaya, J. Im, V. Kireev, M. Elzeftawi, H. Hedayati, T. Pham, S. Asuncion, C. Borrelli, G. Zhang, H. Zhang, K. Chang, A 56-Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16-nm FinFET, IEEE J. Solid State Circ. 52 (2017) 1101–1110.

6. Conclusion This paper studies the BER performance of an ADC-based serial link receiver with embedded analog DFE and discusses the conditions under which the maximum BER improvement could be obtained. Since embedding a high tap-count analog DFE is not feasible in practical implementations, BER improvement by receivers with embedded DFE is typically higher than a BER-optimal ADC in which the quantization thresholds are located at the crossover points of the conditional PDFs. But while implementation of a BER-optimal ADC due to the required repetitive algorithms that are usually used for online calibration of threshold levels, may display prohibitive power, an ADC with embedded DFE can be realized in a more energy-efficient way. A low tap-count analog DFE in 12

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Integration, the VLSI Journal xxx (2018) 1–13 [33] X. Yang, J. Liu, A 10 GS/s 6 b time-interleaved partially active flash ADC, IEEE Trans. Circuits Syst. I Regul. Pap. 61 (2014) 2272–2280.

[13] H. Yueksel, L. Kull, A. Burg, M. Braendli, P. Buchmann, P.A. Francese, C. Menolfi, M. Kossel, T. Morf, T.M. Andersen, D. Luu, T. Toifl, A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS, in: Eur. Solid-state Circuits Conf., 2015, pp. 148–151. [14] E.Z. Tabasy, A. Shafik, K. Lee, S. Hoyos, S. Palermo, A 6 bit 10 GS/s TI-SAR ADC with low-overhead embedded FFE/DFE equalization for wireline receiver applications, IEEE J. Solid State Circ. 49 (2014) 2560–2574. [15] A. Shafik, E. Zhian Tabasy, S. Cai, K. Lee, S. Hoyos, S. Palermo, A 10 Gb/s hybrid ADC-based receiver with embedded analog and per-symbol dynamically enabled digital equalization, IEEE J. Solid State Circ. (2016) 671–685. [16] A. Varzaghani, C.K.K. Yang, A 4.8 GS/s 5-bit ADC-based receiver with embedded DFE for signal equalization, IEEE J. Solid State Circ. 44 (2009) 901–915. [17] A. Mahmoudi, P. Torkzadeh, M. Dousti, A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS, AEU - Int. J. Electron. Commun. 89 (2018) 6–14. [18] K. Joshua, D.T. Lin, L. Li, M.P. Flynn, A reconfigurable FIR filter embedded in a 9b successive approximation ADC, Proc. Cust. Integr. Circuits Conf. (2008) 711–714. [19] E.Z. Tabasy, A. Shafik, S. Huang, N.H.W. Yang, S. Hoyos, S. Palermo, A 6-b 1.6-GS/s ADC with redundant cycle one-tap embedded DFE in 90-nm CMOS, IEEE J. Solid State Circ. 48 (2013) 1885–1897. [20] S. Kasturia, J.H. Winters, Techniques for high-speed implementation of nonlinear cancellation, IEEE J. Sel. Area. Commun. 9 (1991) 711–717. [21] V. Stojanovic, A. Ho, B. Garlepp, F. Chen, J. Wei, Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver, in: IEEE Symp. VLSI Circuits, 2004, pp. 348–351. [22] Y.-S.S.Y.-S. Sohn, S.-J.B.S.-J. Bae, H.-J.P.H.-J. Park, C.-H.K.C.-H. Kim, S.-I.C.S.I. Cho, A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pinto-pin time skew compensation, in: Proc. IEEE 2003 Cust. Integr. Circuits Conf. 2003., 2003, pp. 473–476. [23] IEEE P802, 3ap Task Force Channel Model Material, 2006. http://www.ieee802. org/3/ap/public/channel_model/. [24] R. Narasimha, M. Lu, N.R. Shanbhag, A.C. Singer, BER-optimal analog-to-digital converters for communication links, IEEE Trans. Signal Process. 60 (2012) 3683–3691. [25] Y. Lin, A. Xu, N. Shanbhag, A. Singer, Energy-efficient high-speed links using BERoptimal ADCs, in: 2011 IEEE Electr. Des. Adv. Packag. Syst. Symp. EDAPS 2011, 2011. [26] Y. Lin, M.S. Keel, A. Faust, A. Xu, N.R. Shanbhag, E. Rosenbaum, A.C. Singer, A study of BER-optimal ADC-based receiver for serial links, IEEE Trans. Circuits Syst. I Regul. Pap. 63 (2016) 693–704. [27] Y. Lai, CMOS Integrated Analog-to-digital and Digital-to-analog Converters, 2009. [28] A. Emami-Neyestanak, A. Varzaghani, J.F. Bulzacchelli, A. Rylyakov, C.K.K. Yang, D.J. Friedman, A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE, IEEE J. Solid State Circ. 42 (2007) 889–896. [29] M. Choi, A.A. Abidi, A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS, IEEE J. Solid State Circ. 36 (2001) 1847–1858. [30] M. Miyahara, Y. Asada, D. Paik, A. Matsuzawa, A low-noise self-calibrating dynamic comparator for high-speed ADCs, in: Proc. 2008 IEEE Asian Solid-state Circuits Conf. A-SSCC 2008, 2008, pp. 269–272. [31] D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, B. Nauta, A double-tail latchtype voltage sense amplifier with 18ps SetupþHold time, in: 2007 IEEE Int. Solidstate Circuits Conf. Dig. Tech. Pap., 2007, pp. 314–605. [32] C. Menolfi, T. Toifi, P. Buchmann, M. Kossel, T. Morf, J. Weiss, M. Schmatz, A 16Gb/S source-series terminated transmitter in 65nm CMOS SOI, in: Dig. Tech. Pap. - IEEE Int. Solid-state Circuits Conf., 2007.

Azad Mahmoudi was born in Sardasht, Iran, in 1983. He received the B.S. and M.S. degrees in electrical engineering from Urmia University, Urmia, Iran, in 2005 and 2008, respectively. He is currently working toward the Ph.D. degree in the Department of Electrical and Computer Engineering, Science and Research Branch of Islamic Azad University, Tehran, Iran. His research interests include high-speed analog and mixedsignal integrated circuit design, with special emphasis on data converters.

Pooya Torkzadeh was born in Isfahan, in 1980. He received the B.Sc. degree from Isfahan University of Technology (IUT), Iran, in 2002 and the M.Sc. and Ph.D. degrees from the Sharif University of Technology (SUT), Iran, in 2004 and 2011 respectively both in electrical engineering. He is currently faculty member of Islamic Azad University, Science and Research Branch. Since 2003 he has joint to Sharif Integrated Circuit and System Group (SICAS) working on continuous/discrete time sigma-delta modulators with low power consumption for low power appliances. He has received many patents in the field of sigma-delta modulator designing and optimizing. He is the author and coauthor of more than 25 published international journal and conference papers on analog and digital integrated circuits. His research interests include ADC signal converters, low power phase locked loops (PLLs) with ultra-low phase noise amount for broad-band applications.

Massoud Dousti received B.S. in Electrical Engineering from Orleans University, Orleans, France and M.S. degrees in Electronics (Microwave and Optics) from Limoges University, Limoges, France, in 1991 and 1994 and Ph.D. in Electronics (Active Microwave Circuits) from University of Paris VI, Pierre et Marie Currie, in 1999 respectively. He served as a teaching assistant in the Department of Electrical Engineering at Ensea, Cergy Pontoise, France from 1998 to 2000. In 2001 he joined Department of Electrical and Computer Engineering of Science and Research branch, Islamic Azad University, Tehran, IRAN, where he is now an Associate Professor. His research interests are linear and non-linear microwave/RF circuits and systems design, millimeter wave circuits design, and MMIC technology.

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