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A test bench for evaluating fast ADCs
Nuclear Instruments and Methods in Physics Research A 342 (1994) 578-590 North-Holland
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH Section A
A test bench for evaluating fast ADCs H.B. Crawley, R. McKay, W.T. Meyer *, E.I. Rosenberg, W.D. Thomas Department of Physics and Ames Laboratory, USDOE, Iowa State University, Ames, IA 50011, USA
(Received 1 April 1993)
This document describes a test bench and procedures used to evaluate the performance of analog-to-digital converters that operate in the range of 10 to 140 million samples per second .
1. Introduction With the availability of a wide selection of analogto-digital converters that can operate at speeds greater than 100 megasamples per second (MSPS), the user needing to select a device faces the difficult task of sorting the information from various manufacturers. In part this is because the manufacturers use different tests and definitions of parameters . To address this problem, we have built an ADC test bench that operates up to 140 megasamples per second, and performs a set of tests producing results under the same conditions for all devices. This allows the user to compare the characteristics of most interest for a particular application and thus to choose the device best fitting the need . Our motivation is to help select devices for use in high energy physics experiments at particle colliders. However, the tests are very general and the results should be useful to a wide range of users. Our starting point has been the proposed IEEE Standard 1057, "IEEE Trial-Use Standard for Digitizing Waveform Recorders", July 1989 [1]. However, that document is intended for commercial waveform recorders, not the actual ADC devices, so some adjustments to the procedures were necessary. We have kept the conventions and symbol definitions of that document . Other useful sources have been technical documents from manufacturers and articles in the trade literature [2,6]. A brief description of these tests has been published elsewhere [7], as have some of the first
* Corresponding author.
results [8,9]. This report gives a detailed description of the tests. Comparative results from devices we have tested will be in future publications . While we have been careful to maintain the quality of our tests, devices can have unavoidable differences that affect the results. Also, the results in a specific application may vary from our results due to external factors. Àll tests are performed at ambient room temperature with forced air cooling on the evaluation board. Finally, the reader is cautioned that we test only one or two samples of each device, the results are not an average over a large number of samples, nor do we test for long-term aging of devices. We intend to test most of the major commercially available devices, and users with special needs may contact us . 2. Test bench The test bench consists of four major parts : a clock/trigger module, an ADC evaluation board, a readout board to interface the evaluation board to our CAMAC-based data acquisition system, and a set of test signal sources . The test bench is controlled from a VAXStation 3100 computer, as shown in Fig. 1 . We use an IOTech SCSI/GPIB interface to create a GPIB connection to the signal sources and a Jorway model 73 crate controller to interface CAMAC to the computer's SCSI bus. In order to avoid false readings due to startup effects when an ADC goes from its quiescent state to its active state, we take two consecutive records and use the data from the second one. The operator has the option of turning off this feature in order to look for startup effects.
0168-9002/94/$07.00 © 1994 - Elsevier Science B.V . All rights reserved SSDI0168-9002(93)E1257-X
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n
._____________-__
_____________________________ Faraday Cage
M Mi mmo
CAMAC
;Evaluation Board/
'qumila
Crate Controller VAXStation 3100 SCSI
Readout Board
SCSI/GPIB GPIB
Universal Source
Function Generator
Signal Generator
Fig. l . The ADC test bench. We have enclosed the CAMAC crate in a Faraday cage in order to minimize pickup from external sources of radio frequency noise . 2.1 . Clock/ trigge r module
This is a CAMAC board with a set of four crystal oscillators operating at frequencies of 160, 200, 240 and 280 MHz. Circuits to divide by two, four, eight, and sixteen are used to produce output frequencies of 10, 15, 17 .5, 20, 25, 30, 40, 50, 60, 70, 80, 100, 120, and 140 MHz. Additionally, there is provision for an external clock. The operator chooses a specific frequency via CAMAC. To reduce noise, we turn off all the oscillators except the one needed . Connectors provide ECL and TTL outputs for three signals: the clock at
the selected frequency, an event trigger, and a pretrigger which comes one full clock cycle before the event trigger. A trigger is generated whenever the frequency selection circuitry is addressed via CAMAC. Thus, the controlling computer can select the clock frequency and generate event triggers . A special feature of the synchronization circuit is the ability to adjust under computer control the duty cycle of the clock waveform . We included this feature because some ADCs perform best with an asymmetric clock signal . Fig. 2 shows a block diagram of the clock/trigger board. 2.2. Evaluation board
This is usually supplied by the ADC manufacturer . Since manufacturers follow their own standards re-
SOFTWARE SELECT
05C OUT 30.
ECL
PRE-TRIG OUT
DRIVER
TRIG OUT
SYNCNRO CIRCUIT OSC OUT TTL DRIVER
Fig. 2. The clock/trigger board.
[
PRE-TRIG OUT TRIG OUT
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H. B. Crawley et al. /Nuel. Instr. and Meth in Phys. Res. A 342 (1994) 578-590
garding pinout and signals, we are prepared to accept a wide variety of evaluation boards . Generally, the evaluation board contains an input amplifier, the ADC itself, and various biasing and regulation circuits . Since this is where the most care must be taken to optimize ADC performance, we prefer to use a manufacturer's board, if available. When necessary, it is possible to build an evaluation board using a manufacturer-supplied circuit schematic or a custom design . We can provide guidelines to users needing to build evaluation boards . In order for certain important tests to be done, the evaluation board must have a DC coupling from the test signal to the ADC input pin. 2.3. Readout board
This is a CAMAC board which accepts the evaluation board as a daughter board mounted at a right angle to the readout board. To accommodate a range of evaluation boards it contains four different daughter board connectors, and the pinout of these can be reprogrammed using short wire-wrapped jumpers. The connectors have been chosen to match the evaluation boards known to be available at the time the board was designed . The readout board's primary purpose is to accept data from the evaluation board at the full readout speed - up to 140 MHz - and store it until it can be read out at the much slower CAMAC data speeds typically 1 MHz. For this purpose the board contains a 2K x 16-bit buffer made from 5 ns ECL memory chips. Two cable connectors provide inputs for the address register and for the memory strobe . Normally both of these are connected to the clock output from the clock trigger board, but separate inputs are provided to allow different cable delays . The only CAMAC function of the board is to read out the memory buffer either in single word mode or Q-stop DMA mode . Fig. 3 shows a block diagram of this board. 2 .4. Signal sources
For DC levels we use a Hewlett-Packard 3245A Universal Source unit, controlled via the GPIB bus . For DC levels, this unit gives 24 bit precision. For triangle and square wave signals we use a Hewlett-Packard model HP3314A function generator, also controlled via the GPIB bus. For sine wave inputs we use a Hewlett-Packard model HP8656B signal generator. Because some of the tests are very sensitive to the harmonic content of the sine wave, we use external passive filters purchased from TTE, Inc. to remove the higher harmonics. These filters provide a minimum of 40 dB of attenuation at
ANALOG INPUT
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FLASH EVALUATION BOARD
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Fig. 3. The readout board .
the first harmonic . Use of these filters limits our tests to 32 specific frequencies in the range between 0.182 and 58 .39 MHz for which we have filters. The operating computer controls the signal generator via the GPIB bus, but the filters are inserted manually . When a DC offset is required for a sine wave, a DC output from the function generator is added to the output of the sine wave generator after the filter . The function generator gives the DC offset and the signal generator superimposes the sine wave . This produces no observable degradation of the sine wave . For some devices, it is necessary to amplify the input signal either to prevent saturation or to permit the signal source to operate in its region of best performance. When this is necessary, a Phillips Scientific model 771 variable gain NIM amplifier is used . If filters are being used to purify a sine wave, they are placed after this amplifier. 3 . Tests
The tests are categorized according to the input signal . An event record consists of M (maximum value 2048) consecutive digitizations of the input signal . The sampling frequency is denoted by f,, N denotes the
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number of digitized bits and k denotes an ADC code value. 0 .50
3.1 . DC levels
We get the following seven parameters from the DC tests: gain, offset, differential nonlinearity, maximum static error, integral nonlinearity, monotonicity, and hysteresis . The first step in examining any ADC is to determine the DC voltage corresponding to the lower transition for each ADC code value. We denote the transition level between code k - 1 and code k by T[k]. The transition level is the input voltage that produces a 50-50 mix of the two codes in the event record, as determined by a linear interpolation between the measurements on either side of the transition . With the universal source set to produce DC levels, we start with an input level slightly lower than that needed to produce code 1. We take a record of 512 samples and note the percentages of codes 0 and 1 . The input level is increased until the percentage of code 0 is less than 50% and the interpolated value for T[1] is calculated . This step is repeated for each of the 2' - 1 code values, giving us the array of values T[k] . Once we have determined T[k] we compute the gain and offset by doing a least squares fit of a straight line to the data, assuming equal measurement errors for all codes. The results of the fit are the slope and intercept of the straight line. The gain (in mV per ADC count) is the measured slope and the offset (in V) is the intercept plus the width of the first code . (We add the width of the first code because the intercept from the fit represents the hypothetical lower edge of code 0, whereas the offset is defined to be the lower edge of code 1 .) Note that these definitions for gain and offset differ from those in IEEE Std. 1057 . With our definition, the gain is the same as the width of an ideal code (denoted by Q) . Fig. 4 shows the residuals from the fit. Transdion Residuals
10
5 4969
0
-1 0 00
00
640
1280 A/D code
1920
É
-6 .4969 256.0
Fig. 4. The residuals from a straight-line fit to the transition levels . The vertical axis is in units of least significant bits, and the horizontal axis is the ADC code value. Note that the right-hand scale shows the difference in mV .
00
-0 .50
0
00
640
128 .0 A/D code
192 .0
256 .0
Fig. 5. The differential nonlinearity vs ADC code for an eight-bit ADC. This measurement also gives us the differential nonlinearity and the integral nonlinearity. The differential nonlinearity is a measure of the width of each code normalized to the ideal width. The differential nonlinearity of code k is defined as : DNLK[k ] =(T[k+1 ] -T[k ] -Q)/Q, where Q is the ideal code width. A DNLK[k] value of 1 indicates that a code is twice as wide as the ideal, a value of 0 indicates it is as wide as the ideal and a value of -1 indicates that it is missing, i.e ., that it has zero width. The differential nonlinearity (DNL) for the ADC is defined to be the DNLKjk] with the highest absolute value, DNL= maxIDNLK[k]~ . an k
Fig. 5 shows a plot of DNLK[k] for an eight-bit ADC. We define the maximum static error to be the maximum of the absolute value of the deviation of T[k] from the straight-line fit. This is given in units of mV . We define the integral nonlinearity (INL) to be the maximum static error expressed as a percentage of full scale. Monotonicity is checked by setting the input voltage at the midpoint of each code value as determined from the value of (T[k + 1] - T[k])/2. The average value of the resulting data record is called A[k] . The array A[k] is scanned to check that A[k + 1] -A[k] has the same sign for all k. If so, the ADC is monotonic. If the ADC is not monotonic, we record the value of the worst deviation from monotonicity, in units of ADC counts . Hysteresis is checked by repeating the scan for A[ k ], this time starting with the top code and scanning downwards. This gives us the array A'[k]. The hysteresis parameter is defined as hysteresis = max I A' [ k] -A[ k ] . all k
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H.B . Crawley et al. INucl. Instr. and Meth. in Phys . Res. A 342 (1994) 578-590
3.2. Sine waves
All of the tests in this section use sine wave inputs . As discussed earlier, the quality of many of the results depends strongly on the existence of a pure sine wave . To get as pure a wave as possible, we use external filters on the output of the signal generator, and this limits us to discrete values of sine wave frequencies . In addition, care must be taken that the data record does not contain an integral number of sine wave cycles .
â
10
3.2.1 . Single event
We get the following parameters from this test : signal-to-noise ratio, normalized peak error, and number of effective bits . One of the most important tests is to take a single record of a pure sine wave input and do a computer fit of a sine wave to the data . By subtracting the fit value from the data value we get a measurement of the noise level for a particular choice of sampling and sine wave frequencies . For this test we fix the sine frequency to be 1/54 .8 times the sample frequency. The choice of the ratio of 54 .8 was somewhat technical, but it involved avoiding an integral number of cycles in the data record, having enough cycles to allow a good computer fit, and having frequencies which could be shared with other tests, thus reducing the number of filter values needed . Fig. 6a shows the first 512 samples of an event record for an eight-bit ADC from this test and Fig. 6b shows the residuals from the sine wave fit . Once we have the residuals from the fit we calculate the average rms noise using the equation 1 rms noise = ~-
O
n1
M n=1
Yy
-
yn
1/2
' )2J
,
where the y,, are the data values within the record and the yn , are the fitted values to the data. The signal to noise ratio is given by SNR = rms signal/rms noise, where the rms signal is the fitted amplitude divided by the square root of two and the rms noise is given above. The SNR can be a function both of sampling frequency and input signal frequency. The sine wave fitting algorithm used is the four-parameter fit given in section 4.1 .3.2 of IEEE Std. 1057 . The peak error is defined to be the data sample with the largest difference in magnitude between the data and the fit. The normalized peak error is calculated from this by dividing by three times the standard deviation of the differences . A normalized peak error significantly greater than one indicates that differential nonlinearity is an important source of error. Another way to express noise is in terms of effective bits, a concept which has emerged as one of the most
Single Sine, Fd Resid 1 095MHz
64970
050
32485
00
00
-050
-10 00
É
-3 2485
128.0
2560 memory adr
3840
-6 4970 512 0
Fig. 6. (a) The first 512 samples of an event record with a sine wave input. (b) The residuals from a sine wave fit for an eight-bit ADC. The left-hand vertical axis is in units of ADC counts, the right-hand vertical axis is in units of mV into the evaluation board, and the horizontal axis is the bin in the data sample . Only the fast 512 samples of the total record of 1024 are shown. useful parameters describing ADC performance. The fundamental idea is that even if the ADC returns, say, an eight-bit value, the significance of the result can be reduced because of noise so that fewer of the bits are significant. The effective bits parameter is one way of quantifying this measure . The number of effective bits, E, is defined as actual rms error
ideal rms quantization error )' where N is the number of digitized bits . The ideal quantization error is the ideal width of a code bin (Q) divided by the square root of 12 . The number of effective bits is, in general, a function of the sampling frequency and the frequency of the input sine wave . In our tests when we quote a single value for number of effective bits it will be the value at the Nyquist limit for the highest sampling frequency tested . More generally, we prefer to present plots of E as a function of frequency, as described next . 3 .2 .2 . Effective bits scan
To give more information, we created a test where we scan the number of effective bits, E, as a function of sine frequency for fixed sample frequency . In principle, the sine frequency can exceed the Nyquist limit
KB. Crawley et al. I Nucl. Instr. and Meth . in Phys. Res. A 342 (1994) 578-590 Eff. Bits scan
80
ADC codes around the middle of the range) and at the extremes of amplitude.
7 .0 60
3.2.3. Harmonic analysis
50 4 .0 30 2 .0 10 0 .0 00
100
200 300 40 .0 Frequency (MHz)
500
600
Fig. 7. The number of effective bits vs sine frequency in MHz for an eight-bit ADC running at 120 MSPS . and still give a valid result for E. The results are presented as a plot of E vs f,ne for a particular f, . Fig. 7 shows a typical plot . When we do an effective bits scan, we also keep track of the rms error associated with each ADC code . This lets us look for troublesome codes and for effects correlated with amplitude or slew rate . Fig. 8a shows such a plot for an eight-bit device with no problems. As an example of such a plot revealing problems, Fig. 8b shows the same device operated under stressed conditions (i .e ., a very high sample rate and a high input frequency) . Under these conditions we find evidence for higher rms values at both high slew rates (the 10
S;agle Sine, RMS vs ADC 1 .095MHz
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a
m
E
00 0 0
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128 .0
m N
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We get the following parameter from this test : total harmonic distortion . Harmonic distortion is the presence of unwanted Fourier components at frequencies which are a multiple of the applied sine wave frequency. To measure the total harmonic distortion we take a record of a pure sine wave and perform a discrete Fourier transform (DFT) to measure the strength of the harmonics in the observed record . The subject of DFTs is a complicated one which has been discussed in many places, and our primary reference has been the book Numerical Recipes by Press et al . [10] . In order to reduce aliasing caused by abrupt changes at the ends of the data record, it is customary to weight the raw data with a window function, which is a function that goes smoothly from zero at the extremes of the window to a value of 1 .0 at the center . Many such functions exist, and we have chosen a so-called "four term Blackman-Harris function". To calculate the power spectrum, we use data records of 1024 values which we divide into three half-overlapping windows of 512 values each . We calculate the DFT using the subroutine RPA from the CERN software library, which performs all calculations in double precision and we have verified its accuracy on computer generated sine waves to a level of 14 bits . By choosing a sine frequency which is 1/13 .7 times the sampling frequency we set the scale of the frequency plot to have the right range for our purposes . In order to reduce the background level, we take 25 records and average the results. The power spectrum is calculated by adding in quadrature the real and imaginary parts of the DFT. We show a sample plot of the power spectrum in Fig. 9. In addition to a strong peak at the fundamental
00
E
ADC Code
Fig . 8. (a) The rms error associated with each ADC code value for an eight-bit ADC at 60 MSPS . (b) The same device but with the ADC running at a very high sample rate (120 MSPS) and with a high input frequency.
Fig. 9. The power spectrum for an eight-bit ADC. The vertical axis is the logarithm of the power in arbitrary units and the horizontal axis is frequency in MHz.
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frequency we can see small peaks at harmonic frequencies . In addition, there is a background level which is set by the quantization error of the ADC. From the power spectrum we calculate the total harmonic distortion (THD) as follows. From Fig. 9 we see that the peak is contained in fewer than nine bins . (This width is mainly determined by the window function and the relatively narrow peak was one reason we chose to use the Blackman-Harris function .) We calculate the power squared in the fundamental by adding the square of the power in each bin of the peak . Similarly we calculate the power squared in the first five harmonics, also using nine bins per harmonic . The THD is defined as THD = 10 log,, ( fundamental/harmonics~ . We also show in the figure the separate values in arbitrary units for the fundamental and the first three harmonics. The rms value shown in the figure is the root-mean-square deviation of the THD values from the 25 scans. It is a measure of the reproducibility of the results. 3 .2.4. Multiple euent scan
We get the following parameters from this test : fixed error in sample time and aperture uncertainty . In this test we take ten or more scans using a sine wave that is 4/13 .7 times the sample rate, fit a sine wave to each scan, and compute and save the residuals for each scan separately . The residuals are converted to a time difference by dividing by the slope of the fitted curve for that point. To avoid dividing by small numbers, data points within ± 15° of the sine peak are removed. We denote the nth time difference (n = 1 . . . M) of the ith scan (i = 1 . . . 10) by din- We then calculate the bin-by-bin average of the d in : 1
m
Dn = -Y_ d in , m 1-1
0 .10
0
00
-0 .10 , 0 0
128.0
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Memory adr
Fig. 10 . 512 values of the array D from the test to measure fixed error in sample time . The vertical axis is in us and the horizontal axis is the bin number within the data record .
Fig. 11 . A histogram of the average residuals from the multiple event scan . where m < 10 is the number of scans with the nth point outside of the 15° cut. The average of all the D is D. Fig. 10 shows a plot of D for an eight-bit ADC. The fixed error in sample time is the maximum value of I D - D I . It is expressed in ns and represents a nonrandom error in the instant of sampling . This may be due to circumstances internal to the ADC or to external factors like noise on the ADC clock signal . The aperture uncertainty, or timing jitter, is the standard deviation of the sample instant in time . An upper bound on this value is the standard deviation of the din distribution . This is an upper bound because it can include noise from sources other than timing jitter . Fig. 11 shows a histogram of the din and the rms value of this distribution is used for the upper bound on the aperture uncertainty . 3.2.5 . Analog bandwidth scan
We get the following parameters from this test : minimum and maximum analog bandwidth. Because it is in part an analog device, an ADC has an analog bandwidth, defined as the input frequency range over which the gain of the device is within ±3 dB of its value at a specified reference frequency. The gain is defined to be the ratio of the output signal (in ADC counts) to the input signal (in mV). If there are both upper and lower 3 dB cutoffs, both numbers are given. If only one number is given, it is the upper limit and the lower limit does not exist because the gain stayed in the allowed range to the lowest frequency measured . We measure the analog bandwidth using a sine wave input centered at midrange on the ADC and covering the range from 10% to 90%. At each frequency the input to the ADC is monitored with an oscilloscope to be sure the input amplitude is held constant . Variations with frequency, both in the output of the signal generator and due to bandwidth effects of input amplifiers on the evaluation boards, make this step necessary. The array of values resulting from this
H.B. Crawley et al. I Nucl. Instr. and Meth . in Phys. Res. A 342 (1994) 578-590 Bandwidth Plot
1 .20
v
0 .80
0
0.60
v â E a
192 .0
û
va
0 .40 0 .20 0 .0 0 .0
Triangle DNL data
256 .0
1 .0
585
Lower 3 dB limit : Upper 3 dB limit: 15.0
128 .0
64 .0
0.0 60.1 30 .0 Frequency (MHz)
45.0
0 .0 0 .0
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Fig. 12 . A scan to measure analog bandwidth. The vertical axis is the ratio of the amplitude to the amplitude of the reference frequency, the horizontal axis is the frequency in MHz. scan is searched and the 3 dB points are found, interpolating if necessary. If an upper limit is not found, the highest frequency measured is cited as a lower limit to the analog bandwidth. Fig. 12 shows a scan for an eight-bit ADC. Since the purity of the sine wave is not a critical factor, filters are not needed for this test . If we are unable to monitor the input signal at the input pin to the ADC, the bandwidth measured here may include the effects of input amplifiers on the evaluation board. 3 .3 . Triangle waves
We get the following parameters from these tests: differential nonlinearity, random noise level, and word error 1/z rate . Using a symmetrical triangle wave we can make a second measurement of the differential nonlinearity, this time with an input which is changing with time. We use a triangle wave whose extremes go off scale at both the high and low end of the ADC range. In fact, we set it up so as to avoid using the top or bottom 5% of the wave because of possible nonlinearities in the waveform . Fig. 13 shows a record taken with such a waveform . We trigger the readout asynchronously with the waveform and make a histogram of the number of times each ADC code is hit. In an ideal case, all codes would be hit_equally. If C[k] is the number of hits for code k and C is the average of all C[k] then the DNL is calculated from
256.0
512 .0 memory odr
768 .0
1024 .C
Fig. 13 . The triangle waveform used to measure DNL. there are differences because the triangle DNL uses a varying input, hence time-dependent effects can influence the result. Random noise is defined as a nondeterministic output of the ADC . We measure it using a triangle wave with an amplitude of 10 counts peak-to-peak . The data trigger is synchronous with the triangle wave so that the record begins at the positive-going portion of the waveform . The frequency is adjusted so that one period subtends one record length of 1024 samples. Two events are taken and the following quantity is calculated: irise =
M
M-1 -1 (Yan-Ybn)2~
where Yan and Ybn are the noise record samples and M is the length of each record . The noise level, or, is then calculated from Q2=
~~
mse )
2
_z
+ (0 .866 mse)-4J
This is repeated 100 times and the average result is the noise level. Since this test measures the noise level over only a small range of input levels, we have an
DNLK[k] = ( C[k] - C)/C The interpretation of DNL is the same as for the DC test . Fig. 14 shows a plot of DNLK[k] from a triangle wave test . In an ideal ADC the distribution of DNLK[k] and its maximum absolute value (DNL), from this test should agree with those from the DC test . In reality,
Fig. 14. DNL vs ADC code from the triangle wave test for an eight-bit ADC.
H.B. Crawley et al. /Nucl. Instr. and Meth. i n Phys. Res A 342 (1994) 578-590
586
Settling time
256.0
192 .0
c 0
c
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Settling time =
0.0 969.0
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15 .
An event with a sparkle code .
79 .75V/us
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difference exceeded the qualified error level. The test continues until the required number of errors is found or a maximum number of samples is taken . The word error rate is then the number of qualified errors found, divided by the number of samples examined . A record of the data in the vicinity of the bad data is saved in a disk file for later analysis . 3.4. Step function
The step functions used in these tests are generated by the HP3314A function generator, which has a 10 to Over volt raw data
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Dato-Exlropolabor
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a
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993.750
Fig. 17 . Data from the short term settling time measurement. Note that only the portion of the data record near the step 1s shown. The arrows point to the values used to calculate the settling time .
00 00
Slew rate test Slew rate =
985.50 Memory adr
option to repeat the test automatically at a settable number of evenly spaced intervals. Usually we repeat it four times, once per quadrant . The word error rate is the probability of getting a wrong code after allowing for gain, offset, and linearity errors and after making a specified allowance for noise. In a flash ADC this kind of error is associated with "sparkle" codes, which have results nowhere near the expected value, usually due to an internal error in decoding the thermometer code generated by the comparators . An example is shown in Fig. 15 . Because this rate should be small, measuring it requires a large number of samples. We use a slowly varying large amplitude triangle wave with a slope such that the output changes by less than one count between samples . We choose a "qualified error level" which excludes all known sources of error (such as random noise) . Usually we use a qualified error level of more than two counts, but this can be changed by the operator and care must be taken to know the qualified error level in order for the test results to be meaningful . To calculate the word error rate, a sample is taken and the differences between successive samples are calculated . A running total is kept of the number of times this 256 .0
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Fig. 16. Data from the slew limit measurement Note that only the portion of the data record near the step 1s shown. Multiple data records with varying step sizes are superimposed and the two points used to calculate the slew rate are circled .
-1 0 0.0
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Fig. 18. (a) The waveform for the overvoltage test . (b) The residual from subtracting the extrapolated fit from the data in the overvoltage test .
H.B. Crawley et al. I Nucl. Instr. and Meth. to Phys . Res. A 342 (1994) 578-590
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90% rise time of less than 9 ns. At our highest sampling rates, this may marginally affect the results.
step, the slew limit reported is a lower bound on the true value.
3.4 .1 . Slew limit The slew limit is defined as the transition rate of change of the output for which an increased input step causes no change . We measure it using a step function initially having an amplitude of 10% of full scale. We take a data record and look at the maximum step size between two adjacent samples, then we repeat the process, raising the step amplitude each time . When we no longer see the maximum step size increase we have reached the limit and the result is converted into units of V/ws . Note that if the evaluation board includes a preamplifier before the ADC, as many of them do, the slew rate may be determined by the preamplifier rather than the ADC. Also, because of the gain of the preamplifier the slew rate at the ADC may be different from our measured slew rate at the input to the evaluation board. Fig. 16 shows the results of this test . In this plot the traces from successive scans of increasing amplitude are sumperimposed. If the maximum step size occurs on the scan with the largest
3.4 .2. Short term settling time The settling time is measured using a step function from approximately 10% to 90% of full scale, as shown in Fig. 17 . It is defined as the time from the first proximal point (10%) to the time the output has settled to within a specified tolerance of the final output for two consecutive bins . If the two points are in adjacent bins, the settling time quoted is an upper bound on the true value. The default value for the tolerance is one ideal code width. The final output value is determined by an average of 50 events . 3.5. Other inputs This section describes several tests which use unique inputs . 3.5.1 . Random noise In addition to the method described in section 3 .3, random noise can be measured as follows, provided the Date : 13-FEB-93 12 .05 .39 Operator : HBC,WTM Minimum Input Level : -1 .65 Maximum Input Level : 0 .05
FADC : Sample Output Sample Rate : 60 .0 MSPS No . Bits : 8
Sample Length : 1024 Program Version: 2 .2 -------------------------------------------------------------------------IEEE 1057 Tests Parameter
--------Gain
Offset Differential Nonlinearity Integral Nonlinearity Max Static Error Code Width RMS Monotonicity
Units
----------mV/count volts none '/, of f .s . my lsb none counts dBc none bits counts
Hysteresis Harmonic Distortion Signal-to-noise Ratio Effective Bits Normal Peak Error Fixed Error in Sample time ns Aperture Uncertainty ns ns Short-term Settling time Slew Limit Random Noise Word Error Rate Analog Bandwidth Abs . Overvoltage Recovery
volts/us counts none MHz ns
DC Level -------6 .4936
Sine
-1 .6403 0 .685 0 .100 1 .6543
0.210 Yes 1 .520
Triangle
Other
0 .560
50 .2 229 .6 7 .7 0 .966 0.115 < 0 .030
30 .1
0 .164 0 .000E+00
48 .3 79 .8 0 .000
0 .5
--------------------------------------------------------------------------
Fig. 19 . A sample summary page . The data values shown are illustrative only .
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fixed-pattern noise. The noise variance is estimated from
SAMPLE OUTPUT
1 2(M-1)
6
EI (
yan-ybn
where o2 is the noise variance, yan and ybn are the noise record samples, and M is the number of samples. If the noise variance is less than one lsb, this test is not valid. For some evaluation boards, terminating the input causes the ADC to go out of range so this test cannot be done. If this test is valid, it should produce the same result as the test in section 3.3 for an ideal ADC.
5
4
a 2
0
M
3.5.2. Absolute overuoltage recovery 0
20
40
60
80
This test uses a special input signal formed by putting a narrow square wave pulse on top of a high purity sine wave such that the pulse comes near the peak part of a sine cycle near the middle of the record . The pulse drives the ADC off scale, but stays within the safe limits for the device . Fig. 18a shows a typical waveform for this test . The goal is to measure how long it takes the device to recover from the spike. From the data record we fit a sine wave to the part of the data
100 120 140 Sample Rote (MSPS)
Fig. 20. Effective bits at selected input frequencies as a function of the sample rate . noise level is at least one lsb. We terminate the input to the evaluation board and take two data records. A bin-by-bin subtraction of the data records removes any
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0
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80 120 Sample Rate (MSPS)
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H. B. Crawley et al. /Nucl. Instr. and Meth . to Phys . Res. A 342 (1994) 578-590
z 0
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00 .75 0.5 0.25 0
0
40
"
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0
40
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Fig. 22 . Six test parameters as a function of sample rate .
before the spike and extrapolate the fit to the end of the record . The overvoltage recovery time is the time from the last full-scale point in the pulse to the first data point that is within the desired tolerance of the extrapolated fit. We use a tolerance of ±0 .95 counts . Fig. 18b shows the difference between the data and the extrapolated fit.
4. Output These tests produce a large amount of information, and it is difficult to present the results concisely. Our main attempt to do so is a summary page for each device and sample rate tested, an example of which is shown in Fig. 19 . The values shown in this example and in the figures to follow are illustrative only, they should not be taken as test results. As a final step we produce a series of plots showing effective bits as a function of sampling frequency and a series of plots showing various parameters from the summary page as a function of sample rate . A representative set of these is given in Figs . 20 through 22 .
Acknowledgements This work was supported in part by a Research Development and Exploratory Fund grant by the director of the Ames Laboratory and by the US Department of Energy under contract number W-7405-ENG-82, supported by the offices of High Energy and Nuclear Physics and Superconducting Super Collider . Reference to a company or to a product name does not imply approval or recommendation of the product by Iowa State University or the US Department of Energy to the exclusion of others that might be suitable .
References [1] Institute of Electrical and Electronics Engineers, IEEE Trial-Use Standard for Digitizing Waveform Recorders, IEEE Std. 1057 (1989). [21 Analog Devices, High Speed Design Seminar, Analog Devices, Inc. (1990) . [31 B.M . Gordon, and the Analogic Engineering Staff, The Analogic Data-Conversion Systems Digest, 4th ed ., Analogic Corporation (1990) .
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W . Kester, EDN (1990) 103 . D . Smith, Electronic Products (1990) 31 . A .W. Swager, EDN (1989) 93 . H .B . Crawley, R . McKay, W .T . Meyer, E.I . Rosenberg and W .D . Thomas, IEEE Trans . Nucl . Sci . NS-38 (1991) 102 . [8] H .B . Crawley, R. McKay, W .T . Meyer, E .I . Rosenberg and W .D . Thomas, IEEE Trans . Nucl . Sci . NS-39 (1992) 780 . [4] [5] [6] [7]
[9] H .B . Crawley, R . McKay, W .T. Meyer, E.I . Rosenberg and W.D . Thomas, IEEE Trans . Nucl . Sci. NS-40 (1993) 729 . [10] W .H. Press, B .P . Flannery, S .A . Teukolsky and W.T . Vetterling, Numerical Recipes (Cambridge University Press, Cambridge, 1986) .
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH Section A
A test bench for evaluating fast ADCs H.B. Crawley, R. McKay, W.T. Meyer *, E.I. Rosenberg, W.D. Thomas Department of Physics and Ames Laboratory, USDOE, Iowa State University, Ames, IA 50011, USA
(Received 1 April 1993)
This document describes a test bench and procedures used to evaluate the performance of analog-to-digital converters that operate in the range of 10 to 140 million samples per second .
1. Introduction With the availability of a wide selection of analogto-digital converters that can operate at speeds greater than 100 megasamples per second (MSPS), the user needing to select a device faces the difficult task of sorting the information from various manufacturers. In part this is because the manufacturers use different tests and definitions of parameters . To address this problem, we have built an ADC test bench that operates up to 140 megasamples per second, and performs a set of tests producing results under the same conditions for all devices. This allows the user to compare the characteristics of most interest for a particular application and thus to choose the device best fitting the need . Our motivation is to help select devices for use in high energy physics experiments at particle colliders. However, the tests are very general and the results should be useful to a wide range of users. Our starting point has been the proposed IEEE Standard 1057, "IEEE Trial-Use Standard for Digitizing Waveform Recorders", July 1989 [1]. However, that document is intended for commercial waveform recorders, not the actual ADC devices, so some adjustments to the procedures were necessary. We have kept the conventions and symbol definitions of that document . Other useful sources have been technical documents from manufacturers and articles in the trade literature [2,6]. A brief description of these tests has been published elsewhere [7], as have some of the first
* Corresponding author.
results [8,9]. This report gives a detailed description of the tests. Comparative results from devices we have tested will be in future publications . While we have been careful to maintain the quality of our tests, devices can have unavoidable differences that affect the results. Also, the results in a specific application may vary from our results due to external factors. Àll tests are performed at ambient room temperature with forced air cooling on the evaluation board. Finally, the reader is cautioned that we test only one or two samples of each device, the results are not an average over a large number of samples, nor do we test for long-term aging of devices. We intend to test most of the major commercially available devices, and users with special needs may contact us . 2. Test bench The test bench consists of four major parts : a clock/trigger module, an ADC evaluation board, a readout board to interface the evaluation board to our CAMAC-based data acquisition system, and a set of test signal sources . The test bench is controlled from a VAXStation 3100 computer, as shown in Fig. 1 . We use an IOTech SCSI/GPIB interface to create a GPIB connection to the signal sources and a Jorway model 73 crate controller to interface CAMAC to the computer's SCSI bus. In order to avoid false readings due to startup effects when an ADC goes from its quiescent state to its active state, we take two consecutive records and use the data from the second one. The operator has the option of turning off this feature in order to look for startup effects.
0168-9002/94/$07.00 © 1994 - Elsevier Science B.V . All rights reserved SSDI0168-9002(93)E1257-X
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n
._____________-__
_____________________________ Faraday Cage
M Mi mmo
CAMAC
;Evaluation Board/
'qumila
Crate Controller VAXStation 3100 SCSI
Readout Board
SCSI/GPIB GPIB
Universal Source
Function Generator
Signal Generator
Fig. l . The ADC test bench. We have enclosed the CAMAC crate in a Faraday cage in order to minimize pickup from external sources of radio frequency noise . 2.1 . Clock/ trigge r module
This is a CAMAC board with a set of four crystal oscillators operating at frequencies of 160, 200, 240 and 280 MHz. Circuits to divide by two, four, eight, and sixteen are used to produce output frequencies of 10, 15, 17 .5, 20, 25, 30, 40, 50, 60, 70, 80, 100, 120, and 140 MHz. Additionally, there is provision for an external clock. The operator chooses a specific frequency via CAMAC. To reduce noise, we turn off all the oscillators except the one needed . Connectors provide ECL and TTL outputs for three signals: the clock at
the selected frequency, an event trigger, and a pretrigger which comes one full clock cycle before the event trigger. A trigger is generated whenever the frequency selection circuitry is addressed via CAMAC. Thus, the controlling computer can select the clock frequency and generate event triggers . A special feature of the synchronization circuit is the ability to adjust under computer control the duty cycle of the clock waveform . We included this feature because some ADCs perform best with an asymmetric clock signal . Fig. 2 shows a block diagram of the clock/trigger board. 2.2. Evaluation board
This is usually supplied by the ADC manufacturer . Since manufacturers follow their own standards re-
SOFTWARE SELECT
05C OUT 30.
ECL
PRE-TRIG OUT
DRIVER
TRIG OUT
SYNCNRO CIRCUIT OSC OUT TTL DRIVER
Fig. 2. The clock/trigger board.
[
PRE-TRIG OUT TRIG OUT
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garding pinout and signals, we are prepared to accept a wide variety of evaluation boards . Generally, the evaluation board contains an input amplifier, the ADC itself, and various biasing and regulation circuits . Since this is where the most care must be taken to optimize ADC performance, we prefer to use a manufacturer's board, if available. When necessary, it is possible to build an evaluation board using a manufacturer-supplied circuit schematic or a custom design . We can provide guidelines to users needing to build evaluation boards . In order for certain important tests to be done, the evaluation board must have a DC coupling from the test signal to the ADC input pin. 2.3. Readout board
This is a CAMAC board which accepts the evaluation board as a daughter board mounted at a right angle to the readout board. To accommodate a range of evaluation boards it contains four different daughter board connectors, and the pinout of these can be reprogrammed using short wire-wrapped jumpers. The connectors have been chosen to match the evaluation boards known to be available at the time the board was designed . The readout board's primary purpose is to accept data from the evaluation board at the full readout speed - up to 140 MHz - and store it until it can be read out at the much slower CAMAC data speeds typically 1 MHz. For this purpose the board contains a 2K x 16-bit buffer made from 5 ns ECL memory chips. Two cable connectors provide inputs for the address register and for the memory strobe . Normally both of these are connected to the clock output from the clock trigger board, but separate inputs are provided to allow different cable delays . The only CAMAC function of the board is to read out the memory buffer either in single word mode or Q-stop DMA mode . Fig. 3 shows a block diagram of this board. 2 .4. Signal sources
For DC levels we use a Hewlett-Packard 3245A Universal Source unit, controlled via the GPIB bus . For DC levels, this unit gives 24 bit precision. For triangle and square wave signals we use a Hewlett-Packard model HP3314A function generator, also controlled via the GPIB bus. For sine wave inputs we use a Hewlett-Packard model HP8656B signal generator. Because some of the tests are very sensitive to the harmonic content of the sine wave, we use external passive filters purchased from TTE, Inc. to remove the higher harmonics. These filters provide a minimum of 40 dB of attenuation at
ANALOG INPUT
M
FLASH EVALUATION BOARD
SELECTED DIGITIZING FREOUENCY
r W
ô
sW 0
V]
IC
u
FLASH DATA
W
W
u
W
X
N
W i N
0
Y
WJ
~o
MEMORY DATA OUT
wô u1 u
~l7 r .. ocr r i Ur
Wa
E
E
Fig. 3. The readout board .
the first harmonic . Use of these filters limits our tests to 32 specific frequencies in the range between 0.182 and 58 .39 MHz for which we have filters. The operating computer controls the signal generator via the GPIB bus, but the filters are inserted manually . When a DC offset is required for a sine wave, a DC output from the function generator is added to the output of the sine wave generator after the filter . The function generator gives the DC offset and the signal generator superimposes the sine wave . This produces no observable degradation of the sine wave . For some devices, it is necessary to amplify the input signal either to prevent saturation or to permit the signal source to operate in its region of best performance. When this is necessary, a Phillips Scientific model 771 variable gain NIM amplifier is used . If filters are being used to purify a sine wave, they are placed after this amplifier. 3 . Tests
The tests are categorized according to the input signal . An event record consists of M (maximum value 2048) consecutive digitizations of the input signal . The sampling frequency is denoted by f,, N denotes the
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number of digitized bits and k denotes an ADC code value. 0 .50
3.1 . DC levels
We get the following seven parameters from the DC tests: gain, offset, differential nonlinearity, maximum static error, integral nonlinearity, monotonicity, and hysteresis . The first step in examining any ADC is to determine the DC voltage corresponding to the lower transition for each ADC code value. We denote the transition level between code k - 1 and code k by T[k]. The transition level is the input voltage that produces a 50-50 mix of the two codes in the event record, as determined by a linear interpolation between the measurements on either side of the transition . With the universal source set to produce DC levels, we start with an input level slightly lower than that needed to produce code 1. We take a record of 512 samples and note the percentages of codes 0 and 1 . The input level is increased until the percentage of code 0 is less than 50% and the interpolated value for T[1] is calculated . This step is repeated for each of the 2' - 1 code values, giving us the array of values T[k] . Once we have determined T[k] we compute the gain and offset by doing a least squares fit of a straight line to the data, assuming equal measurement errors for all codes. The results of the fit are the slope and intercept of the straight line. The gain (in mV per ADC count) is the measured slope and the offset (in V) is the intercept plus the width of the first code . (We add the width of the first code because the intercept from the fit represents the hypothetical lower edge of code 0, whereas the offset is defined to be the lower edge of code 1 .) Note that these definitions for gain and offset differ from those in IEEE Std. 1057 . With our definition, the gain is the same as the width of an ideal code (denoted by Q) . Fig. 4 shows the residuals from the fit. Transdion Residuals
10
5 4969
0
-1 0 00
00
640
1280 A/D code
1920
É
-6 .4969 256.0
Fig. 4. The residuals from a straight-line fit to the transition levels . The vertical axis is in units of least significant bits, and the horizontal axis is the ADC code value. Note that the right-hand scale shows the difference in mV .
00
-0 .50
0
00
640
128 .0 A/D code
192 .0
256 .0
Fig. 5. The differential nonlinearity vs ADC code for an eight-bit ADC. This measurement also gives us the differential nonlinearity and the integral nonlinearity. The differential nonlinearity is a measure of the width of each code normalized to the ideal width. The differential nonlinearity of code k is defined as : DNLK[k ] =(T[k+1 ] -T[k ] -Q)/Q, where Q is the ideal code width. A DNLK[k] value of 1 indicates that a code is twice as wide as the ideal, a value of 0 indicates it is as wide as the ideal and a value of -1 indicates that it is missing, i.e ., that it has zero width. The differential nonlinearity (DNL) for the ADC is defined to be the DNLKjk] with the highest absolute value, DNL= maxIDNLK[k]~ . an k
Fig. 5 shows a plot of DNLK[k] for an eight-bit ADC. We define the maximum static error to be the maximum of the absolute value of the deviation of T[k] from the straight-line fit. This is given in units of mV . We define the integral nonlinearity (INL) to be the maximum static error expressed as a percentage of full scale. Monotonicity is checked by setting the input voltage at the midpoint of each code value as determined from the value of (T[k + 1] - T[k])/2. The average value of the resulting data record is called A[k] . The array A[k] is scanned to check that A[k + 1] -A[k] has the same sign for all k. If so, the ADC is monotonic. If the ADC is not monotonic, we record the value of the worst deviation from monotonicity, in units of ADC counts . Hysteresis is checked by repeating the scan for A[ k ], this time starting with the top code and scanning downwards. This gives us the array A'[k]. The hysteresis parameter is defined as hysteresis = max I A' [ k] -A[ k ] . all k
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3.2. Sine waves
All of the tests in this section use sine wave inputs . As discussed earlier, the quality of many of the results depends strongly on the existence of a pure sine wave . To get as pure a wave as possible, we use external filters on the output of the signal generator, and this limits us to discrete values of sine wave frequencies . In addition, care must be taken that the data record does not contain an integral number of sine wave cycles .
â
10
3.2.1 . Single event
We get the following parameters from this test : signal-to-noise ratio, normalized peak error, and number of effective bits . One of the most important tests is to take a single record of a pure sine wave input and do a computer fit of a sine wave to the data . By subtracting the fit value from the data value we get a measurement of the noise level for a particular choice of sampling and sine wave frequencies . For this test we fix the sine frequency to be 1/54 .8 times the sample frequency. The choice of the ratio of 54 .8 was somewhat technical, but it involved avoiding an integral number of cycles in the data record, having enough cycles to allow a good computer fit, and having frequencies which could be shared with other tests, thus reducing the number of filter values needed . Fig. 6a shows the first 512 samples of an event record for an eight-bit ADC from this test and Fig. 6b shows the residuals from the sine wave fit . Once we have the residuals from the fit we calculate the average rms noise using the equation 1 rms noise = ~-
O
n1
M n=1
Yy
-
yn
1/2
' )2J
,
where the y,, are the data values within the record and the yn , are the fitted values to the data. The signal to noise ratio is given by SNR = rms signal/rms noise, where the rms signal is the fitted amplitude divided by the square root of two and the rms noise is given above. The SNR can be a function both of sampling frequency and input signal frequency. The sine wave fitting algorithm used is the four-parameter fit given in section 4.1 .3.2 of IEEE Std. 1057 . The peak error is defined to be the data sample with the largest difference in magnitude between the data and the fit. The normalized peak error is calculated from this by dividing by three times the standard deviation of the differences . A normalized peak error significantly greater than one indicates that differential nonlinearity is an important source of error. Another way to express noise is in terms of effective bits, a concept which has emerged as one of the most
Single Sine, Fd Resid 1 095MHz
64970
050
32485
00
00
-050
-10 00
É
-3 2485
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2560 memory adr
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Fig. 6. (a) The first 512 samples of an event record with a sine wave input. (b) The residuals from a sine wave fit for an eight-bit ADC. The left-hand vertical axis is in units of ADC counts, the right-hand vertical axis is in units of mV into the evaluation board, and the horizontal axis is the bin in the data sample . Only the fast 512 samples of the total record of 1024 are shown. useful parameters describing ADC performance. The fundamental idea is that even if the ADC returns, say, an eight-bit value, the significance of the result can be reduced because of noise so that fewer of the bits are significant. The effective bits parameter is one way of quantifying this measure . The number of effective bits, E, is defined as actual rms error
ideal rms quantization error )' where N is the number of digitized bits . The ideal quantization error is the ideal width of a code bin (Q) divided by the square root of 12 . The number of effective bits is, in general, a function of the sampling frequency and the frequency of the input sine wave . In our tests when we quote a single value for number of effective bits it will be the value at the Nyquist limit for the highest sampling frequency tested . More generally, we prefer to present plots of E as a function of frequency, as described next . 3 .2 .2 . Effective bits scan
To give more information, we created a test where we scan the number of effective bits, E, as a function of sine frequency for fixed sample frequency . In principle, the sine frequency can exceed the Nyquist limit
KB. Crawley et al. I Nucl. Instr. and Meth . in Phys. Res. A 342 (1994) 578-590 Eff. Bits scan
80
ADC codes around the middle of the range) and at the extremes of amplitude.
7 .0 60
3.2.3. Harmonic analysis
50 4 .0 30 2 .0 10 0 .0 00
100
200 300 40 .0 Frequency (MHz)
500
600
Fig. 7. The number of effective bits vs sine frequency in MHz for an eight-bit ADC running at 120 MSPS . and still give a valid result for E. The results are presented as a plot of E vs f,ne for a particular f, . Fig. 7 shows a typical plot . When we do an effective bits scan, we also keep track of the rms error associated with each ADC code . This lets us look for troublesome codes and for effects correlated with amplitude or slew rate . Fig. 8a shows such a plot for an eight-bit device with no problems. As an example of such a plot revealing problems, Fig. 8b shows the same device operated under stressed conditions (i .e ., a very high sample rate and a high input frequency) . Under these conditions we find evidence for higher rms values at both high slew rates (the 10
S;agle Sine, RMS vs ADC 1 .095MHz
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We get the following parameter from this test : total harmonic distortion . Harmonic distortion is the presence of unwanted Fourier components at frequencies which are a multiple of the applied sine wave frequency. To measure the total harmonic distortion we take a record of a pure sine wave and perform a discrete Fourier transform (DFT) to measure the strength of the harmonics in the observed record . The subject of DFTs is a complicated one which has been discussed in many places, and our primary reference has been the book Numerical Recipes by Press et al . [10] . In order to reduce aliasing caused by abrupt changes at the ends of the data record, it is customary to weight the raw data with a window function, which is a function that goes smoothly from zero at the extremes of the window to a value of 1 .0 at the center . Many such functions exist, and we have chosen a so-called "four term Blackman-Harris function". To calculate the power spectrum, we use data records of 1024 values which we divide into three half-overlapping windows of 512 values each . We calculate the DFT using the subroutine RPA from the CERN software library, which performs all calculations in double precision and we have verified its accuracy on computer generated sine waves to a level of 14 bits . By choosing a sine frequency which is 1/13 .7 times the sampling frequency we set the scale of the frequency plot to have the right range for our purposes . In order to reduce the background level, we take 25 records and average the results. The power spectrum is calculated by adding in quadrature the real and imaginary parts of the DFT. We show a sample plot of the power spectrum in Fig. 9. In addition to a strong peak at the fundamental
00
E
ADC Code
Fig . 8. (a) The rms error associated with each ADC code value for an eight-bit ADC at 60 MSPS . (b) The same device but with the ADC running at a very high sample rate (120 MSPS) and with a high input frequency.
Fig. 9. The power spectrum for an eight-bit ADC. The vertical axis is the logarithm of the power in arbitrary units and the horizontal axis is frequency in MHz.
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frequency we can see small peaks at harmonic frequencies . In addition, there is a background level which is set by the quantization error of the ADC. From the power spectrum we calculate the total harmonic distortion (THD) as follows. From Fig. 9 we see that the peak is contained in fewer than nine bins . (This width is mainly determined by the window function and the relatively narrow peak was one reason we chose to use the Blackman-Harris function .) We calculate the power squared in the fundamental by adding the square of the power in each bin of the peak . Similarly we calculate the power squared in the first five harmonics, also using nine bins per harmonic . The THD is defined as THD = 10 log,, ( fundamental/harmonics~ . We also show in the figure the separate values in arbitrary units for the fundamental and the first three harmonics. The rms value shown in the figure is the root-mean-square deviation of the THD values from the 25 scans. It is a measure of the reproducibility of the results. 3 .2.4. Multiple euent scan
We get the following parameters from this test : fixed error in sample time and aperture uncertainty . In this test we take ten or more scans using a sine wave that is 4/13 .7 times the sample rate, fit a sine wave to each scan, and compute and save the residuals for each scan separately . The residuals are converted to a time difference by dividing by the slope of the fitted curve for that point. To avoid dividing by small numbers, data points within ± 15° of the sine peak are removed. We denote the nth time difference (n = 1 . . . M) of the ith scan (i = 1 . . . 10) by din- We then calculate the bin-by-bin average of the d in : 1
m
Dn = -Y_ d in , m 1-1
0 .10
0
00
-0 .10 , 0 0
128.0
2560
3840
5120
Memory adr
Fig. 10 . 512 values of the array D from the test to measure fixed error in sample time . The vertical axis is in us and the horizontal axis is the bin number within the data record .
Fig. 11 . A histogram of the average residuals from the multiple event scan . where m < 10 is the number of scans with the nth point outside of the 15° cut. The average of all the D is D. Fig. 10 shows a plot of D for an eight-bit ADC. The fixed error in sample time is the maximum value of I D - D I . It is expressed in ns and represents a nonrandom error in the instant of sampling . This may be due to circumstances internal to the ADC or to external factors like noise on the ADC clock signal . The aperture uncertainty, or timing jitter, is the standard deviation of the sample instant in time . An upper bound on this value is the standard deviation of the din distribution . This is an upper bound because it can include noise from sources other than timing jitter . Fig. 11 shows a histogram of the din and the rms value of this distribution is used for the upper bound on the aperture uncertainty . 3.2.5 . Analog bandwidth scan
We get the following parameters from this test : minimum and maximum analog bandwidth. Because it is in part an analog device, an ADC has an analog bandwidth, defined as the input frequency range over which the gain of the device is within ±3 dB of its value at a specified reference frequency. The gain is defined to be the ratio of the output signal (in ADC counts) to the input signal (in mV). If there are both upper and lower 3 dB cutoffs, both numbers are given. If only one number is given, it is the upper limit and the lower limit does not exist because the gain stayed in the allowed range to the lowest frequency measured . We measure the analog bandwidth using a sine wave input centered at midrange on the ADC and covering the range from 10% to 90%. At each frequency the input to the ADC is monitored with an oscilloscope to be sure the input amplitude is held constant . Variations with frequency, both in the output of the signal generator and due to bandwidth effects of input amplifiers on the evaluation boards, make this step necessary. The array of values resulting from this
H.B. Crawley et al. I Nucl. Instr. and Meth . in Phys. Res. A 342 (1994) 578-590 Bandwidth Plot
1 .20
v
0 .80
0
0.60
v â E a
192 .0
û
va
0 .40 0 .20 0 .0 0 .0
Triangle DNL data
256 .0
1 .0
585
Lower 3 dB limit : Upper 3 dB limit: 15.0
128 .0
64 .0
0.0 60.1 30 .0 Frequency (MHz)
45.0
0 .0 0 .0
60 .0
Fig. 12 . A scan to measure analog bandwidth. The vertical axis is the ratio of the amplitude to the amplitude of the reference frequency, the horizontal axis is the frequency in MHz. scan is searched and the 3 dB points are found, interpolating if necessary. If an upper limit is not found, the highest frequency measured is cited as a lower limit to the analog bandwidth. Fig. 12 shows a scan for an eight-bit ADC. Since the purity of the sine wave is not a critical factor, filters are not needed for this test . If we are unable to monitor the input signal at the input pin to the ADC, the bandwidth measured here may include the effects of input amplifiers on the evaluation board. 3 .3 . Triangle waves
We get the following parameters from these tests: differential nonlinearity, random noise level, and word error 1/z rate . Using a symmetrical triangle wave we can make a second measurement of the differential nonlinearity, this time with an input which is changing with time. We use a triangle wave whose extremes go off scale at both the high and low end of the ADC range. In fact, we set it up so as to avoid using the top or bottom 5% of the wave because of possible nonlinearities in the waveform . Fig. 13 shows a record taken with such a waveform . We trigger the readout asynchronously with the waveform and make a histogram of the number of times each ADC code is hit. In an ideal case, all codes would be hit_equally. If C[k] is the number of hits for code k and C is the average of all C[k] then the DNL is calculated from
256.0
512 .0 memory odr
768 .0
1024 .C
Fig. 13 . The triangle waveform used to measure DNL. there are differences because the triangle DNL uses a varying input, hence time-dependent effects can influence the result. Random noise is defined as a nondeterministic output of the ADC . We measure it using a triangle wave with an amplitude of 10 counts peak-to-peak . The data trigger is synchronous with the triangle wave so that the record begins at the positive-going portion of the waveform . The frequency is adjusted so that one period subtends one record length of 1024 samples. Two events are taken and the following quantity is calculated: irise =
M
M-1 -1 (Yan-Ybn)2~
where Yan and Ybn are the noise record samples and M is the length of each record . The noise level, or, is then calculated from Q2=
~~
mse )
2
_z
+ (0 .866 mse)-4J
This is repeated 100 times and the average result is the noise level. Since this test measures the noise level over only a small range of input levels, we have an
DNLK[k] = ( C[k] - C)/C The interpretation of DNL is the same as for the DC test . Fig. 14 shows a plot of DNLK[k] from a triangle wave test . In an ideal ADC the distribution of DNLK[k] and its maximum absolute value (DNL), from this test should agree with those from the DC test . In reality,
Fig. 14. DNL vs ADC code from the triangle wave test for an eight-bit ADC.
H.B. Crawley et al. /Nucl. Instr. and Meth. i n Phys. Res A 342 (1994) 578-590
586
Settling time
256.0
192 .0
c 0
c
u 0
û
Q
128.0
Q 64 .0
Settling time =
0.0 969.0
Fig.
15 .
An event with a sparkle code .
79 .75V/us
1002 .0
difference exceeded the qualified error level. The test continues until the required number of errors is found or a maximum number of samples is taken . The word error rate is then the number of qualified errors found, divided by the number of samples examined . A record of the data in the vicinity of the bad data is saved in a disk file for later analysis . 3.4. Step function
The step functions used in these tests are generated by the HP3314A function generator, which has a 10 to Over volt raw data
2560
1920
1280
64 0
2560
5120
7680
10240
Dato-Exlropolabor
301
192.0
a
16 ns
993.750
Fig. 17 . Data from the short term settling time measurement. Note that only the portion of the data record near the step 1s shown. The arrows point to the values used to calculate the settling time .
00 00
Slew rate test Slew rate =
985.50 Memory adr
option to repeat the test automatically at a settable number of evenly spaced intervals. Usually we repeat it four times, once per quadrant . The word error rate is the probability of getting a wrong code after allowing for gain, offset, and linearity errors and after making a specified allowance for noise. In a flash ADC this kind of error is associated with "sparkle" codes, which have results nowhere near the expected value, usually due to an internal error in decoding the thermometer code generated by the comparators . An example is shown in Fig. 15 . Because this rate should be small, measuring it requires a large number of samples. We use a slowly varying large amplitude triangle wave with a slope such that the output changes by less than one count between samples . We choose a "qualified error level" which excludes all known sources of error (such as random noise) . Usually we use a qualified error level of more than two counts, but this can be changed by the operator and care must be taken to know the qualified error level in order for the test results to be meaningful . To calculate the word error rate, a sample is taken and the differences between successive samples are calculated . A running total is kept of the number of times this 256 .0
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00
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Fig. 16. Data from the slew limit measurement Note that only the portion of the data record near the step 1s shown. Multiple data records with varying step sizes are superimposed and the two points used to calculate the slew rate are circled .
-1 0 0.0
256.0
512.0 memory adr
7680
-64944 10240
Fig. 18. (a) The waveform for the overvoltage test . (b) The residual from subtracting the extrapolated fit from the data in the overvoltage test .
H.B. Crawley et al. I Nucl. Instr. and Meth. to Phys . Res. A 342 (1994) 578-590
587
90% rise time of less than 9 ns. At our highest sampling rates, this may marginally affect the results.
step, the slew limit reported is a lower bound on the true value.
3.4 .1 . Slew limit The slew limit is defined as the transition rate of change of the output for which an increased input step causes no change . We measure it using a step function initially having an amplitude of 10% of full scale. We take a data record and look at the maximum step size between two adjacent samples, then we repeat the process, raising the step amplitude each time . When we no longer see the maximum step size increase we have reached the limit and the result is converted into units of V/ws . Note that if the evaluation board includes a preamplifier before the ADC, as many of them do, the slew rate may be determined by the preamplifier rather than the ADC. Also, because of the gain of the preamplifier the slew rate at the ADC may be different from our measured slew rate at the input to the evaluation board. Fig. 16 shows the results of this test . In this plot the traces from successive scans of increasing amplitude are sumperimposed. If the maximum step size occurs on the scan with the largest
3.4 .2. Short term settling time The settling time is measured using a step function from approximately 10% to 90% of full scale, as shown in Fig. 17 . It is defined as the time from the first proximal point (10%) to the time the output has settled to within a specified tolerance of the final output for two consecutive bins . If the two points are in adjacent bins, the settling time quoted is an upper bound on the true value. The default value for the tolerance is one ideal code width. The final output value is determined by an average of 50 events . 3.5. Other inputs This section describes several tests which use unique inputs . 3.5.1 . Random noise In addition to the method described in section 3 .3, random noise can be measured as follows, provided the Date : 13-FEB-93 12 .05 .39 Operator : HBC,WTM Minimum Input Level : -1 .65 Maximum Input Level : 0 .05
FADC : Sample Output Sample Rate : 60 .0 MSPS No . Bits : 8
Sample Length : 1024 Program Version: 2 .2 -------------------------------------------------------------------------IEEE 1057 Tests Parameter
--------Gain
Offset Differential Nonlinearity Integral Nonlinearity Max Static Error Code Width RMS Monotonicity
Units
----------mV/count volts none '/, of f .s . my lsb none counts dBc none bits counts
Hysteresis Harmonic Distortion Signal-to-noise Ratio Effective Bits Normal Peak Error Fixed Error in Sample time ns Aperture Uncertainty ns ns Short-term Settling time Slew Limit Random Noise Word Error Rate Analog Bandwidth Abs . Overvoltage Recovery
volts/us counts none MHz ns
DC Level -------6 .4936
Sine
-1 .6403 0 .685 0 .100 1 .6543
0.210 Yes 1 .520
Triangle
Other
0 .560
50 .2 229 .6 7 .7 0 .966 0.115 < 0 .030
30 .1
0 .164 0 .000E+00
48 .3 79 .8 0 .000
0 .5
--------------------------------------------------------------------------
Fig. 19 . A sample summary page . The data values shown are illustrative only .
588
H.B. Crawley et al. INucl. Instr. and Meth. in Phys . Res. A 342 (1994) 578-590
fixed-pattern noise. The noise variance is estimated from
SAMPLE OUTPUT
1 2(M-1)
6
EI (
yan-ybn
where o2 is the noise variance, yan and ybn are the noise record samples, and M is the number of samples. If the noise variance is less than one lsb, this test is not valid. For some evaluation boards, terminating the input causes the ADC to go out of range so this test cannot be done. If this test is valid, it should produce the same result as the test in section 3.3 for an ideal ADC.
5
4
a 2
0
M
3.5.2. Absolute overuoltage recovery 0
20
40
60
80
This test uses a special input signal formed by putting a narrow square wave pulse on top of a high purity sine wave such that the pulse comes near the peak part of a sine cycle near the middle of the record . The pulse drives the ADC off scale, but stays within the safe limits for the device . Fig. 18a shows a typical waveform for this test . The goal is to measure how long it takes the device to recover from the spike. From the data record we fit a sine wave to the part of the data
100 120 140 Sample Rote (MSPS)
Fig. 20. Effective bits at selected input frequencies as a function of the sample rate . noise level is at least one lsb. We terminate the input to the evaluation board and take two data records. A bin-by-bin subtraction of the data records removes any
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Fig. 21 . Four test parameters as a function of sample rate .
H. B. Crawley et al. /Nucl. Instr. and Meth . to Phys . Res. A 342 (1994) 578-590
z 0
589
1
00 .75 0.5 0.25 0
0
40
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0
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80 120 Sample Rate (MSPS)
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Fig. 22 . Six test parameters as a function of sample rate .
before the spike and extrapolate the fit to the end of the record . The overvoltage recovery time is the time from the last full-scale point in the pulse to the first data point that is within the desired tolerance of the extrapolated fit. We use a tolerance of ±0 .95 counts . Fig. 18b shows the difference between the data and the extrapolated fit.
4. Output These tests produce a large amount of information, and it is difficult to present the results concisely. Our main attempt to do so is a summary page for each device and sample rate tested, an example of which is shown in Fig. 19 . The values shown in this example and in the figures to follow are illustrative only, they should not be taken as test results. As a final step we produce a series of plots showing effective bits as a function of sampling frequency and a series of plots showing various parameters from the summary page as a function of sample rate . A representative set of these is given in Figs . 20 through 22 .
Acknowledgements This work was supported in part by a Research Development and Exploratory Fund grant by the director of the Ames Laboratory and by the US Department of Energy under contract number W-7405-ENG-82, supported by the offices of High Energy and Nuclear Physics and Superconducting Super Collider . Reference to a company or to a product name does not imply approval or recommendation of the product by Iowa State University or the US Department of Energy to the exclusion of others that might be suitable .
References [1] Institute of Electrical and Electronics Engineers, IEEE Trial-Use Standard for Digitizing Waveform Recorders, IEEE Std. 1057 (1989). [21 Analog Devices, High Speed Design Seminar, Analog Devices, Inc. (1990) . [31 B.M . Gordon, and the Analogic Engineering Staff, The Analogic Data-Conversion Systems Digest, 4th ed ., Analogic Corporation (1990) .
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H.B Crawley et al. /Nucl. Instr. and Meth. i n Phys . Res . A 342 (1994) 578-590
W . Kester, EDN (1990) 103 . D . Smith, Electronic Products (1990) 31 . A .W. Swager, EDN (1989) 93 . H .B . Crawley, R . McKay, W .T . Meyer, E.I . Rosenberg and W .D . Thomas, IEEE Trans . Nucl . Sci . NS-38 (1991) 102 . [8] H .B . Crawley, R. McKay, W .T . Meyer, E .I . Rosenberg and W .D . Thomas, IEEE Trans . Nucl . Sci . NS-39 (1992) 780 . [4] [5] [6] [7]
[9] H .B . Crawley, R . McKay, W .T. Meyer, E.I . Rosenberg and W.D . Thomas, IEEE Trans . Nucl . Sci. NS-40 (1993) 729 . [10] W .H. Press, B .P . Flannery, S .A . Teukolsky and W.T . Vetterling, Numerical Recipes (Cambridge University Press, Cambridge, 1986) .