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Accelerated life testing of flexible printed circuits Part II—Failure modes in flexible printed circuits coated with UV-cured resins
World Abstracts on Microelectronics and Reliability advanced metallizations for use on semiconductor devices is presented. Methods for the deposition of thin films and the properties of these films are described and the application of these metallizations to actual devices is discussed. In addition, since beryllium can be a toxic material, precautions necessary for its use arc detailed.
Accelerated life testing of flexible printed circuits. Part i - - T e s t program and typical results. P. J. BODDY, R. H. DELANEY, J. N. LAHTL 1;,. 1-'. LANDRY and R. C. RESTRJCK. Part ll--Failure modes in flexible printed circuits coated with UV-cured resins. R. tl. DELANEY and J. N. LAHTI. IEEE Reliab. Phys. 108 (1976). Part I of this paper describes a facility which has recently been developed to conduct accelerated life tests on printed wiring products. Procedures developed for the evaluation of flexible printed circnits are outlined, and a representative set of life test data is reviewed to illustrate the kinds of information obtainable with this facility. In conducting accelerated life tests on finelinc flexible printed circuits coated with UV-cured resins, failures have been observed to occur in virtually every part of the circuit structure. In Part If, the various failure modes are described and are categorized according to the principal structural element involved (e.g., covercoat, substrate, ctc.). In many cases environmental domains have bcen identified, within which there is a clear predominance of a specific failure mode. Methods for evaluating plated-through-hole reliability. M. A. OIr.y. IEEE Reliab. Phys. 129 (1976). The principal thermo-mechanical failure modes of a plated-through-hole structure are described and the major factors contributing to such failures are discussed in mechanistic terms. This leads to the development of an improved methodology for evaluating the reliability of plated-through-holes.
A simple nmdel for the thermo-mechaincal deformations of plated-through-holes in multilayer printed wiring boards. M. A. Omr< IEEE Reliab. Phys. 121 (1976). A simple model is described which provides a basic understanding of the relationship between the thermo-mechanical deformations of a plated-through-hole and the consequent principal failure modes of the PTtt structure. The model facilitates the design of effective reliability test programs and the interpretation of experimental results. Measurement of thermo-mechanical strains in platedthrongh-hules. H. H. AMM.*NN and R. W. JOCIIER. I E E E Reliah. Phys. 118 (1976). Knowledge of thermo-mechanical strains in plated-throt,gh-holcs, complemeted by an understading of failure mechanics, yields valuable information about the effect of materials, design and process paramctcrs on product reliability potential. A technique is described for measuring central barrel strata and surface land rotation for plated-through-holes during thermal transients.
The effect of impurities on the corrosion of aluminum metallization. W. M. PAUl,SON and R. P. LORIGA.X. Proc. IEEE Reliab. Phys. 42 (1976). Surface impurities are an important factor that affects the reliability of semiconductor devices exposed to THB environments. Aluminum metallized specimens were intentionally contaminated with controlled mnounts of Na, K and CI. Corrosion was observed at both the anode and cathode following THB tests. The corrosion rate wax proportional to the log of the impurity concentration. A model is proposed to explain the observed corrosion processes.
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An evaluation of silicon damage resulting from ultrasonic wire bonding. VERN H. WINCItYLL If. IEEE Reliab. Phys. 98 (1976). Ultrasonic wire bonding is a dynamic process which has been found to introduce material damage to improperly protected silicon. Damage is detected through the generation of steam oxidation induced stacking faults in the silicon after the metal and oxides have been removed. Silicon of both (100) and (111) orientations were evaluated with faulting being found predominately on those (111) planes whose lines of intersection with the surface were most nearly perpendicular to the applied direction of ultrasonic motion. Stacking faults predominate at the outer periphery of the bond. In addition to a correlation between the direction of ultrasonic motion and the fault planes observed, different fault planes operate at the toc and hecl of the bond. No stacking faults are induced for normal ultrasonic bonding parameters and standard thicknesses of metallization (10 KA) using 2-mil bonding wire. This method of analysis provides a means for evaluating changes in materials and processing to improve bond reliability.
Hot electron induced degradation of N-channel IGFETs. S. A. ABBAS and R. C. DOKERTY. Proc. IEEE Reliab. Phys. 38 (1976). Under certain bias conditions, electrons flowing through the channel of an n-channel IGFET can be injected into the gate insulator. A fraction of the injected electrons is trapped in the dielectric, producing a shift in device operating characteristics. This phenomenon is minimized by proper device design. A model is described to predict long-term shifts from accelerated stress test data.
Microsurgery as a tool in the analysis of L.S.I.A. LORO. Proc. IEEE Reliab. Phys. 33 (1976). The ability to open or bridge selected conductors on an L.S.1. chip opens up a wide range of analytical opportunities in the field of failure analysis, design debugging, and commercial device analysis. Simple methods o1' severing, repairing and interconnecting condnctors in high density L.S.1. silicon chips are described. The design details of a simple precision tool serving the dual functions of microsurgery and subsequent electrical probing of components is discussed. Results obtained with the methods described on various commercial and custom L.S.I. circuits arc presented.
A CMOS/SOS Reliability Study. JACK S. SMrrrt and LT. DOXALD D. TALADA. Proc. 1EEE Reliab. Phys. 23 (1976). With over 100,000 hours of reliability testing of complementary metal oxide semiconductor devices built on sapphire substrates, a pattern of failure mechanisms has emerged. Not surprisingly, the well known gate oxide charge instabilities and gate oxide shorts commonly found in CMOS are also present in this latest technology innovation. The sapphire technology has added to these failure mechanisms several problems related to the input protective network and the so called back-channel leakage current stemming from the silicon-sapphire interface.
ReliabiliD' implications of hot electron generation and parasitic bipolar action in an IGFEI device. S. A. ARBAS and E. E. DAVID,CON.Proc. IEEE Reliab. Phys. 18 (1976). Potential reliability effects due to a profusion of hot electrons generated by a parasitic bipolar have been identified in short channel N-type IGFET devices. An explanation of the phenomenon as well as a mathematical and circuit model for the effects are presented. Results frorrS the model will be used to predict changes in device characteristics with time.
Accelerated life testing of flexible printed circuits. Part i - - T e s t program and typical results. P. J. BODDY, R. H. DELANEY, J. N. LAHTL 1;,. 1-'. LANDRY and R. C. RESTRJCK. Part ll--Failure modes in flexible printed circuits coated with UV-cured resins. R. tl. DELANEY and J. N. LAHTI. IEEE Reliab. Phys. 108 (1976). Part I of this paper describes a facility which has recently been developed to conduct accelerated life tests on printed wiring products. Procedures developed for the evaluation of flexible printed circnits are outlined, and a representative set of life test data is reviewed to illustrate the kinds of information obtainable with this facility. In conducting accelerated life tests on finelinc flexible printed circuits coated with UV-cured resins, failures have been observed to occur in virtually every part of the circuit structure. In Part If, the various failure modes are described and are categorized according to the principal structural element involved (e.g., covercoat, substrate, ctc.). In many cases environmental domains have bcen identified, within which there is a clear predominance of a specific failure mode. Methods for evaluating plated-through-hole reliability. M. A. OIr.y. IEEE Reliab. Phys. 129 (1976). The principal thermo-mechanical failure modes of a plated-through-hole structure are described and the major factors contributing to such failures are discussed in mechanistic terms. This leads to the development of an improved methodology for evaluating the reliability of plated-through-holes.
A simple nmdel for the thermo-mechaincal deformations of plated-through-holes in multilayer printed wiring boards. M. A. Omr< IEEE Reliab. Phys. 121 (1976). A simple model is described which provides a basic understanding of the relationship between the thermo-mechanical deformations of a plated-through-hole and the consequent principal failure modes of the PTtt structure. The model facilitates the design of effective reliability test programs and the interpretation of experimental results. Measurement of thermo-mechanical strains in platedthrongh-hules. H. H. AMM.*NN and R. W. JOCIIER. I E E E Reliah. Phys. 118 (1976). Knowledge of thermo-mechanical strains in plated-throt,gh-holcs, complemeted by an understading of failure mechanics, yields valuable information about the effect of materials, design and process paramctcrs on product reliability potential. A technique is described for measuring central barrel strata and surface land rotation for plated-through-holes during thermal transients.
The effect of impurities on the corrosion of aluminum metallization. W. M. PAUl,SON and R. P. LORIGA.X. Proc. IEEE Reliab. Phys. 42 (1976). Surface impurities are an important factor that affects the reliability of semiconductor devices exposed to THB environments. Aluminum metallized specimens were intentionally contaminated with controlled mnounts of Na, K and CI. Corrosion was observed at both the anode and cathode following THB tests. The corrosion rate wax proportional to the log of the impurity concentration. A model is proposed to explain the observed corrosion processes.
15
An evaluation of silicon damage resulting from ultrasonic wire bonding. VERN H. WINCItYLL If. IEEE Reliab. Phys. 98 (1976). Ultrasonic wire bonding is a dynamic process which has been found to introduce material damage to improperly protected silicon. Damage is detected through the generation of steam oxidation induced stacking faults in the silicon after the metal and oxides have been removed. Silicon of both (100) and (111) orientations were evaluated with faulting being found predominately on those (111) planes whose lines of intersection with the surface were most nearly perpendicular to the applied direction of ultrasonic motion. Stacking faults predominate at the outer periphery of the bond. In addition to a correlation between the direction of ultrasonic motion and the fault planes observed, different fault planes operate at the toc and hecl of the bond. No stacking faults are induced for normal ultrasonic bonding parameters and standard thicknesses of metallization (10 KA) using 2-mil bonding wire. This method of analysis provides a means for evaluating changes in materials and processing to improve bond reliability.
Hot electron induced degradation of N-channel IGFETs. S. A. ABBAS and R. C. DOKERTY. Proc. IEEE Reliab. Phys. 38 (1976). Under certain bias conditions, electrons flowing through the channel of an n-channel IGFET can be injected into the gate insulator. A fraction of the injected electrons is trapped in the dielectric, producing a shift in device operating characteristics. This phenomenon is minimized by proper device design. A model is described to predict long-term shifts from accelerated stress test data.
Microsurgery as a tool in the analysis of L.S.I.A. LORO. Proc. IEEE Reliab. Phys. 33 (1976). The ability to open or bridge selected conductors on an L.S.1. chip opens up a wide range of analytical opportunities in the field of failure analysis, design debugging, and commercial device analysis. Simple methods o1' severing, repairing and interconnecting condnctors in high density L.S.1. silicon chips are described. The design details of a simple precision tool serving the dual functions of microsurgery and subsequent electrical probing of components is discussed. Results obtained with the methods described on various commercial and custom L.S.I. circuits arc presented.
A CMOS/SOS Reliability Study. JACK S. SMrrrt and LT. DOXALD D. TALADA. Proc. 1EEE Reliab. Phys. 23 (1976). With over 100,000 hours of reliability testing of complementary metal oxide semiconductor devices built on sapphire substrates, a pattern of failure mechanisms has emerged. Not surprisingly, the well known gate oxide charge instabilities and gate oxide shorts commonly found in CMOS are also present in this latest technology innovation. The sapphire technology has added to these failure mechanisms several problems related to the input protective network and the so called back-channel leakage current stemming from the silicon-sapphire interface.
ReliabiliD' implications of hot electron generation and parasitic bipolar action in an IGFEI device. S. A. ARBAS and E. E. DAVID,CON.Proc. IEEE Reliab. Phys. 18 (1976). Potential reliability effects due to a profusion of hot electrons generated by a parasitic bipolar have been identified in short channel N-type IGFET devices. An explanation of the phenomenon as well as a mathematical and circuit model for the effects are presented. Results frorrS the model will be used to predict changes in device characteristics with time.