Analysis of frequency and amplitude in CMOS differential ring oscillators

Author's Accepted Manuscript

Analysis of Frequency and Amplitude in CMOS Differential Ring Oscillators Hojat Ghonoodi, Hossein Mohammad Gholami

Miar-Naimi,

www.elsevier.com/locate/vlsi

PII: DOI: Reference:

S0167-9260(15)00083-8 http://dx.doi.org/10.1016/j.vlsi.2015.07.004 VLSI1136

To appear in:

INTEGRATION, the VLSI journal

Received date: 31 October 2014 Revised date: 10 July 2015 Accepted date: 13 July 2015 Cite this article as: Hojat Ghonoodi, Hossein Miar-Naimi, Mohammad Gholami , Analysis of Frequency and Amplitude in CMOS Differential Ring Oscillators, INTEGRATION, the VLSI journal, http://dx.doi.org/10.1016/j.vlsi.2015.07.004 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting galley proof before it is published in its final citable form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

Hojat Ghonoodia, *, Hossein Miar-Naimia, 1 and Mohammad Gholamib, 2

Analysis of Frequency and Amplitude in CMOS Differential Ring Oscillators Abstract In this paper, a new method for computing the amplitude and frequency of differential ring oscillators (ROs) is proposed. The analysis is performed in two separate parts. In the first of these, equations are derived with the assumption of a sinusoidal waveform of outputs, while in the other, the outputs are assumed to be exponential. It is shown that the derived equations for frequency and amplitude are sufficiently exact. In addition, conditions in which sinusoidal and exponential output occur are thoroughly discussed. In the instances in which the results did not satisfy the necessary conditions for sinusoidal output, the output is assumed to be exponential. Moreover, the related analytical equations are written, and the new expressions for frequency and amplitude of ROs are derived. Analytical results are confirmed by simulation results, using the Taiwan a

Electrical Engineering Department, Babol University of Technology, Babol, Iran b

Faculty of Engineering & Technology, University of Mazandaran, Babolsar, Iran

Semiconductor Manufacturing Company 0.18µm technology model. The simulation results indicate the high level of accuracy of the proposed model. Index Terms— Equations, ring oscillators, CMOS, RF circuit.

I. INTRODUCTION

O

scillators are key building blocks in many wired and wireless communication systems. In particular, they are fundamental parts in phase-locked loops (PLLs) and clock and data recovery (CDR) [1]–[12]. Ring oscillators (ROs) are used in these applications because of their low power consumption, large tuning range, and lower die space area. Although ROs are in widespread usage, their design, analysis, and modeling still present a variety of challenges. For example, the design of an RO involves numerous tradeoffs in terms of speed, power, area, and phase noise [13]-[14]. In order to make improved decisions regarding these tradeoffs, an accurate method to determine the oscillation frequency and amplitude of the RO is required. The use of a numerical simulator, such as HSPICE, may be an accurate method of determining oscillation frequency and amplitude, but it does not provide a clear procedure to allow the designer to ascertain how to optimize circuit parameters. The designer can find some basic trends by running several different simulations, but, even then, the impact of modified variables may not be apparent. An RO consists of a number of delay stages in a feedback loop; a single-ended RO requires at least three inverters in its loop to oscillate. This chain of delay stages is shown in Fig. 1. According to the Barkhausen criterion, the ring must provide an open loop phase shift equal to 2π at the oscillation frequency to achieve oscillation. The π phase shift is provided by a DC level inversion. Therefore, each delay stage must provide a phase shift of π/N, where N is the number of delay stages. This means that for an oscillator with single-ended inverter delay stages, an odd number of stages is necessary for the DC level inversion. If differential delay stages are used, N can be an even number. In this case, the positive output of the last stage should be connected to the negative input of the first stage and vice versa. The use of differential inverter delay stages has advantages over the use of single-ended delay stages, primarily because there is little distortion in the outputs [15]. This paper will focus on differential delay stages, such as the one shown in Fig. 3. This paper is organized as follows. Section II investigates the equations related to oscillation frequency in ROs, which have been derived in previous works. In Section III, a method to calculate oscillation frequency and voltage swing is proposed. In this section, equations will be derived in two cases of sinusoidal and exponential output to ensure greater precision. Different ROs are simulated to evaluate the results of the analysis, and these results are discussed and compared to those of other works in Section IV. Section V presents our conclusions. *

Corresponding author. Tel.: +989111566604. E-mail address: [email protected]. P. Box 484. E-mail address: [email protected]. 2 E-mail address: mgh_elec@ yahoo.com. 1

V out 1

V out 1

(a )

−Gm

−Gm

−Gm

−Gm

−Gm

−Gm

V out 2

V out 3

td

V sw

odd number of stages

(b )

td

t

V out 2

−Gm

t

V out 3

T = 2Nt d t

Fig. 1. The chain of delay stages in a) a single-ended ring oscillator and b) a differential ring oscillator.

Fig. 2. The delay-stage timing waveforms.

II. PREVIOUSLY DERIVED EQUATIONS FOR THE FREQUENCY OF ROS As previously mentioned, considering RO as a chain of delay stages is a method which is commonly used by designers. By defining the delay of each stage as td (as shown in Fig. 2), the total open-loop phase shift of 2π must be provided in the period of 2N.td. Therefore, the oscillation frequency is 1 f = (1) 2N ⋅ t d where td is the delay of each stage. The main challenge in deriving a closed-form frequency equation is the calculation of td, and the reasons behind this problem are the nonlinearities and parasitic effects of the circuit. Several methods have previously been proposed to derive an equation for the frequency of oscillation in ROs. The differential slew rate is defined as tail current divided by load capacitance (ISS/CL). Reference [16] assumes that the transistor of each stage initiates switching when the differential output of its previous stage crosses zero. As a result, the delay per stage is defined as the total change in differential output voltage, VSW, divided by the differential slew rate, therefore td = VSW/(slew rate) = VSW/( ISS/CL)= CLVSW/ISS. Using this definition and (1), the oscillation frequency can be calculated as follows: Iss . f = (2) 2NC LV sw The parameters that have been used in this method are listed in Table I. According to [17], the delay stage is modeled as a resistor-capacitor (RC) circuit and the delay of each stage is derived by the calculation of initial and final values, so that td =RLCLln2. Hence, the frequency is given by f = f =

1 . 2NR L C L ln 2 1

2N ⋅ (0.8) ⋅ R L (C dbN + C dbP + C gdN + C gdP + C in )

(3)

The method proposed in [18] assumes a ramp input to find the time-delay to time-constant ratio in order to obtain the following equation:

(4)

where Cin is the input capacitance of the next delay stage, and the transistor parasitic elements that are used in (4) ( C dbN , C gdN , VDD C gsP

V Bias

C dbP C gdP

V out (t )

C gdN

V in (t )

C dbN

C gsN

Fig. 4.Parasitic capacitors in a delay stage.

1

2 1 0

Id.i, mA

3

0

-1

1.6

1.5 Vo, V

Id.i, mA Vo, V

2

1.4 1.2

1.0 0.5 0.0

1.0 5.0

5.2

5.4

5.6

5.8

5.0

6.0

5.5

6.0

6.5

7.0

7.5

8.0

time, nsec

time, nsec

Fig. 5. The voltage and current in the sinusoidal output state.

Fig. 6. The voltage and current in the exponential output state.

C dbP and C gdP ) are drain-bulk and gate-drain capacitors, as shown in Fig. 4. Parasitic capacitors in a delay stage are shown in Fig. 4. Load capacitance of the delay stage in this equation can be adapted for differential ROs, as considered in this paper. A different method for deriving an equation for oscillation frequency of ROs was proposed in [19]. This method does not attempt to directly find a value for td. Rather, it creates a system of equations that can be reduced to a single equation. Oscillation frequency is the only unknown parameter in this method. The method begins by assuming that the voltage waveform at the input of a stage is sinusoidal with an unknown frequency. Therefore, an expression for the output voltage of the stage is also known, as it is a phase-shifted version of the input voltage. These voltage expressions can be used to create expressions for currents in the delay stage. These expressions VDD Vbias − Vout (t )

+ Vout (t )

Vin+ (t )

Vin− (t )

I SS

Fig. 3. Differential delay stage.

can be reduced and solved for the frequency of oscillation as follows. f =

I ss 2N .V sw (C in + C gdP )

(5)

where Cin is the input capacitance of the next delay stage and Cgdp is the gate-drain capacitance of a PMOS transistor, which is used as an active load. The other parameters that were used in (5) are listed in Table I. Two closed-form equations were also proposed for the frequency and amplitude of a single-ended RO in [20]. III. THE PROPOSED METHOD The analyses are divided into two cases in the proposed method. In the first of these, equations are derived by assuming that the outputs have sinusoidal waveforms, while in the second the outputs are assumed to be exponential. We used this method TABLE I DELAY STAGE PARAMETERS

Iss Vsw N td RL CL

Tail current used in the delay stage. Peak-to-peak amplitude of the voltage waveform. Number of delay stages in the RO. Delay of each stage in the RO. Equivalent load resistance of the delay stage. Equivalent load capacitance of the delay stage.

because variation of output voltage level will change the transistor work region in differential pairs, and will consequently change the drain current of the transistor. In the case of sinusoidal output, two transistors of differential pairs work in the saturation region, but in the case of exponential output, one of the transistors works in the cut-off region. This issue will be further discussed in the following. As derived in [21] and [22], the drain current of a transistor, when two transistors of differential pairs are in the saturation region, can be written as

I d (t )

I = ss + 2

µ n C ox 4

W LV id (t )

4 ⋅ I ss −V id (t ) 2 W µn C ox L

(6)

where Vid (t ) is the input differential voltage and I ss is the tail current source, as shown in Fig. 3. Equation (6) is a nonlinear equation for a transistor’s drain current. Oscillation amplitude is small for small loop gains, and output can be simply approximated by sinusoidal waveforms. In this condition, (6) can be satisfied and the drain current of transistors never reaches zero. According to [19] and [20], the voltage interval of output in which two transistors of differential pairs are not fully switched, and are in the saturation region, will be as the following. −

2 ⋅ I ss 2 ⋅ I ss . ≤V id (t ) ≤ W W µnC ox µnC ox L L

(7)

Note that in this condition, (6) is satisfied. Previous equations are mainly considered for small loop gains or, equally, the sinusoidal outputs condition. In this case, the expression for frequency can be simply given by using Barkhausen criterion. The oscillation amplitude is high for large loop gains, so that the transistor pair is fully switched and the introduced condition of (6) cannot be satisfied. In this condition, the tail current is fully steered by transistors and the output waveforms differ from an ideal sine wave. Therefore, the simple analysis above does not lead us to correct equations for oscillation frequency. In the proposed method we introduce a novel and general formula, and in order to do so we consider two distinct cases: a) sinusoidal outputs and b) exponential outputs. The outputs of these cases are shown in Fig. 5 and 6. In the sinusoidal case, the drain current does not reach 0 or ISS, unlike in exponential outputs, where transistors current varies in the range of (0, I SS ) . In the second case, the drain current of transistors is zero or I SS most of the time, and the transition between these two distinct values is rapid. Hence, the times at which drain current has values in the range of (0, I SS ) can be ignored. In other words, in this situation, the drain current will only be 0 or ISS. Therefore, currents can be considered as square waveforms. In the second case, output voltages have exponential waveforms because of the RC circuit in the drain and tail current source. We will introduce some criteria to separate these two cases, which will be discussed in the following. 3.1. The sinusoidal outputs

In differential ROs, when the loop gain is low, AC equivalent circuit from drains can be considered as an RC circuit in sinusoidal steady-state. Figure 5 shows the drain current and output voltage in the sinusoidal state. To calculate the output frequency, according to Fig. 5, we have: V out (t )

V in (t )

ID

I RL

RL

CL

IC L

Fig. 7. RC model for each stage in ring oscillators for the sinusoidal case in AC mode.

Vout = − Z L I d ∠Vout = ∠Z L + ∠I d +π where ZL is defined as:

(8)

1

ZL =

jC L ωosc

RL (1 + j (R L C L ωosc ) )

RL =

C L = C dbN + C dbP + C gdN + C gdP + C in + C l 1 . RL = W V gs − V tp − 0.5 V ds µ p C ox L

(

(9)

)

In the above equation, parasitic capacitors are considered according to Fig. 4 and [18]. Cin and Cl are the input capacitance of the next delay stage and external capacitor,

respectively. The above equation assumes that the equivalent resistance of the PMOS load is constant and equal to resistor load (RL). The PMOS load works in the linear region, therefore this resistance is a function of Vds. Since Vds is a function of time, this resistance is also a function of time. However, the time-varying nature of the variable PMOS load resistance has no effect on frequency [19]. Since Vin and Id are in phase, we can conclude from (8) and Fig. 7 that the phase relationship between the input and output voltages of each stage can be written as:

∠V out = ∠Z L + ∠V in + π .

(10)

As we know, the phase difference between input and output is as π − (π N ) . Therefore, we have ∠Vout −∠V in − π =∠ZL = −π N  tan(π N ) .  ⇒ ωosc = RLC L 

(11)

∠ZL = − arctan(RLC L ωosc )

Note that a single-ended RO requires at least three inverters in its loop in order to oscillate. Therefore, in the above equation: N ≥3 Now, to derive an equation for oscillation amplitude, we can write: V o max(AC ) = Z L I d max(AC ) . (12) On the basis of (9) and (11), the magnitude of ZL is as RL

ZL =

tan 2 Nπ + 1

( )

.

(13)

By combining (12) and (13), we obtain (14): VDD

I RL

RL

V out (t )

ID

V in (t )

CL

ICL

Fig. 8. RC model for each stage in ring oscillators for the exponential case.

V o max ( AC ) =

RL 2 π tan N

( ) +1

I d max ( AC ) .

Since V o max ( A C ) is equal to V in max ( A C ) , with a phase shift, we have:

V id max = 2V in max ( AC ) = 2V o max ( AC ) = V sw =

2 ⋅ RL tan 2 Nπ

( ) +1

I d max ( AC ) .

(15)

(14)

where Vsw is the maximum output swing. In addition, according to (6), we can write: W µ n C ox 4 ⋅ I ss 2 LV I d max ( A C ) = −V sw . (16) sw W 4 µ n C ox L By substituting (16) in (15) and some approximations, the following expression can be obtained for Vsw :

V sw =

4 ⋅ tan 2 Nπ + 1 4 ⋅ I ss − . 2 W  W  µn C ox L  R L µnC ox L   

( ( ) )

(17)

The above equation explains the relationship between Vsw and circuit parameter in the sinusoidal case. As previously mentioned, (7) explains the output voltage condition for the sinusoidal case. Hence, by combining (7) and (17), the following valuable inequality is obtained, and relates the aspect ratio of transistors to the circuit conditions. 2 ⋅ tan 2 Nπ + 1 W ≤ . L µnC ox .I ss .R L2

( ( ) )

(18)

Equation (18) illustrates the condition in which an oscillator has sinusoidal outputs. 3.2. The exponential outputs

As mentioned above, when (18) is satisfied, sinusoidal waveforms are a good approximation of outputs. For aspect ratios for which (18) is not satisfied, outputs are not sinusoidal and the currents of transistors are very similar to square waves. Figure 6 shows the wave forms of the exponential output case. On the basis of the previous discussion and Fig. 8, in this case the output can be written as: V out (t ) =V out (final ) + [V out (initial ) −V out (final )]  −t  (19) × exp  .  R LC L  According to the above discussion, the transient of output in the rising and falling duration can be written as the following. (see Fig. 9)

V rise (t ) =V DD + (V out − −V DD ) ⋅ exp(−αt )

(20)

V fall (t ) =V DD − R L I SS + (V out + −V DD + R L I SS )

(21)

× exp(−α (t − t1 )).

+ − In the above equations, α = 1 R LC L , t1 = T 2 = 1 2 f and T is the time period of oscillation. Terms V out and V out are the maximum and minimum output voltages, respectively. According to Fig. 9, the following equations can easily be written for Vout + and Vout − from (20) and (21).

V out + =V DD + (V out − −V DD ) ⋅ exp(−αt1 )

(22)

V out − =V DD − R L I ss + (V out + −V DD + R L I ss )

(23) ⋅ exp(−α t1 ). Subtracting (23) from (22) leaves an explicit relationship between output swing and frequency, which is shown in the following.

V sw = R L I ss − (R L I ss +V sw ) ⋅ exp(−α t1 ) where Vsw = Vout + − Vout − and t1 =

T 1 = . 2 2f

(24)

Note that t1 is the half time period of oscillation. Additionally, each output rises for a duration of Ntd , and falls for a duration of Ntd . Therefore, we can write t1 = Nt d . According to (24), VSW and f are two unknown parameters. Therefore, another equation is required for the calculation of these parameters. As we know, the input voltage of each stage is the output of the previous stage. Fig. 9 shows that td is the time that each transistor needs for switching the next stage transistor. Hence, the following equations can be written for the calculation of the level of switching voltage: Vsw ∆VSwitch + = Vrise (t ) t = td 2 2 V ∆VSwitch VSwitch , DN = sw − = V fall (t ) t = t1 + td 2 2 ∆VSwitch = VSwitch,UP − VSwitch, DN

(25)

VSwitch ,UP =

(26) (27)

where VSwitch,UP and VSwitch, DN are the output voltage levels that can turn the next-stage transistor on and turn off, respectively. It should be noted that the delay of each stage is V out 1

t1 = T 2

V out 1

V out 2

V out 3

V out + V Switch ,UP V Switch ,DN V out −

td

td

td

t

V out 2

t

V out 3

t Fig. 9. The exponential output voltage for a ring oscillator with three delay stages. Output voltage turns on the next stage by crossing from V Switch ,UP and turns off the next stage by crossing fromV Switch , DN . In addition, td is the time that each transistor requires to switch the next stage transistor following its switch. Vout+ is the maximum output voltage and Vout- is the minimum output voltage.

the time between the status change of each stage and the status change of the next stage. Therefore, according to Fig. 9, the time between minimum output voltage and VSwitch,UP is equal to a delay time (td), which is also equal to the time between maximum output voltage and VSwitch, DN . From (20) and (25), we have:

V Switch ,UP =V DD + (V out − −V DD ) ⋅ exp(−αt d )

(28)

and from (21) and (26), we also have: V Switch , DN = V DD − R L I ss + (V out + −V DD + R L I ss ) ⋅ exp( −α t d ).

(29)

Subtracting (28) from (29) leaves the relationship between ∆VSwitch and frequency, which is shown in (30):

∆V Switch = R L I ss − (R L I ss +V sw ) ⋅ exp(−α t d ).

(30)

According to (7), it is obvious that: 2 I ss

∆V Switch = V id (t d ) = 2

W L

µ n C ox

, t d = t1 N .

(31)

By considering (24) and (30), we can find output voltage swing and oscillation frequency. From (24) and t1=1/2f, we can derive f as below. 1 f = .  R L I ss +V sw  (32) 2R L C L ln    R L I ss −V sw  In the above equation, Vsw is unknown, but by replacing (32) and td=1/2Nf in (30) we have ∆V Switch = R L I ss − ( R L I ss +V sw ) N

R L I ss −V sw . R L I ss +V sw

(33)

By assuming ∆VSwitch ≈ 0 and using (32) and (33), Vsw can be estimated for a three-stage RO as V sw =

(

)R

5 −1 2

L I ss

≅ 0.6R L I ss .

(34)

By replacing (34) in (32), a frequency relationship independent of Vsw is given by

f =

1 1 = .  R L I ss + 0.6R L I ss  4R L C L ln(2) 2R L C L ln    R L I ss − 0.6R L I ss 

(35)

Equation (33) shows that increasing N results in a lower difference between Vsw and RL I ss . Therefore by defining ∆Vsw = RL I ss − Vsw , we can rewrite (33) as below:  R L I ss − ∆V Switch     2R L I ss + ∆V sw 

N

=

∆V sw . 2R L I ss + ∆V sw

(36)

Drain currents are considered as square waveforms, and ∆V Switch can be assumed equal to zero according to (31). In addition, for large values of N, ∆Vsw is negligible compared to R L I ss . Therefore, from (36), we have: ∆V sw ≈ R L I ss (0.5) N

−1

(37)

.

Given the above description and (37), for large values of N we have: V sw = R L I ss − ∆V sw ≈ R L I ss 1 − (0.5) N −1 .

(

)

(38)

By replacing (38) in (32), the frequency of the oscillator for large values of N can be rewritten as follows: 1 f =  R I + R I 1 − (0.5)N −1  L ss L ss  2R L C L ln   N −1   R L I ss − R L I ss 1 − (0.5)    1 1 = = (39)  2 − (0.5)N −1  2R L C L ln 2N − 1 2R L C L ln   (0.5)N −1    1 For Large N  →f ≅ . 2NR L C L ln(2)

( (

) )

(

)

The above equation is similar to (3); however, we show that (3) is true when (18) is not satisfied, and the number of delay stages (N) is high. It should be noted that by increasing N, generation of a sinusoidal output will become more difficult, according to (18), but if the derived condition is true, (11) will be used to calculate the frequency. According to (38) and (39), increasing N decreases the oscillation frequency and increases the swing voltage. However, these equations are derived for large values of N. Since oscillation frequency and swing voltage equations are not directly derived in (32) and (33), we will obtain different values of ( γ ) with respect to N by using the

Table II The analysis results and their condition Output waveform Sinusoidal

Conditions

Analysis results

f = 2.(tan 2 ( Nπ ) + 1) W ≤ L µ n C ox .I ss .R L2

V sw =

( )

tan Nπ

2π R L C L

4I ss

−

W µn C ox L

4. tan 2 Nπ + 1

(

( ) )

W    R L µn C ox  L  

V sw = R L I ss 1 − (0.5)γ ( N −1)

(

Exponential

2.(tan 2 ( Nπ ) + 1) W > L µ n C ox .I ss .R L2

f =

1 2γ NR L C L ln(2)

where N = 3 ⇒ γ = 0.67 N = 4 ⇒ γ = 0.87 N = 5 ⇒ γ = 0.95 N ≥ 6 ⇒ γ =1

)

2

1.2

Vsw(v)

1 0.8

0.6 Simulation Analysis

0.4 0.2

1

1.5

2

2.5

Iss(mA)

Fig. 10. Plot of the output swing versus Iss for sinusoidal case. N=3, Wn/L=12/0.18, Cl=130fF, RL=0.5k

. 1.6 1.4

Vsw

1.2 1 0.8 0.6 Simulation Analysis

0.4 0.2 0.5

1

1.5 Iss

2

2.5

Fig. 11. Plot of the output swing versus Iss for exponential case. N=3, W/L=50/0.18, Cl=250fF, RL=1k

numerical method to solve the above system ((32) and (33)). We consequently directly derive oscillation frequency and swing voltage equations versus N, as indicated in Table II, which summarizes the results of the above analysis. IV. SIMULATIONS VERSUS ANALYTICAL RESULTS To evaluate the proposed model, a differential RO was simulated using the Taiwan Semiconductor Manufacturing Company 0.18 µ m model at a 1.8 V supply voltage, and different experiments were performed using this simulation. The derivation for the above equation assumes that the equivalent resistance of the PMOS load is constant, according to (9). To ensure an improved evaluation of analysis an external resistance load (RL) was used instead of a PMOS load in some simulations, as shown in Fig. 10 to 13. In addition, external capacitor (Cl) was used in some simulations to control frequency. It should be noted that Cl is added to CL for the calculation of frequency. Figures 10 and 11 show the output swing of the oscillator. Here, simulations were performed using external RL and Cl. As is clear, the analysis results are very close to the simulation. The analysis results deviated from the simulation results for low values of ISS by approximately 0.04 V and 0.025 V for the sinusoidal case and the exponential case, respectively.

Fig. 12. Plot of oscillation frequency versus resistor load for sinusoidal case. N=3, Wn/L=[4/0.18_10/0.18], Cl=[67.5fF_87fF], Iss= 1mA

Fig. 13. Plot of oscillation frequency versus external capacitor for exponential case. N=3, Wn/L=15/0.18, RL= 1.5k, Iss= 1mA

Figures 12 and 13 show the frequency calculated by the proposed equations versus RL and Cl, compared to other studies. As the figures show, our results are more accurate than the results of other methods. In Fig. 12, oscillation frequency was plotted versus external resistor in the sinusoidal case. Here, we changed Wn according to the conditions of Table II; therefore, we changed the Cl with the change in Wn to fix the equivalent capacitor load and to eliminate the effect of capacitance load variation on the variation of oscillation frequency. Figures 14 and 15 show the comparison of simulation results for the two cases of sinusoidal and exponential output. Here, we did not use Cl and RL, so RO conditions for the two defined cases were altered by the variation of transistor width. This figure shows that derived equations verify the simulation results for different values of N, and they do so because these equations were derived in different conditions. V. CONCLUSIONS In this paper, a new method is proposed to calculate the amplitude and frequency of differential ROs. The analysis is divided into two distinct parts; initially, outputs are assumed to be sinusoidal, and closed-form equations are obtained for frequency and amplitude. In the instances where the results did not meet the necessary conditions for sinusoidal output, outputs are assumed to be exponential and related equations were obtained accordingly. The simulations showed the high degree of accuracy of the proposed model.

Fig. 14. Plot of oscillation frequency versus the number of stage for sinusoidal case. Vbias=0.7, Iss=[0.6_1mA], Wn/L=7/0.18, Wp/L=10/0.18.

Fig. 15. Plot of oscillation frequency versus the number of stage for exponential case. Vbias=0.7, Iss=[0.6_1mA], Wn/L=15/0.18, Wp/L=10/0.18.

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Highlights - A new method is proposed for computing amplitude and frequency of differential ring oscillators. - This method is supposed to provide analytical equations more accurate and exact than previous methods - It provides the toggle condition for which the oscillator passes from being linear (sinusoidal signal) to nonlinear (exponential signal). - Analytical results confirm the simulation results using TSMC 0.18µm technology model in 0.5 to 10 GHz frequencies.