Analytical and numerical study of the impact of HALOs on short channel and hot carrier effects in scaled MOSFETs

Solid-State Electronics 46 (2002) 429–434

Analytical and numerical study of the impact of HALOs on short channel and hot carrier effects in scaled MOSFETs S. Zanchetta *, A. Todon, A. Abramo, L. Selmi, E. Sangiorgi DIEGM – University of Udine, via delle Scienze 208, 33100 Udine, Italy Received 17 February 2000; received in revised form 14 February 2001; accepted 1 March 2001

Abstract This paper investigates the relationship between various HALO parameters best suited to achieve short channel effect control in MOSFETs with channel lengths of ’0.1 lm. New insights into the HALO control upon threshold voltage have been achieved by means of a simple analytical model. The analysis has been refined through extensive drift diffusion simulations based on a parametric representation of the HALO profile. Ó 2002 Elsevier Science Ltd. All rights reserved. Keywords: Implantation pockets; MOSFET; Scaling; Short channel effects

1. Introduction The subject of scaling the MOSFET channel length below 0.1 lm has gained increasing interest in recent years, because of the growing demand to meet and, possibly, to accelerate the predictions of the SIA roadmap. Preliminary investigations [1] point out the advantages of the epitaxial ground plane (GP) concept in terms of compatibility with mainstream technology and the capability to maintain acceptable performance down to very short channel length. The high cost of epitaxy has led to development of alternative ways to achieve super-steep retrograde (SSR) profiles, e.g. by making use of heavy ion implantation techniques [2]. Since then, it has been generally accepted that HALOs (p-pockets) or super-HALOs should be added to the basic GP architecture to control short channel effects (SCE) and to reduce the device sensitivity to process-induced channel length variations [3–6]. Optimization of the above MOSFET architecture, however, is still a difficult multi-variable problem [7], made even more complicated by the two-dimensional (2D) nature of the doping profile. In particular, al-

*

Corresponding author. Tel./fax: +39-0432-55-82-51. E-mail address: [email protected] (S. Zanchetta).

though recent work based on simple analytical models [8] has given valuable insight into the optimization of this design concept, it is still not clear what the optimum HALO profile should be [9] in order to achieve a specified device performance. Furthermore, limited knowledge is available on the relationship between HALO process parameters (dose, energy, implantation angle, etc.) and the resulting doping profile. In this framework, we exploit two different modeling approaches (one analytical, the other numerical) to gain a deeper insight in the impact of HALOs on threshold voltage and SCE control in deep sub-micron technologies. The first one allows us to define a critical penetration of the HALO in the channel that yields maximum flatness of the threshold voltage versus channel length curve. The second allows to explore doping profile steepness requirements that provide a good compromise between the contrasting needs of threshold voltage and hot carrier (HC) control.

2. Quasi two-dimensional model To gain a first understanding of HALO design constraints and to restrict the range of suitable HALO parameters we implemented a simple model based on the quasi-2D approach proposed in Ref. [10] to integrate

0038-1101/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 1 ) 0 0 1 1 6 - 2

430

S. Zanchetta et al. / Solid-State Electronics 46 (2002) 429–434

Fig. 1. Schematic MOSFET cross-section with definition of the analytical model parameters.

Poisson’s equation in conventional MOSFETs. Following Ref. [11] the doping is approximated by a piecewise constant profile (Fig. 1). The threshold voltage ðVT Þ is defined as the gate voltage such that /s;min ¼ 2UFC , where /s;min is the minimum surface potential, UFC is the channel Fermi potential and / ¼ 0 in the neutral region of the bulk. In each region (left pocket – LP, right pocket – RP, and channel – C) /s ðxÞ is expressed as:

Fig. 2. Left plot: comparison of the surface potential calculated by the analytical model (  ) with that from fully 2D drift, NC ¼ 5  1017 diffusion simulations (—). VGS ¼ 0 V, tox ¼ 40 A cm3 . Right plot: threshold voltage calculated with the analytical model (  ) and with full 2D drift-diffusion simula, VDS ¼ 1 mV. tion (—). NC ¼ 5  1017 cm3 , tox ¼ 40 A

sinhððx  xL;i Þ=ki Þ þ ð/L;i  /s;i Þ sinhðLi =ki Þ sinhððxR;i  xÞ=ki Þ þ /s;i  ð1Þ sinhðLi =ki Þ

/s ðxÞ ¼ ð/R;i  /s;i Þ

where i ¼ RP, LP or C, xR;i and xL;i are the coordinates of the region boundaries, Li ¼ xR;i  xL;i , /R;i ¼ /s ðxR;i Þ, /L;i ¼ /s ðxL;i Þ, ki is a suitable decay length computed according to Ref. [10] and /s;i ¼ /s;i ðVG Þ is the long channel surface potential given by
 /s;i ðVG Þ ¼ VG  VFB þ 0:5c2i 0 1 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2 V  V G FB A ð2Þ  @1  1  VG  VFB þ 0:5c2i where ci is the body effect coefficient. The set of Eq. (1) can be solved with the boundary conditions /L;LP ¼ Vbi , /R;RP ¼ Vbi þ VDS to calculate /s ðxÞ in the whole structure. Since the equations are valid for any gate voltage value between flat band and threshold we can find VT as the VG value that yields /s;min ¼ 2UFC . Fig. 2 compares /s ðxÞ (left plot) and VT ðLÞ (right plot) results calculated with the analytical model to those of a drift-diffusion simulator [12] and demonstrate satisfactory mutual agreement over a broad parameter range. The upper plot in Fig. 3 gives the linear threshold voltage of submicron MOSFETs predicted by the analytical model as a function of the pocket penetration

Fig. 3. Threshold voltage VT of HALO devices at VDS ¼ 1 mV (upper graph) and VDS ¼ 1 V (lower graph), as a function of pocket length LP . NC ¼ 5  1017 cm3 , NP ¼ 2  1018 cm3 , . tox ¼ 40 A

in the channel ðLP Þ. As can be seen, a critical LP exists ðLP;crit Þ that yields a threshold voltage independent of channel length. Below LP;crit the threshold voltage of the longer devices is controlled by the channel doping and remains unaffected by the HALO, whereas that of the short devices exhibits relevant SCE. Around LP;crit , an optimum region exists where VT is controlled by HALO, but still fairly independent of LG . Instead, above LP;crit VT tends to a maximum value fixed by the HALO doping, while relevant reverse short channel effects (RSCE) arise, eventually compromising the flatness of VT versus LG . Qualitatively similar results are observed at high VDS (lower graph in Fig. 3), but in this case LP;crit is larger

S. Zanchetta et al. / Solid-State Electronics 46 (2002) 429–434

431

this condition is reached, VT remains constant for long channels, as expected from the results of Fig. 3. When LP;crit is exceeded also VT starts to increase. This observation suggests that, LP;crit corresponds to the condition   d/s ðxÞ ¼0 ð3Þ dx x¼xR;LP Imposing this condition yields:   Vbi  /s;LP LP;crit ¼ kP acosh /s;C  /s;LP

Fig. 4. Surface potential of HALO devices featuring VGS ¼ VT and different pocket length LP but constant channel and pocket doping (NC ¼ 5  1017 cm3 and NP ¼ 1018 cm3 , respectively). VT is unchanged as long as the surface potential exhibits only one minimum.

and weakly dependent on the range of channel lengths considered. As a result, the curves exhibit a larger spread than those for small VDS . To explain this behavior, Fig. 4 presents /s ðxÞ of devices with increasing LP biased at VDS ¼ 0 and VGS ¼ VT , that is, having the same /s;min . Clearly, LP;crit corresponds to the physical condition at which two distinct minima start to appear in the surface potential. Until

ð4Þ

Eq. (4) represents the HALO extension below which SCE dominate VT scaling; therefore, it provides the minimum value of pocket penetration required to compensate short channel effects, at least at low VDS .

3. Full two-dimensional simulations The first order analytical model can provide useful lower limits for pocket penetration in the channel and dose but, due to the piecewise constant doping assumption, it does not give information about the requirements for HALO steepness and their relationship with process parameters. To address these issues, a more realistic model has been adopted. In particular, HALOs have been described by gaussian profiles parametrized by the quantities defined in the inset of Fig. 5. The SSR

Fig. 5. Relationship between the pocket implantation angle h and q ¼ ðXpeak þ Llat Þ=ðYpeak þ Lvert Þ according to: (a) assumptions of this work; (b) data from Ref. [3]. The inset reports the definition of the parameters of the Gaussian doping profiles used to describe the HALOs. Llat and Lvert represent the standard deviation of the Gaussian profile in the lateral and vertical direction, respectively.

432

S. Zanchetta et al. / Solid-State Electronics 46 (2002) 429–434

channel profile, the source/drain and the MDD structure, instead, are representative of a 0.13 lm technology, and were tentatively kept fixed to emphasize the role of HALOs in device performance. In particular, the peak concentration of the SSR is 1018 cm3 and is located 0.08 lm below the interface. The source and drain implant dose is 2  1015 cm2 , corresponding to a location of the junction 0.13 lm below the interface, almost independent of the addition of HALOs. The MDD extension dose is 8  1013 cm2 . Two different optimization strategies have been explored through extensive 2D drift-diffusion simulations, including Van Dort’s quantum mechanical corrections [13]. Both assume Ypeak ¼ Lvert ¼ Xj =2 to limit the increase of junction capacitance due to boron spreading below the source and drain. The first strategy (denoted (a) in the following) assumes that the ratio between the vertical and lateral standard deviation of the Gaussian HALOs (g ¼ Llat =Lvert ¼ 0:3) is fixed by process conditions. NP is then optimized for each implantation angle (h) to get the flattest VT compatible with a RSCE lower than 30 mV. The second strategy (b) aims at the same goal with respect to VT flatness, but changes the ratio q ¼ ðXpeak þ Llat Þ=ðYpeak þ Lvert Þ as a function of h according to the data in Ref. [3]. These strategies are summarized by the q versus h curves in Fig. 5, and emulate different processing conditions. Fig. 6 gives the peak pocket concentration (NP ) and the corresponding implant dose as a function of h for different strategies. Note that strategy (a) corresponds to a higher peak doping and also a steeper lateral HALO profile than strategy (b). In particular, the lateral HALO steepness at the interface is approximately 16 nm/dec for strategy (a) and 40 nm/dec for strategy (b). Instead, the average lateral source/drain steepness is approximately 8 nm/dec, in good agreement with the results of Ref. [6].

Fig. 7. Upper plot: threshold voltage of optimized structures according to strategy (a) (solid line with open symbols) and (b) (dashed line with filled symbols) for different angles of the HALO implant: h ¼ 7° (); h ¼ 25° ( ); h ¼ 45° ( ). , VDS ¼ 1:2 V. VT is defined as the VGS such that tox ¼ 25 A ID ¼ 1 lA/lm at VDS ¼ 1:2 V. Lower plot: threshold voltage versus channel length for different implantation angles according to strategy (a) and different values of g ¼ Llat =Lvert . (  ): g ¼ 0:4; (—): g ¼ 0:2.

4. Short channel effect performance analysis Fig. 7 (upper plot) shows the threshold voltage (VT ) as a function of LG for different h angles and optimization strategies. We observe that, for a given maximum RSCE, a small h is beneficial to achieve a flat VT over a large LG range. Furthermore, strategy (a) provides better SCE control than strategy (b), thereby confirming the advantages of a steep HALO profile in the lateral direction. These steep profiles, however, have a detrimental effect on the sensitivity to process variations and in particular to the spread on g ¼ Llat =Lvert . This is demonstrated in Fig. 7 (lower plot), where VT curves for different values of the parameter g are given. Fig. 8 presents the off-state current of the optimized devices at VGS ¼ 0 V and VDS ¼ 1:2 V, demonstrating less than 109 A/lm for progressively lower LG as h is decreased. These calculations do not include band to band tunneling generation, but we verified that the peak field in the drain/gate overlap region is well below the threshold for significant tunneling (F > 1 MV/cm).

5. Hot carrier performance analysis

Fig. 6. Optimum peak pocket doping (NP ) and corresponding implant dose, as a function of implantation angle h for the two strategies explored in this work. Symbols are the same as in Fig. 5.

The high doping necessary to control SCE can significantly increase the local electric field in proximity of the drain junction, thus enhancing conventional channel HC effects. In addition, HALO extensions also increase the concentration deep in the substrate; therefore, in

S. Zanchetta et al. / Solid-State Electronics 46 (2002) 429–434

433

worse than that of the same device without HALOs and of that with HALOs designed according to strategy (b) (6 times and 5 times worse, respectively). These results indicate that excessive HC effects could represent a further limitation of strategy (a) with respect to strategy (b). 6. Conclusions

Fig. 8. Off state current at VGS ¼ 0 V and VDS ¼ 1:2 V of the devices in Fig. 7. (—): strategy (a); (  ): strategy (b).

presence of an applied substrate voltage they can lead to a large increase of the so-called channel initiated secondary electron injection regime (CHISEL, [14,15]). In order to study how these effects affect threshold voltage and SCE control, high energy transport simulations have been carried out (at zero substrate bias) by means of the Monte Carlo simulator ‘‘band.it’’ [16]. More specifically, a non-self-consistent approach has been taken but, in order to incorporate the effect of hot electrons on the potential distribution, the potential profile was derived from hydrodynamic simulations using Ref. [12]. Fig. 9 gives the substrate current IB , and the ratio IB =ID of 0:12 lm devices featuring the best design (i.e. that for h ¼ 7°) normalized to those of the non-HALO device architecture. The substrate current of the device designed according to strategy (a) is substantially

10.0 Normalized IB and IB/ID

o

8.0 6.0 4.0

θ=7 LG=0.12µm VDS=VGS=2V IB IB/ID

2.0 0.0

no-halo

(a)

(b)

Fig. 9. Hystogram of the substrate current (IB ) and ratio between substrate and drain current (IB =ID ) of 0:12 lm channel length devices without HALOs, and featuring HALO designs according to strategy (a) and (b). VGS ¼ VDS ¼ 2 V.

In summary, a quasi-2D model and drift diffusion simulations were exploited to derive HALO design guidelines for a scaled MOS technology. Results indicate that the lateral HALO steepness plays a crucial role in controlling SCE and Ioff for a given source/drain structure. Simulation results, however, demonstrate that high doping and super-steep profiles require tighter control of process conditions due to increased sensitivity to process variations, and may trigger excessive HC effects or premature band to band tunneling and avalanche of the source/drain junctions.

Acknowledgements The authors would like to acknowledge stimulating discussions with S. Kubiceck (IMEC, Belgium). This work was partially supported by the italian MURST and the UE under the ‘‘40%’’ and ULIS projects, respectively. References [1] Fiegna C, Iwai I, Wada T, Saito M, Sangiorgi E, Ricc o B. Scaling the MOS transistor below 0:1 lm: methodology, device structures and technology requirements. IEEE Trans Electron Dev 1994;41:941. [2] Shahidi GG, Antoniadis DA, Smith HI. Indium channel implant for improved short-channel behavior of submicrometer NMOSFET’s. IEEE Trans Electron Dev 1993;14(8):409. [3] Hori T. A 0:1 lm CMOS technology with tilt-implanted punchthrough stopper (TIPS). IEDM Tech Dig 1994:75. [4] Wann CH, Noda K, Tanaka T, Yoshida M, Hu C. A comparative study of advanced MOSFET concepts. IEEE Trans Electron Dev 1996;43:1742. [5] Kurata H, Sugii T. Self aligned control of threshold voltages in sub-0.2 lm MOSFET’s. IEEE Trans Electron Dev 1998;45(10):2161. [6] Taur Y, Wann CH, Frank DJ. 25 nm CMOS Design Considerations. IEDM Tech Dig 1998:789. [7] Kubicek S, Henson WK, Keersgieter A, Badenes G, Jansen P, Meer H, Kerr D, Naem A, Deferm L, Meyer K. Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides. IEDM Tech Dig 1999:823. [8] Skotnicki T, Merckel G, Pedron T. The voltage-doping transformation: a new approach to the modeling of

434

[9]

[10]

[11]

[12]

S. Zanchetta et al. / Solid-State Electronics 46 (2002) 429–434 MOSFET short channel effects. IEEE Electron Dev Lett 1988;9(3):109. Gwoziecki R, Skotnicki T, Bouillon P, Haond M, Coster W. Improved understanding and optimization of 0.18 lm CMOS technology with retrograde channel and pockets. Proc Euro Solid State Dev Res Conf, 1998. p. 353. Liu ZH, Hu C, Huang JH, Chan TY, Jeng MC, Ko PK, Cheng YC. Threshold voltage model for deep-submicrometer MOSFET’s. IEEE Trans Electron Dev 1993;40(1):86. Yu B, Wann CH, Novak ED, Noda K, Hu C. Shortchannel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET’s. IEEE Trans Electron Dev 1997;44(4):627. ISE, Dessis user’s manual. Tech rep, ISE, Integrated Systems Engineering, 1998.

[13] Van Dort MJ, Woerlee PH, Walker AJ, Juffermans CA, Lifka H. A simple model for quantisation effects in heavilydoped silicon MOSFETs at inversion conditions. SolidState Electron 1994;37:411. [14] Bude JD, Frommer A, Pinto MR, Weber GR. EEPROM/ flash sub 3.0 V drain–source bias hot carrier writing. IEDM Tech Dig 1995:989. [15] Bude JD, Mastrapasqua M, Pinto MR, Gregor RW, Kelley PJ, Kohler RA, Leung CW, Ma Y, McPartland RJ, Roy PK, Singh R. Secondary electron flash – a high performance, low power flash technology for 0.35 lm and below. IEDM Tech Dig 1997:279. [16] Venturi F, Ghetti A. Assessment of accuracy limitations of full band monte carlo device simulation. Proc SISPAD, 1997. p. 343.