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Annealing of damage in Se+-implanted indium phosphide
I 172
World Abstracts on Microelectronics and Reliability
slope at the junctions center. Numerical values are given for silicon and germanium.
independent Gaussian profiles for two diffusion coefficients. and results in the kink and tail structures of the profile.
Silicon processing with silicon carbide furnace components. BRYAN D. FOSTER and R. E. TRESSLER.Solid St. Technol. 143 (October 1984). The material purity and operating characteristics of silicon carbide, polysilicon, and fused silica tubes are compared. An analysis of the silicon carbide starting purity performed with neutron activation analysis showed it to be comparable or superior to that of fused silica. Atomic absorption spectroscopy and deep level measurements carried out on processed silicon wafers showed the silicon carbide tube to yield the highest purity silicon processing. These results are discussed in terms of the composition and structure of the various furnace component materials.
Analysis of distribution of boron and phosphorus concentration in poly Si SiO2-Si. CEZARY SLABY and JANINA MARCIAKKOZLOWSKA. Electron Technol. 16, 35 (1983). Basing on the analytical solution of the impurity diffusion equation in the three-layer structure, a distribution of the boron and phosphorus concentration in poly Si SiO 2- Si is discussed. An influence of the layer thickness and the diffusion parameters upon the impurity concentration profile is examined. A method for determining of the diffusion coefficients in poly Si SiO2 Si structure is proposed. A masking condition in the discussed structure is obtained.
The role of surface treatment on the anodic oxidation of nGaAs. MADHU KOCHHAR, O. P. DAGA, B. R. SINGH and W. S. KHOKLE. Microelectron. Reliab. 24, 629 (1984). Surface preparation plays an important rote in obtaining good quality ohmic and Schottky contacts on GaAs. Different chemical treatments have been observed to affect surface compositions and stoichiometry of interfacial GaAs and etch characteristics [1 6]. These parameters are expected to influence the growth kinetics of interfacial anodic oxide layer which in turn would affect the interface properties. The objective of this paper is to report the effects of surface preparation on the anodic oxidation of GaAs and to gain insight of the growth kinetics. The effects of growth temperature and anodization current density are also included. Annealing of damage in Se+-implanted indium phosphide. J. D. WOODHOUSE, J. P. DONNELLY, P. M. NITISHIN, E. I. OWENS and J. L. RYAN. Solid-St. Electron. 27, 677 (1984). The production and annealing of damage in (100) InP implanted with Se + ions at 77 K, room temperature and 180°C have been studied by channeling and differential Hall measurements. For ion energies from 100 to 400KeV, fluences of 1014 and l0 ~s cm -z produce amorphous layers which extend to the surface in samples implanted at 77 K or room temperature, while the samples implanted at 180°C remain crystalline. According to the channeling measurements, amorphous layer less than 2000 A thick produced by either 77 K or room-temperature implants are completely recordered by annealing at 750°C for 10min, while the post-anneal residual disorder of thicker layers is linearly dependent on the initial amorphous layer thickness. After annealing, samples implanted at 180°C have higher sheet carrier concentrations and mobilities but considerably broader carrier concentrations than samples similarly implanted at either 77 K or room temperature, even when the amorphous layers in the latter samples are completely recordered. It is considered that for most applications heated implants should be used to avoid the formation of amorphous layers. Interband recombination in doped GaAs. MACIEJ BUGAJSK! and ANDRZEJ M. KONTKIEWICZ. Electron. Technol. 15, 49 (1982). The luminescence spectra of heavily-doped GaAs are calculated in terms of the van Roosbroeck-Shockley detailed balance principle [1]. Unlike the usual approach to this problem, using the experimental absorption curve ct(h~o), the theoretical frequency dependence of an absorption coefficient in a doped semiconductor which had been reported earlier [2, 3] has been employed. The applicability of the detailed balance principle is also discussed. Process modeling of phosphorus diffusion in silicon--a new model. G. ERANNA and D. KAKATI. Solid St. Technol. 116 (December 1984). A new process model for phosphorus diffusion into silicon is proposed. It is based on the concept that the phosphorus profile can be fitted using two
On the semi-insulating polycrystalline silicon resistor. M1NGKWANG LEE and CHIH-YUAN LU, KuN-ZEN CHANG and CnlNTAV Sum. Solid-St. Electron. 27, 995 (1984). The n p neutralization reaction between phosphorus and boron incorporated in polysilicon fihns was investigated. A process for fabricating semi-insulating polysilicon resistors has been developed. It has been found that the I-V characteristics seem not to be so explicitly related to the resistor length as for resistors fabricated using conventional methods. The activation energies observed are from 0.24 to 0.3t eV which are very small compared with those of polysilicon resistors fabricated using conventional methods, i.e. the temperature coefficient of the semi-insulating polysilicon resistors in the present studies is significantly lowered. Numerical simulation of hot-electron effects on source-drain burnout characteristics of GaAs power FETs. F. A. BUOT and K.J. SLEGER.Solid-St. Electron. 27. 1067 (1984). A High Speed Semiconductor Device Analysis (HISSDAY) computer program, based on the energy transport model, is used to numerically analyze various GaAs FET structures to gain physical insights and to establish potential design criteria for minimization of burnout phenomena. A major finding is the relationship between the spatial distribution of hot electrons in the gate-drain region and the degree of burnout tolerance. FET structures which effectively prevent hot electrons from reaching the drain edge demonstrate high burnout power. Recessed-gate structures alone do not prevent hot electrons from reaching the edge of the drain electrode and therefore cannot prevent or minimize source-drain burnout. Gate-todrain surface-field considerations also indicate that whereas recessed-gate designs improve gate-drain avalanche breakdown voltages, recessed-channel and n + ledge designs tend to degrade gate-drain avalanche breakdown voltages. The combination of recessed gate and n + ledge or recessed channel (double-recess structure) is a central feature to designs which minimize both gate-drain avalanche and source-drain burnout. A feedback-system model of the source-drain burnout mechanism for all FET slructures simulated is proposed. Significant source-drain burnout voltage degradation at large gate biases near pinchoff is clarified in terms of the strong sensitivity of the hot electron energy-density distribution to channel opening in conventional MESFETs. Calculation of the extended-state electron mobility in hydrogenated amorphous silicon. M. SILVER and E. SNOW' Solid St. Commun. 54, 15 (1985). In a recent paper, Marshall and his collaborators conclude that the extended-state electron mobility in hydrogenated amorphous silicon is 10 20 cm2/V-s. This deduction is based on experimental results indicating the demarcation level does not exceed 0.14 eV, in disagreement with conventional multiple-trapping theory. In this paper, we show that the data can be understood without modification of the existing theory, and reiterate that the observed drift mobility and density of localized states require an extended-state electron mobility in excess of 100 cmZ/V s.
World Abstracts on Microelectronics and Reliability
slope at the junctions center. Numerical values are given for silicon and germanium.
independent Gaussian profiles for two diffusion coefficients. and results in the kink and tail structures of the profile.
Silicon processing with silicon carbide furnace components. BRYAN D. FOSTER and R. E. TRESSLER.Solid St. Technol. 143 (October 1984). The material purity and operating characteristics of silicon carbide, polysilicon, and fused silica tubes are compared. An analysis of the silicon carbide starting purity performed with neutron activation analysis showed it to be comparable or superior to that of fused silica. Atomic absorption spectroscopy and deep level measurements carried out on processed silicon wafers showed the silicon carbide tube to yield the highest purity silicon processing. These results are discussed in terms of the composition and structure of the various furnace component materials.
Analysis of distribution of boron and phosphorus concentration in poly Si SiO2-Si. CEZARY SLABY and JANINA MARCIAKKOZLOWSKA. Electron Technol. 16, 35 (1983). Basing on the analytical solution of the impurity diffusion equation in the three-layer structure, a distribution of the boron and phosphorus concentration in poly Si SiO 2- Si is discussed. An influence of the layer thickness and the diffusion parameters upon the impurity concentration profile is examined. A method for determining of the diffusion coefficients in poly Si SiO2 Si structure is proposed. A masking condition in the discussed structure is obtained.
The role of surface treatment on the anodic oxidation of nGaAs. MADHU KOCHHAR, O. P. DAGA, B. R. SINGH and W. S. KHOKLE. Microelectron. Reliab. 24, 629 (1984). Surface preparation plays an important rote in obtaining good quality ohmic and Schottky contacts on GaAs. Different chemical treatments have been observed to affect surface compositions and stoichiometry of interfacial GaAs and etch characteristics [1 6]. These parameters are expected to influence the growth kinetics of interfacial anodic oxide layer which in turn would affect the interface properties. The objective of this paper is to report the effects of surface preparation on the anodic oxidation of GaAs and to gain insight of the growth kinetics. The effects of growth temperature and anodization current density are also included. Annealing of damage in Se+-implanted indium phosphide. J. D. WOODHOUSE, J. P. DONNELLY, P. M. NITISHIN, E. I. OWENS and J. L. RYAN. Solid-St. Electron. 27, 677 (1984). The production and annealing of damage in (100) InP implanted with Se + ions at 77 K, room temperature and 180°C have been studied by channeling and differential Hall measurements. For ion energies from 100 to 400KeV, fluences of 1014 and l0 ~s cm -z produce amorphous layers which extend to the surface in samples implanted at 77 K or room temperature, while the samples implanted at 180°C remain crystalline. According to the channeling measurements, amorphous layer less than 2000 A thick produced by either 77 K or room-temperature implants are completely recordered by annealing at 750°C for 10min, while the post-anneal residual disorder of thicker layers is linearly dependent on the initial amorphous layer thickness. After annealing, samples implanted at 180°C have higher sheet carrier concentrations and mobilities but considerably broader carrier concentrations than samples similarly implanted at either 77 K or room temperature, even when the amorphous layers in the latter samples are completely recordered. It is considered that for most applications heated implants should be used to avoid the formation of amorphous layers. Interband recombination in doped GaAs. MACIEJ BUGAJSK! and ANDRZEJ M. KONTKIEWICZ. Electron. Technol. 15, 49 (1982). The luminescence spectra of heavily-doped GaAs are calculated in terms of the van Roosbroeck-Shockley detailed balance principle [1]. Unlike the usual approach to this problem, using the experimental absorption curve ct(h~o), the theoretical frequency dependence of an absorption coefficient in a doped semiconductor which had been reported earlier [2, 3] has been employed. The applicability of the detailed balance principle is also discussed. Process modeling of phosphorus diffusion in silicon--a new model. G. ERANNA and D. KAKATI. Solid St. Technol. 116 (December 1984). A new process model for phosphorus diffusion into silicon is proposed. It is based on the concept that the phosphorus profile can be fitted using two
On the semi-insulating polycrystalline silicon resistor. M1NGKWANG LEE and CHIH-YUAN LU, KuN-ZEN CHANG and CnlNTAV Sum. Solid-St. Electron. 27, 995 (1984). The n p neutralization reaction between phosphorus and boron incorporated in polysilicon fihns was investigated. A process for fabricating semi-insulating polysilicon resistors has been developed. It has been found that the I-V characteristics seem not to be so explicitly related to the resistor length as for resistors fabricated using conventional methods. The activation energies observed are from 0.24 to 0.3t eV which are very small compared with those of polysilicon resistors fabricated using conventional methods, i.e. the temperature coefficient of the semi-insulating polysilicon resistors in the present studies is significantly lowered. Numerical simulation of hot-electron effects on source-drain burnout characteristics of GaAs power FETs. F. A. BUOT and K.J. SLEGER.Solid-St. Electron. 27. 1067 (1984). A High Speed Semiconductor Device Analysis (HISSDAY) computer program, based on the energy transport model, is used to numerically analyze various GaAs FET structures to gain physical insights and to establish potential design criteria for minimization of burnout phenomena. A major finding is the relationship between the spatial distribution of hot electrons in the gate-drain region and the degree of burnout tolerance. FET structures which effectively prevent hot electrons from reaching the drain edge demonstrate high burnout power. Recessed-gate structures alone do not prevent hot electrons from reaching the edge of the drain electrode and therefore cannot prevent or minimize source-drain burnout. Gate-todrain surface-field considerations also indicate that whereas recessed-gate designs improve gate-drain avalanche breakdown voltages, recessed-channel and n + ledge designs tend to degrade gate-drain avalanche breakdown voltages. The combination of recessed gate and n + ledge or recessed channel (double-recess structure) is a central feature to designs which minimize both gate-drain avalanche and source-drain burnout. A feedback-system model of the source-drain burnout mechanism for all FET slructures simulated is proposed. Significant source-drain burnout voltage degradation at large gate biases near pinchoff is clarified in terms of the strong sensitivity of the hot electron energy-density distribution to channel opening in conventional MESFETs. Calculation of the extended-state electron mobility in hydrogenated amorphous silicon. M. SILVER and E. SNOW' Solid St. Commun. 54, 15 (1985). In a recent paper, Marshall and his collaborators conclude that the extended-state electron mobility in hydrogenated amorphous silicon is 10 20 cm2/V-s. This deduction is based on experimental results indicating the demarcation level does not exceed 0.14 eV, in disagreement with conventional multiple-trapping theory. In this paper, we show that the data can be understood without modification of the existing theory, and reiterate that the observed drift mobility and density of localized states require an extended-state electron mobility in excess of 100 cmZ/V s.