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Application of the ferroelectric materials to ULSI memories
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applied
surface science ELSEVIER
Applied Surface Science 113/l
14 (1997) 656-663
Application of the ferroelectric materials to ULSI memories Yasuo Tarui *, Tadahiko Hirai I, Kazuhiro Teramoto, Hiroshi Koike, Kazuhito Nagashima Waseda University, 3-4-l Ohkubo, Shinjuku-ku, Tokyo 169, Japan
Abstract Memory is essential to electronic data processing and continuous efforts are being made to develop improved memory devices. In the era of VLSI, difficulties have arisen with respect to storage capacitance, which must be kept to a certain value while the device dimensions are reduced. This has prompted the adoption of complicated structures like the trench or stack, causing the number of process steps to be increased. The use of high dielectric constant materials has been researched for the extension of DRAM development. Recently, the development of the memories which use the polarization reversal current of the ferroelectric material is rapidly progressing because it enables high speed nonvolatile memory action which generally needed in recent electronic systems. These memories will replace a large portion of the existing memory systems in the near future. However, this is not a perfect solution to the problem, because they are not in accordance with the scaling rule. In this paper, it is shown that ferroelectric memories using the field effect current of a semiconductor by the remanent polarization of the ferroelectric material are in accordance with the scaling rule. The first experimental verification of the non-volatile memory action was reported by Moll and Tarui in 1963 [I]. This basic memory action has been successively used in MFS (metal-ferroelectric-semiconductor) transistors. The ferroelectric memories are nonvolatile and are expected to be high-speed devices, making them suitable for universal applications. However, it is necessary to optimize the interface between the semiconductor and ferroelectric material. Experiments for the prospective devices using CeO, or Ce,Zr(, _ , ,O, as the buffer insulator layers of the MFIS (metal-ferroelectric-insulator-semiconductor) transistors are described.
1. Introduction One of the important problems of the DRAM development for higher integration exist on the storage capacitance of the DRAM. According to the first-order scaling theory [2], capacitance decreases to 1/K when dimensions are decreased by l/K. This problem of capacitance for DRAMS, that the capacitance value must be kept almost the same while cell area is reduced, leads to three-dimensional
* Corresponding author. ’ Permanent Address: Asahi Chemical Industry Co., 2- 1 Samejima, Fuji-City, Shizuoka Pref., 416 Japan. 0169.4332/97/$17.00 Copyright PI1 SO1 69.4332(96)00963-4
structures which require increases in the number of process steps needed to fabricate chips. One way to decrease the capacitance area is use of a material with a high dielectric constant. The Ta,O, dielectric layer seems to have reached the stage of practical use. The ratio of its dielectric constant to that of SiO,, however, is only large enough for one higher generation of DRAM. Typical materials being studied in the effort to create a material with a higher dielectric constant are SrTiO, and (Ba, Sr)TiO,. With those materials, equivalent SiO, thickness less than 10 A is reported. These countermeasures will extend the integration of the DRAM a few more generations but cannot escape
0 1997 Elsevier Science B.V. All rights reserved.
651
Y. Tarui et al. /Applied Swface Science 113 / 114 (I 997) 656-663 P
PS
?
fF
W=lmm
Pr
EC
E
Fig. 1. The polarization material.
versus
electric
field of a ferroelectric Fig. 3. Experimental ferroelectric material.
from the restriction of the scaling rule. The ferroelectric memories mainly mentioned in this paper are free from the restriction of the first order scaling rule. The ferroelectric memories are also expected to meet many needs of the recent development of VLSI; low power nonvolatile operation for portable and general use, low voltage nonvolatile memory for embedded memory of microcontrollers or system LSIS.
2. The first ferroelectric memory The first experimental verification of a ferroelectric memory was reported by Moll and Tarui in 1963 from Stanford University [I]. The primary aim of this device was for application as a variable-gain component for an adaptive system: which is the origin of the neural system. The basic idea of this device is to perform the function of memory in a ferroelecttic material and to control the field effect conductance of a semiconductor by the remanent polarization of the ferroelectric material as shown in Figs. 1 and 2.
r
L
Fig. 2. Principle of the ferroelectric
device
using
on a
At that time, the combination of the single-crystal ferroelectric material with a deposited semiconductor thin film was selected because there was already more experience with semiconductor thin films than with ferroelectric thin films. The single-crystal ferroelectric material TGS (trigrycine sulfate) was therefore used and a CdS thin-film transistor was constructed on TGS as shown in Fig. 3. With the experimental device shown in Fig. 3 the nonvolatile memory action was clearly observed, but the effective mobility calculated from the memory action was about 0.01 cm’/V s. On the other hand, the mobility obtained by the field effect transconductance from the upper electrode of the same unit was 1 cm’/V s. The exact origin of the mobility difference was not clear, but it was obvious that a better interface between the semiconductor and ferroelectric material was needed and that the interface needed to be stable. After this experiment, we tried to fabricate a thin film ferroelectric material on silicon as shown in Fig. 4, at the Electrotechnical Laboratory in Tokyo, but this attempt was not successful because of an interface problem.
1
memory.
a thin film transistor
ferroelectric
Fig. 4. Memory structures constructed tric material on a silicon chip.
material
using a rhin film ferroelec-
658
Y. Tarui et al/Applied
Su$ace Science 113/114
3. Short history of ferroelectric memory development After our experiment of the field effect current of a semiconductor by the remanent polarization of the ferroelectric material (we call this type ‘ferroelectric gate type’ hereafter) was reported, there were experiments with various combination of materials with this type of semiconductor thin film structure: tellurium on BaTiO, [3], tellurium on TGS [4] (trigricine sulfate), CdSe on BaTiO, [5], and SnO, on lead zirconate-titanate ceramic [6]. The fabrication and experimental results obtained with the MFS transistor shown in Fig. 4 were first reported in 1974 by Wu, who used bismuth titanate on Si [7]. The direction of the conduction change after polarization of the ferroelectric material, however, was opposite to the expected direction. The origin of this reversal was found to be the injection of electrons and holes from the semiconductor into the ferroelectric material. In 1975 Sugibuchi et al. showed that this injection can be stopped by stacking a bismuth titanate film on a thermal oxide 181. In 1977 Higuma et al. reported that an MFS transistor using a PZT (lead zilconate titanate) and PLZT (lead lantharum zilconate titanate) thin film deposited on single crystal GaAs has fairly good memory hysteresis of the VG-ID characteristics [9]. In the same year, Ito and Tsuchiya reported the effect of traps on the memory characteristics of the MFS transistor [ 101. In 1987 Kenney et al. reported a different approach to nonvolatile memory with one transistor and one ferroelectric capacitor [ 1I]: in this memory the read operation is done by detecting the polarization reversal current (we call this type ‘polarization reversal current type’ hereafter). In 1988 Eaton reported a 256-bit nonvolatile shadow RAM using a thin PZT film as the ferroelectric material [12]. Recently, layered perovskite oxides exemplified by SrBi,Ta,O, are applied to the memory devices of the polarization reversal current type, showing no significant fatigue after lo’* switching cycles and good retention characteristics [ 13,141. Using this material, in 1994 Sumi et al. reported a 256 kb memory operating 3 V and with read/write time of 100 ns [ 151, in 1995 Sumi et al. reported embedded ferroelectric memory for microcontrollers
(1997) 656-663
1161 and in 1996 Koike et al. reported a 1 Mb nonvolatile memory with 60 ns access time [ 171. Returning to the ferroelectric gate type, in 1991 Sinharoy et al. reported an MFS structure using a new material: BaMgF, (BMF) films on silicon [ 181. In 1992 Lampe reported memory devices using these BaMgF, thin films [19]. While those BMF devices displayed good hysteresis windows, their data retention was short. In 1991 Rost et al. reported an ferroelectric gate type MFS transistor using lithium niobate ferroelectric material without an added buffer layer to prevent charge injection from the silicon into the ferroelectric material [20]. In 1994 Nakamura et al. proposed a floating gate structure under the ferroelectric material of the MFS transistor to prevent the charge injection and material mixing at the interface [21,22]. In this transistor PZT is used as the ferroelectric material. PZT thin films formed on Ir/IrO, electrode show no fatigue up to 10” switching cycles. Beside the device fabrication, in 1992 Miller and McWhorter reported a fine computer simulation of memory devices whose gate dielectric is comprised of a stack of dielectric layers with one ferroelectric layer, including the hysteresis due to ferroelectric switching [23]. The switching time for polarization reversal in ferroelectric films of PZT and PLT was measured by Larsen et al. [24], who found that when the area is less than 100 pm’, the switching speed is very close to the 1.8 ns system rise time. This value is quite encouraging for the application of these films in nonvolatile memory devices.
4. Scaling rule of ferroelectric memories Expecting ideal ferroelectric memories to be developed, let us consider here the scaling rule for ferroelectric memories [25]. The qualities of a ferroelectric thin film depend on the thickness of the film, but for simplicity we assume here that the qualities of the ferroelectric film are uniform. Three types of memories using ferroelectric material are considered as in Table 1: I. A memory that detects the polarization reversal current. 2. A DRAM that uses ferroelectric material as a high E material.
Y. Tarui er al. /Applied
Sur$ace Science I I3 / II4
3. A memory transistor with ferroelectric gate.
The changes of the magnitude of the output signal when the dimensions are reduced to l/K are listed in Table 1. For the first type of memory, the polarization reversal current of the ferroelectric material is proportional to the area of the ferroelectric material and invariant with changes in the thickness of the ferroelectric material. For the second type of memory, the output signal is proportional to the area of the capacitance and inversely proportional to the thickness of the ferroelectric material. And for the third type, we need the following simple derivation. The drain current I, of the n-channel MIS transistor is given as the function of the drain voltage V, using the gradual channel approximation: Z./h.& I, =
2L
[(V, - VT)’ - (V, - G, - VD)2]
(1)
(1997) 656-663
assume V, = 0 and the drain current at the pinch off voltage Z,, can be expressed by the current I, at the point of V, = V,. Eq. (1) can thus be simplified to
(2) The relationship between the electric field and the polarization P of the ferroelectric materials is nonlinear, but if we use the ratio between the gate voltage to polarize the ferroelectric material V,, and thickness of the ferroelectric material d, we can express the polarization as a function of the ratio, provided the field history is the same. P=,f
i
;
i
If we assume C,V, = Q can be replaced by P, the current I,, at V, = 0 after V,, is applied is given by
where L and Z are, respectively, the channel length and width, C, is the gate capacitance per unit area, I_Lis the mobility of the electron. For simplicity we
Table I Change in the magnitude of the output signal when the dimensions are reduced to 1 / K
nlemory
methoc
XY l/K
Thickness IiK
(ai ‘olarizatior reversal current
I ‘K2
(cl Ferro electric gate
(4) where A is a constant. If we assume that the output signal is proportional to I,,, the signal is invariant when Z and L are reduced to l/K together and is also invariant when V,, and d are reduced to l/K together. This means that Eq. (3) (a memory with ferroelectric gate) scales in accordance with the scaling rule.
5. Experiment for the prospective device invarient
(b)
DRAM with high P
659
1 K*
K
nvarient
invarient
To make a good ferroelectric gate type transistors it is necessary that the interface between the silicon and ferroelectric material must: 1. Prevent carrier injection at the interface. 2. Prevent intermixing of materials at the interface. 3. Have few or no interface states and traps at the interface. This may require good hetero-epitaxy between the silicon and ferroelectric material. It would be best if we could meet these standards by using a direct interface between the silicon and the ferroelectric material, but this may have less chance because the selection of ferroelectric materials is limited.
660
K Tarui et &/Applied
Surface Science 113/114
(1997) 656-663
Therefore, we are exploring the use of the buffer materials that prevent the carrier injection and intermixing of the material at the interface and that also help to ensure good hetero-epitaxy between the silicon and ferroelectric material. This may be called the MFIS structure. 5.1. CeO, b&her layer For the first attempt, we selected the CeO, films as the buffer layers between the ferroelectric and the Si because CeO, films with a fluorite (CaF2) structure have a lattice constant (a = 5.41 A> well matched to that of Si (a = 5.43 A). The dielectric constant of CeO, is larger than that of SiO, (26 vetsus 3.8) and the lattice constant of CeO, (a = 5.41 A) is comparable to that of perovskite PbTiO, (afi = 5.51 A). Then we expected the epitaxial growth of CeO,(lOO) on Si(100) [26,27]. CeO, films were deposited on n-type Si(100) single crystal substrate by using an ultrahigh-vacuum (UHV) system with an electron beam evaporator and liquid N2 shroud.The main chamber of the UHV system was evacuated with a cryopump, resulting in a base pressure of 2 X 10m9 Torr. The Si(100) substrate was heated to 900°C by a heater. To deposit the CeO, film on n-type Si 2 fl cm substrate, an electron beam evaporator was used to evaporate a 99.9% hot-pressed CeO, tablet. The crystallinity of the deposited CeO, film was monitored by in situ
20
30
40
50
Fig. 6. TEM image PbTiO, /CeO, /Si(lOO)
of the sample.
interfacial
structure
Fig. 5. X-ray diffraction (XRD) pattern and RHEED (reflection high electron diffraction) pattern of the CeOz on Si(100) substrate.
the
reflection high energy electron diffraction (RHEED) and X-ray diffraction (XRD). The results are shown in Fig. 5. Fig. 6 shows an image of the interface structure of a PbTiO,/CeO,/S( 100) obtained by a transmission electron microscope (TEM?. The typical thickness of CeO, deposited was 100 A and there is an intermediate layer, probably silicon dioxide, between the CeO, and Si [28]. The ferroelectric PbTiO, thin film was deposited on the CeO,/Si(lOO) substrate by using the digital CVD (Chemical Vapor deposition) apparatus [26,27,29]. Tetraethyl-lead, Pb(C,H,), and titanium
J
60
2 8 (degree)
of
20.0
30.0
40.0
50.0
60.0
20 (degree) Fig. 7. X-ray CeOz /Si(loO)
diffraction substrate.
(XRD)
pattern
of the PbTiO,
on a
Y. Tarui er al. /Applied Surface Science I13 / 114 CI9971 656-663
isopropoxide, Ti(i-OC,H, I1 [30,3 11, were used as metal precursors of the films and were vaporized in different stainless-steel bubblers, respectively, kept at 1 and 30°C. Film deposition was performed by introducing Pb(C?H,),, Ti(i-OC3H7)4, O? + 0, and N, purge gas alternately into the reactor. Typical deposition temperature was 550°C. During injection of N? purge gas, the pressure of the reactor was I Torr. For observation of crystal structure, the X-ray diffraction (XRD) pattern of PbTiO,/CeO,/Si(lOO) were measured. An example of the results of the measurement is shown in Fig. 7. 5.2. Ce ~Zr(, ~ x,O2 bufer
layer
Although our intention of CeO, buffer was epitaxial growth of CeO,(lOO) on Si(lOO), as shown in Fig. 6, however, CeO, did not deposit epitaxially on Si( 100). YSZ (YzO,-stabilized-ZrO,) is well known to be deposited epitaxially on silicon (100) [32]. We deposited YSZ on Si( 100) and measured XRD and RHEED patterns. The results are shown in Fig. 8, showing good expitaxy. However C-V (capacitance-voltage) characteristics of MOS diode shows hysteresis behavior probably because of movement of oxygen ions through the oxygen vacancies (see for, e.g., Ref. [32]). Then we tried to combine the good hetero-epitaxy of YSZ and good insulating properties of CeO, by replacing Y with Ce: namely Ce,Zr, _.r02(100)/Si(100). Epitaxial Ce.,Zr, _*02
2 8 (degree] Fig. 8. X-ray diffraction (XRD) pattern and RHEED pattern of the YSZ on Si(100) a substrate.
I
20
30
,
.!
!
40
!
50
1
60
2 8 (degreel Fig. 9. X-ray diffraction (XRD) pattern and RHEED pattern of the Ce, Zr, _ ,02 on a Sic 100) substrate.
buffer layers on Si substrate were characterized as gate-oxide films of MFIS-FET and also substrate films for oriented PbTiO, films. Ce,xZr, _,rO, films, which take a fluorite (CaF,) structure, have a lattice (a = 5.20-5.30 A) which is almost the same as CeO,. Furthermore, cerium is one of the materials which stabilize zirconia. Ce,Zr, _*_02 crystal have three types: structures of monoclynic (X = O-O. I), tetragonal (X = 0.1-0.3) and cubic (X = 0.2- 1.O) depending on the concentration of Ce atoms [33]. The large dielectric constant (E N 30) of the Ce rZr, _xO, material means that we can apply sufficient electric field for reversing the polarization of the ferroelectric film in the MFIS structure. Ce,Zr, _.rO? films were deposited on Si(100) single-crystal substrates using the same ultrahighvacuum (UHV) system used for the CeO,. The substrate was heated to 900°C and a 99.8% pure hot-pressed (CeO, jO,,2(Zr0,),,,, tablet was heated using an electron-beam evaporator to deposit the Ce,Zr, __02 film on the substrate. The Si(100) substrate removed neutral oxide film used. The XRD and RHEED patterns of the Ce,Zr,_.O, film on Si(100) are shown in Fig. 9. They indicated that the Ce, Zr, _ r02 film was deposited almost epitaxially on Si(100). Fig. 10 shows the C-V characteristics of the Al/Ce,Zr, _,O/Si(lOO) sample. The bias voltages were swept from -3 V to +3 V while the capacitances were measured. The ferroelectric PbTiO, thin film was deposited on the Ce,Zr ,_.,O?/Si El001 substrate by a digital
662
Y. Tarui et al. /Applied Surface Science I13 / 114 (1997) 656-663 700 600 500 400 300 200 100
(4
0 -4
-3
-2
-1
0
1
2
3
4
Bias [V] Fig. IO. C-V structure.
characteristics
of an AI/Ce,Zr,_~O,/Si(lOO)
chemical vapor deposition (digital CVD) method, as for the CeO, buffer layer. The XRD pattern of the perovskite PbTiO, tilm is shown in Fig. 11. The main peaks are from the perovskite PbTiO,(OOl) and (100) and there are two other peaks; (002) and (200). The X-ray pole figure patterns of a PbTiO,/Ce,Zr, _xO,/Si [lOOI sample was measured. Fig. 12 shows pole figures that were obtained at 2 8 = 31 SS’, 2 8 = 48.75” and 2 13= 47.40”, which correspond, respectively, to the reflections of the (101) perovskite PbTiO,, the (220) tetragonal Ce,Zr,_,O, and the (202) Si substrate. These pole figure patterns indicate the alignment of PbTiO, [lOO]//Ce,Zr, _rO, [lOl]//Si [l lo] or PbTiO, [OOl]//Ce,Zr, _xO, [lOll//Si [llOl, getting near
pole figure patterns of a 12. X-ray Fig. PbTiO, /Ce,Zr, _ ,O? /Si(lOO) sample, corresponding to (a) Si; 31.55”, (b) Ce ,Zr, _ ,O:: 48.75”. (c) PbTiO,; 47.4”, respectively.
to perfect epitaxy. The experiment mization is now under way.
for further opti-
6. Conclusions
20.0
30.0
40.0
50.0
60.0
20 (degree) Fig. 11. X-ray diffraction (XRD) PbTiO, /Ce ,Zr, _ r02 /Si(lOO) structure.
pattern
of
a
The storage capacitance of the DRAM is not in accordance with the scaling rule and makes it more difficult to develop more highly integrated devices. Several countermeasures will be taken, one of which will be to make ferroelectric memories using the field effect of a semiconductor by the remanent polarization of a ferroelectric material. These kinds of memories are in accordance with the scaling rule
Y. Tarui et 01. /Applied
Sufuce
and have the potential of low power high speed nonvolatile memories. Experiments for the prospective devices using CeO, or Ce rZr, _ V02 as the buffer insulator layers of the MFIS transistors are described. Further improvement will require optimization of the interface and ferroelectric material itself. Recently the development of the memories using the polarization reversal current are rapidly progressing. This will enhance the technological advancement of manufacturing of the ferroelectric layers and the technology will be applied to the ferroelectric gate type.
Acknowledgements We thank Professor Iwao Ohdomari and Professor Tadatsugu Ito at Waseda University for supporting our work.
References [I] J.L. Moll and Y. Tarui, Trans. Electron. Devices (Solid-State Res. Conf. Abs.) ED-IO (1963) 338. (21 R.H. Dennard, F.H. Gaensslen, H.-N. Yu, V.L. Rideout, E. Bassous and A.R. LeBlanc, IEEE J. Solid-State Circuits X-9(5) (1974) 256. [3] P.M. Heyman and G.H. Heilmeier, Proc. IEEE 54(6) (1966) 842. [4] S.S. Perlman and K.H. Ludewig, IEEE Trans. Electron. Devices ED-14(12) (1967) 816. [5] G.G. Teather and L. Young, Solid-State Electron. 11 (1968) 521. [6] J.C. Crawford and F.L. English, IEEE Trans. Electron. Devices ED- 16(6) ( 1969) 525. [7] S.Y. Wu. IEEE Trans. Electron Devices ED-21(a) (1974) 499. [a] K. Sugibuchi, Y. Kurogi and N. Endo, Jpn. J. Appl. Phys. 46(7) (1975) 2877. [9] Y. Higuma, Y. Matsui, M. Okuyama, T. Nakagawa and Y. Hamakawa, Proc. 9th Conf. Solid State Devices (1977): Jpn. J. Appl. Phys. 17 (Suppl. 17-I) (1978) 209. [IO] K. Ito and H. Tsuchiya, Solid-State Electron. 20 (1977) 529. [I 11 W.I. Kinney, W. Shepherd. W. Miller, J. Evans and R. Womack, IEDM ‘87 (1987) p. 850. [I21 S.S. Eaton, D.B. Butler, M. Parris, D. Wilson and H. Mc-
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Conf. (1988) p. 130. [I31 T. Mihara, H. Yoshimori, H. Watanabe and C.A-Paz de Araujo. Jpn. J. Appl. Phys. 34.l(9B) (1955) 5233. 1141 C.A-Paz de Araujo. J.D. Cuchiaro, L.D. McMillan. M.C. Scott and J.F. Scott, Nature 374 (1995) 627. [I51 T. Sumi. N. Moriwaki, G. Nakane. T. Nakakuma. Y. Judai. Y. Uemoto, Y. Nagano,S. Hayashi. M. Azuma. E. Fuji. S. Katsu. T. Otauki, L. McMillan, CA-Araujo and G. Kano. Dig. Tech. Papers. IEEE Int. Solid-State Circuits Conf. (1994) p. 268. iI61T. Sumi. M. Azuma. T. Otsuki, J. Gregory and C.A-Paz de Araujo, Dig. Tech. Papers, IEEE Int. Solid-State Circuits Conf. ( 1995) p. 70. fl71 H. Koike. T. Otsuki. T. Kimura, M. Fukuma, Y. Hayashi, Y. Maejima. K. Amanuma, N. Tanabe. T. Matsuki, S. Saito, T. Takeuchi. S. Kobayashi, T. Kunio, T. Hase. Y. Miyasaka, N. Shohata and M. Takada, Dig. Tech. Papers. IEEE Int. SolidState Circuits Conf. (I 996) p. 368. [I81 S. Sinharoy H. Buhay. M.H. Francombe, W.J. Takei. N.J. Doyle. J.H. Rieger, D.R. Lampe and E. Stepke. J. Vat. Sci. Technol. A 9(3) (1991) 409. t191 D.R. Lampe. D.A. Adams, M. Austin. M. Polinsky. J. Dzimianski. S. Sinharoy, H. Buhay. P. Brdbant and Y.M. Liu. Ferroelectrics 133 (1992) 61. [201 T.A. Roat. H. Lin and T.A. Rabson, Appl. Phys. Lett. 59(27) (1991) 3654. [211 Y. Nakao, T. Nakamura, A. Kamisawa and H. Takasu. ISIF ‘94 Proc. (1994). [221 T. Nakamura, Y. Nakdo. A. Kamisawa and H. Takasu. ISIF ‘94 Proc. (1994). J. Appl. Phys. 72(12) 1231 S.L. Miller and P.J. McWhorter. (1992) 5999. [241 P.K. Larsen. G.L.M. Kampschoer. M.J.E. Ulenaera, G.A.C. Spieringa and R. Cuppens, Appl. Phys. Lett. 59(5) (1991) 61 I. 1251 Y. Tarui. Nikkei Microdevices 97 (1993) 83 (in Japanese). 1261 T. Hirai. K. Teramoto. T. Nishi. T. Goto and Y. Tarui, Jpn. J. Appl. Phys. 33-l(9B) (1994) 5219. H. Koike and Y. [271 T. Hirai. K. Teramoto, K. Nagashima. Tarui. Jpn. J. Appl. Phys. 34.l(8A) (1995) 4163. I281 T. Inoue. T. Ohsuna, Y. Obara, Y. Yamamoto, M. Satoh and Y. Sakura, Jpn. J. Appl. Phys. 32-l(4) (1993) 1765. [291 T. Hirai. T. Goto, H. Matsuhashi, S. Tanimoto and Y. Tarui, Jpn. J. Appl. Phya. 32-l(9B) (1993) 4078. [301 T. Katayama. M. Fujimoto, M. Shimizu and T. Shiosaki, Jpn. J. Appl. Phys. 30(9B) (1991) 2189. [311 M. Okadd, S. Takai, M. Amemiya and K. Tominaga, Jpn. J. Appl. Phys. 28(6) (1989) 1030. [32] C. Pellet. C. Schwebel and P. Hesto. Thin Solid Films 175 (1989) 23. [33] E. Tani. M. Yoshimurd and S. Somiya, .I Am. Ceramic Sot. 66 (19831 506.
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applied
surface science ELSEVIER
Applied Surface Science 113/l
14 (1997) 656-663
Application of the ferroelectric materials to ULSI memories Yasuo Tarui *, Tadahiko Hirai I, Kazuhiro Teramoto, Hiroshi Koike, Kazuhito Nagashima Waseda University, 3-4-l Ohkubo, Shinjuku-ku, Tokyo 169, Japan
Abstract Memory is essential to electronic data processing and continuous efforts are being made to develop improved memory devices. In the era of VLSI, difficulties have arisen with respect to storage capacitance, which must be kept to a certain value while the device dimensions are reduced. This has prompted the adoption of complicated structures like the trench or stack, causing the number of process steps to be increased. The use of high dielectric constant materials has been researched for the extension of DRAM development. Recently, the development of the memories which use the polarization reversal current of the ferroelectric material is rapidly progressing because it enables high speed nonvolatile memory action which generally needed in recent electronic systems. These memories will replace a large portion of the existing memory systems in the near future. However, this is not a perfect solution to the problem, because they are not in accordance with the scaling rule. In this paper, it is shown that ferroelectric memories using the field effect current of a semiconductor by the remanent polarization of the ferroelectric material are in accordance with the scaling rule. The first experimental verification of the non-volatile memory action was reported by Moll and Tarui in 1963 [I]. This basic memory action has been successively used in MFS (metal-ferroelectric-semiconductor) transistors. The ferroelectric memories are nonvolatile and are expected to be high-speed devices, making them suitable for universal applications. However, it is necessary to optimize the interface between the semiconductor and ferroelectric material. Experiments for the prospective devices using CeO, or Ce,Zr(, _ , ,O, as the buffer insulator layers of the MFIS (metal-ferroelectric-insulator-semiconductor) transistors are described.
1. Introduction One of the important problems of the DRAM development for higher integration exist on the storage capacitance of the DRAM. According to the first-order scaling theory [2], capacitance decreases to 1/K when dimensions are decreased by l/K. This problem of capacitance for DRAMS, that the capacitance value must be kept almost the same while cell area is reduced, leads to three-dimensional
* Corresponding author. ’ Permanent Address: Asahi Chemical Industry Co., 2- 1 Samejima, Fuji-City, Shizuoka Pref., 416 Japan. 0169.4332/97/$17.00 Copyright PI1 SO1 69.4332(96)00963-4
structures which require increases in the number of process steps needed to fabricate chips. One way to decrease the capacitance area is use of a material with a high dielectric constant. The Ta,O, dielectric layer seems to have reached the stage of practical use. The ratio of its dielectric constant to that of SiO,, however, is only large enough for one higher generation of DRAM. Typical materials being studied in the effort to create a material with a higher dielectric constant are SrTiO, and (Ba, Sr)TiO,. With those materials, equivalent SiO, thickness less than 10 A is reported. These countermeasures will extend the integration of the DRAM a few more generations but cannot escape
0 1997 Elsevier Science B.V. All rights reserved.
651
Y. Tarui et al. /Applied Swface Science 113 / 114 (I 997) 656-663 P
PS
?
fF
W=lmm
Pr
EC
E
Fig. 1. The polarization material.
versus
electric
field of a ferroelectric Fig. 3. Experimental ferroelectric material.
from the restriction of the scaling rule. The ferroelectric memories mainly mentioned in this paper are free from the restriction of the first order scaling rule. The ferroelectric memories are also expected to meet many needs of the recent development of VLSI; low power nonvolatile operation for portable and general use, low voltage nonvolatile memory for embedded memory of microcontrollers or system LSIS.
2. The first ferroelectric memory The first experimental verification of a ferroelectric memory was reported by Moll and Tarui in 1963 from Stanford University [I]. The primary aim of this device was for application as a variable-gain component for an adaptive system: which is the origin of the neural system. The basic idea of this device is to perform the function of memory in a ferroelecttic material and to control the field effect conductance of a semiconductor by the remanent polarization of the ferroelectric material as shown in Figs. 1 and 2.
r
L
Fig. 2. Principle of the ferroelectric
device
using
on a
At that time, the combination of the single-crystal ferroelectric material with a deposited semiconductor thin film was selected because there was already more experience with semiconductor thin films than with ferroelectric thin films. The single-crystal ferroelectric material TGS (trigrycine sulfate) was therefore used and a CdS thin-film transistor was constructed on TGS as shown in Fig. 3. With the experimental device shown in Fig. 3 the nonvolatile memory action was clearly observed, but the effective mobility calculated from the memory action was about 0.01 cm’/V s. On the other hand, the mobility obtained by the field effect transconductance from the upper electrode of the same unit was 1 cm’/V s. The exact origin of the mobility difference was not clear, but it was obvious that a better interface between the semiconductor and ferroelectric material was needed and that the interface needed to be stable. After this experiment, we tried to fabricate a thin film ferroelectric material on silicon as shown in Fig. 4, at the Electrotechnical Laboratory in Tokyo, but this attempt was not successful because of an interface problem.
1
memory.
a thin film transistor
ferroelectric
Fig. 4. Memory structures constructed tric material on a silicon chip.
material
using a rhin film ferroelec-
658
Y. Tarui et al/Applied
Su$ace Science 113/114
3. Short history of ferroelectric memory development After our experiment of the field effect current of a semiconductor by the remanent polarization of the ferroelectric material (we call this type ‘ferroelectric gate type’ hereafter) was reported, there were experiments with various combination of materials with this type of semiconductor thin film structure: tellurium on BaTiO, [3], tellurium on TGS [4] (trigricine sulfate), CdSe on BaTiO, [5], and SnO, on lead zirconate-titanate ceramic [6]. The fabrication and experimental results obtained with the MFS transistor shown in Fig. 4 were first reported in 1974 by Wu, who used bismuth titanate on Si [7]. The direction of the conduction change after polarization of the ferroelectric material, however, was opposite to the expected direction. The origin of this reversal was found to be the injection of electrons and holes from the semiconductor into the ferroelectric material. In 1975 Sugibuchi et al. showed that this injection can be stopped by stacking a bismuth titanate film on a thermal oxide 181. In 1977 Higuma et al. reported that an MFS transistor using a PZT (lead zilconate titanate) and PLZT (lead lantharum zilconate titanate) thin film deposited on single crystal GaAs has fairly good memory hysteresis of the VG-ID characteristics [9]. In the same year, Ito and Tsuchiya reported the effect of traps on the memory characteristics of the MFS transistor [ 101. In 1987 Kenney et al. reported a different approach to nonvolatile memory with one transistor and one ferroelectric capacitor [ 1I]: in this memory the read operation is done by detecting the polarization reversal current (we call this type ‘polarization reversal current type’ hereafter). In 1988 Eaton reported a 256-bit nonvolatile shadow RAM using a thin PZT film as the ferroelectric material [12]. Recently, layered perovskite oxides exemplified by SrBi,Ta,O, are applied to the memory devices of the polarization reversal current type, showing no significant fatigue after lo’* switching cycles and good retention characteristics [ 13,141. Using this material, in 1994 Sumi et al. reported a 256 kb memory operating 3 V and with read/write time of 100 ns [ 151, in 1995 Sumi et al. reported embedded ferroelectric memory for microcontrollers
(1997) 656-663
1161 and in 1996 Koike et al. reported a 1 Mb nonvolatile memory with 60 ns access time [ 171. Returning to the ferroelectric gate type, in 1991 Sinharoy et al. reported an MFS structure using a new material: BaMgF, (BMF) films on silicon [ 181. In 1992 Lampe reported memory devices using these BaMgF, thin films [19]. While those BMF devices displayed good hysteresis windows, their data retention was short. In 1991 Rost et al. reported an ferroelectric gate type MFS transistor using lithium niobate ferroelectric material without an added buffer layer to prevent charge injection from the silicon into the ferroelectric material [20]. In 1994 Nakamura et al. proposed a floating gate structure under the ferroelectric material of the MFS transistor to prevent the charge injection and material mixing at the interface [21,22]. In this transistor PZT is used as the ferroelectric material. PZT thin films formed on Ir/IrO, electrode show no fatigue up to 10” switching cycles. Beside the device fabrication, in 1992 Miller and McWhorter reported a fine computer simulation of memory devices whose gate dielectric is comprised of a stack of dielectric layers with one ferroelectric layer, including the hysteresis due to ferroelectric switching [23]. The switching time for polarization reversal in ferroelectric films of PZT and PLT was measured by Larsen et al. [24], who found that when the area is less than 100 pm’, the switching speed is very close to the 1.8 ns system rise time. This value is quite encouraging for the application of these films in nonvolatile memory devices.
4. Scaling rule of ferroelectric memories Expecting ideal ferroelectric memories to be developed, let us consider here the scaling rule for ferroelectric memories [25]. The qualities of a ferroelectric thin film depend on the thickness of the film, but for simplicity we assume here that the qualities of the ferroelectric film are uniform. Three types of memories using ferroelectric material are considered as in Table 1: I. A memory that detects the polarization reversal current. 2. A DRAM that uses ferroelectric material as a high E material.
Y. Tarui er al. /Applied
Sur$ace Science I I3 / II4
3. A memory transistor with ferroelectric gate.
The changes of the magnitude of the output signal when the dimensions are reduced to l/K are listed in Table 1. For the first type of memory, the polarization reversal current of the ferroelectric material is proportional to the area of the ferroelectric material and invariant with changes in the thickness of the ferroelectric material. For the second type of memory, the output signal is proportional to the area of the capacitance and inversely proportional to the thickness of the ferroelectric material. And for the third type, we need the following simple derivation. The drain current I, of the n-channel MIS transistor is given as the function of the drain voltage V, using the gradual channel approximation: Z./h.& I, =
2L
[(V, - VT)’ - (V, - G, - VD)2]
(1)
(1997) 656-663
assume V, = 0 and the drain current at the pinch off voltage Z,, can be expressed by the current I, at the point of V, = V,. Eq. (1) can thus be simplified to
(2) The relationship between the electric field and the polarization P of the ferroelectric materials is nonlinear, but if we use the ratio between the gate voltage to polarize the ferroelectric material V,, and thickness of the ferroelectric material d, we can express the polarization as a function of the ratio, provided the field history is the same. P=,f
i
;
i
If we assume C,V, = Q can be replaced by P, the current I,, at V, = 0 after V,, is applied is given by
where L and Z are, respectively, the channel length and width, C, is the gate capacitance per unit area, I_Lis the mobility of the electron. For simplicity we
Table I Change in the magnitude of the output signal when the dimensions are reduced to 1 / K
nlemory
methoc
XY l/K
Thickness IiK
(ai ‘olarizatior reversal current
I ‘K2
(cl Ferro electric gate
(4) where A is a constant. If we assume that the output signal is proportional to I,,, the signal is invariant when Z and L are reduced to l/K together and is also invariant when V,, and d are reduced to l/K together. This means that Eq. (3) (a memory with ferroelectric gate) scales in accordance with the scaling rule.
5. Experiment for the prospective device invarient
(b)
DRAM with high P
659
1 K*
K
nvarient
invarient
To make a good ferroelectric gate type transistors it is necessary that the interface between the silicon and ferroelectric material must: 1. Prevent carrier injection at the interface. 2. Prevent intermixing of materials at the interface. 3. Have few or no interface states and traps at the interface. This may require good hetero-epitaxy between the silicon and ferroelectric material. It would be best if we could meet these standards by using a direct interface between the silicon and the ferroelectric material, but this may have less chance because the selection of ferroelectric materials is limited.
660
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Surface Science 113/114
(1997) 656-663
Therefore, we are exploring the use of the buffer materials that prevent the carrier injection and intermixing of the material at the interface and that also help to ensure good hetero-epitaxy between the silicon and ferroelectric material. This may be called the MFIS structure. 5.1. CeO, b&her layer For the first attempt, we selected the CeO, films as the buffer layers between the ferroelectric and the Si because CeO, films with a fluorite (CaF2) structure have a lattice constant (a = 5.41 A> well matched to that of Si (a = 5.43 A). The dielectric constant of CeO, is larger than that of SiO, (26 vetsus 3.8) and the lattice constant of CeO, (a = 5.41 A) is comparable to that of perovskite PbTiO, (afi = 5.51 A). Then we expected the epitaxial growth of CeO,(lOO) on Si(100) [26,27]. CeO, films were deposited on n-type Si(100) single crystal substrate by using an ultrahigh-vacuum (UHV) system with an electron beam evaporator and liquid N2 shroud.The main chamber of the UHV system was evacuated with a cryopump, resulting in a base pressure of 2 X 10m9 Torr. The Si(100) substrate was heated to 900°C by a heater. To deposit the CeO, film on n-type Si 2 fl cm substrate, an electron beam evaporator was used to evaporate a 99.9% hot-pressed CeO, tablet. The crystallinity of the deposited CeO, film was monitored by in situ
20
30
40
50
Fig. 6. TEM image PbTiO, /CeO, /Si(lOO)
of the sample.
interfacial
structure
Fig. 5. X-ray diffraction (XRD) pattern and RHEED (reflection high electron diffraction) pattern of the CeOz on Si(100) substrate.
the
reflection high energy electron diffraction (RHEED) and X-ray diffraction (XRD). The results are shown in Fig. 5. Fig. 6 shows an image of the interface structure of a PbTiO,/CeO,/S( 100) obtained by a transmission electron microscope (TEM?. The typical thickness of CeO, deposited was 100 A and there is an intermediate layer, probably silicon dioxide, between the CeO, and Si [28]. The ferroelectric PbTiO, thin film was deposited on the CeO,/Si(lOO) substrate by using the digital CVD (Chemical Vapor deposition) apparatus [26,27,29]. Tetraethyl-lead, Pb(C,H,), and titanium
J
60
2 8 (degree)
of
20.0
30.0
40.0
50.0
60.0
20 (degree) Fig. 7. X-ray CeOz /Si(loO)
diffraction substrate.
(XRD)
pattern
of the PbTiO,
on a
Y. Tarui er al. /Applied Surface Science I13 / 114 CI9971 656-663
isopropoxide, Ti(i-OC,H, I1 [30,3 11, were used as metal precursors of the films and were vaporized in different stainless-steel bubblers, respectively, kept at 1 and 30°C. Film deposition was performed by introducing Pb(C?H,),, Ti(i-OC3H7)4, O? + 0, and N, purge gas alternately into the reactor. Typical deposition temperature was 550°C. During injection of N? purge gas, the pressure of the reactor was I Torr. For observation of crystal structure, the X-ray diffraction (XRD) pattern of PbTiO,/CeO,/Si(lOO) were measured. An example of the results of the measurement is shown in Fig. 7. 5.2. Ce ~Zr(, ~ x,O2 bufer
layer
Although our intention of CeO, buffer was epitaxial growth of CeO,(lOO) on Si(lOO), as shown in Fig. 6, however, CeO, did not deposit epitaxially on Si( 100). YSZ (YzO,-stabilized-ZrO,) is well known to be deposited epitaxially on silicon (100) [32]. We deposited YSZ on Si( 100) and measured XRD and RHEED patterns. The results are shown in Fig. 8, showing good expitaxy. However C-V (capacitance-voltage) characteristics of MOS diode shows hysteresis behavior probably because of movement of oxygen ions through the oxygen vacancies (see for, e.g., Ref. [32]). Then we tried to combine the good hetero-epitaxy of YSZ and good insulating properties of CeO, by replacing Y with Ce: namely Ce,Zr, _.r02(100)/Si(100). Epitaxial Ce.,Zr, _*02
2 8 (degree] Fig. 8. X-ray diffraction (XRD) pattern and RHEED pattern of the YSZ on Si(100) a substrate.
I
20
30
,
.!
!
40
!
50
1
60
2 8 (degreel Fig. 9. X-ray diffraction (XRD) pattern and RHEED pattern of the Ce, Zr, _ ,02 on a Sic 100) substrate.
buffer layers on Si substrate were characterized as gate-oxide films of MFIS-FET and also substrate films for oriented PbTiO, films. Ce,xZr, _,rO, films, which take a fluorite (CaF,) structure, have a lattice (a = 5.20-5.30 A) which is almost the same as CeO,. Furthermore, cerium is one of the materials which stabilize zirconia. Ce,Zr, _*_02 crystal have three types: structures of monoclynic (X = O-O. I), tetragonal (X = 0.1-0.3) and cubic (X = 0.2- 1.O) depending on the concentration of Ce atoms [33]. The large dielectric constant (E N 30) of the Ce rZr, _xO, material means that we can apply sufficient electric field for reversing the polarization of the ferroelectric film in the MFIS structure. Ce,Zr, _.rO? films were deposited on Si(100) single-crystal substrates using the same ultrahighvacuum (UHV) system used for the CeO,. The substrate was heated to 900°C and a 99.8% pure hot-pressed (CeO, jO,,2(Zr0,),,,, tablet was heated using an electron-beam evaporator to deposit the Ce,Zr, __02 film on the substrate. The Si(100) substrate removed neutral oxide film used. The XRD and RHEED patterns of the Ce,Zr,_.O, film on Si(100) are shown in Fig. 9. They indicated that the Ce, Zr, _ r02 film was deposited almost epitaxially on Si(100). Fig. 10 shows the C-V characteristics of the Al/Ce,Zr, _,O/Si(lOO) sample. The bias voltages were swept from -3 V to +3 V while the capacitances were measured. The ferroelectric PbTiO, thin film was deposited on the Ce,Zr ,_.,O?/Si El001 substrate by a digital
662
Y. Tarui et al. /Applied Surface Science I13 / 114 (1997) 656-663 700 600 500 400 300 200 100
(4
0 -4
-3
-2
-1
0
1
2
3
4
Bias [V] Fig. IO. C-V structure.
characteristics
of an AI/Ce,Zr,_~O,/Si(lOO)
chemical vapor deposition (digital CVD) method, as for the CeO, buffer layer. The XRD pattern of the perovskite PbTiO, tilm is shown in Fig. 11. The main peaks are from the perovskite PbTiO,(OOl) and (100) and there are two other peaks; (002) and (200). The X-ray pole figure patterns of a PbTiO,/Ce,Zr, _xO,/Si [lOOI sample was measured. Fig. 12 shows pole figures that were obtained at 2 8 = 31 SS’, 2 8 = 48.75” and 2 13= 47.40”, which correspond, respectively, to the reflections of the (101) perovskite PbTiO,, the (220) tetragonal Ce,Zr,_,O, and the (202) Si substrate. These pole figure patterns indicate the alignment of PbTiO, [lOO]//Ce,Zr, _rO, [lOl]//Si [l lo] or PbTiO, [OOl]//Ce,Zr, _xO, [lOll//Si [llOl, getting near
pole figure patterns of a 12. X-ray Fig. PbTiO, /Ce,Zr, _ ,O? /Si(lOO) sample, corresponding to (a) Si; 31.55”, (b) Ce ,Zr, _ ,O:: 48.75”. (c) PbTiO,; 47.4”, respectively.
to perfect epitaxy. The experiment mization is now under way.
for further opti-
6. Conclusions
20.0
30.0
40.0
50.0
60.0
20 (degree) Fig. 11. X-ray diffraction (XRD) PbTiO, /Ce ,Zr, _ r02 /Si(lOO) structure.
pattern
of
a
The storage capacitance of the DRAM is not in accordance with the scaling rule and makes it more difficult to develop more highly integrated devices. Several countermeasures will be taken, one of which will be to make ferroelectric memories using the field effect of a semiconductor by the remanent polarization of a ferroelectric material. These kinds of memories are in accordance with the scaling rule
Y. Tarui et 01. /Applied
Sufuce
and have the potential of low power high speed nonvolatile memories. Experiments for the prospective devices using CeO, or Ce rZr, _ V02 as the buffer insulator layers of the MFIS transistors are described. Further improvement will require optimization of the interface and ferroelectric material itself. Recently the development of the memories using the polarization reversal current are rapidly progressing. This will enhance the technological advancement of manufacturing of the ferroelectric layers and the technology will be applied to the ferroelectric gate type.
Acknowledgements We thank Professor Iwao Ohdomari and Professor Tadatsugu Ito at Waseda University for supporting our work.
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