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Assessing fault model and test quality
Microelectronics Journal, VoL 23, No. 4
In his Preface, the author lists the main topics of the book as: • Communication, such as mesh and pyramid algorithms and combinations between them (Chapter 1), orthogonal trees (Chapter 5) and VLSI for matrix-based computations (Chapter 6). • Emerging Technologies, such as optical communication (Chapter 2) and neural networks (Chapters 9 and 10). • Design Environments and Experimentation, such as the analyses of FFT algorithms on specific machines (Chapter 3), shared memory (Chapter 7) and asynchronous systems (Chapter 8). • Applications, including image restoration (Chapter 1), fault-tolerance in systolic arrays (Chapter 4) and computer tomography (Chapter 5). • Algorithm Design, which is covered in most of the chapters. The book is aimed at research courses in areas such as VLSI, DSP and Parallel Processing, and as such it could be very useful. The material is up to date and has been well edited. P. D. Picton
Title: Authors:
Assessing Fault Model and Test Quality K. M. Butler and M. R. Mercer
Publisher:
Kluwer Academic Publishers, Norwell, MA, 1992, 132 pp., ~40.75, US$59.95, Dfl.135.00
This text, produced by authors from Texas Instruments Inc. (KMB) and the University of Texas at Austin (MRM), considers whether the stuck-at fault model, so widely used in digital fault testing, is truly viable, considering the dynamic nature of all switching circuits when in operation. The authors' approach is based on the use of Ordered Binary Decision Diagrams (OBDDs), which form an alternative representation for Boolean functions. The majority of pages of the text, however, deal with the introduction of OBDDs and their application to digital test, rather than assessing stuck-at fault model performance. This includes a full chapter on symmetric binary functions which are a special class of Boolean functions for which OBDDs are particularly applicable. It is not until Chapter 9 onwards of this 12-chapter text that fault model behaviour and controllability/observability analysis are introduced. The final conclusion of this publication is that the stuck-at fault model may not be well-matched to common defects in current IC technologies, but there is no accurate method yet available for measuring test set performance that produces reliable, statistically significant results. In total, therefore, this is a very specialised text, perhaps only of interest to those engaged in digital test R&D activities. It is not a text for generalpurpose use, although it does contain a very useful range of detail. S. L. Hurst
319
In his Preface, the author lists the main topics of the book as: • Communication, such as mesh and pyramid algorithms and combinations between them (Chapter 1), orthogonal trees (Chapter 5) and VLSI for matrix-based computations (Chapter 6). • Emerging Technologies, such as optical communication (Chapter 2) and neural networks (Chapters 9 and 10). • Design Environments and Experimentation, such as the analyses of FFT algorithms on specific machines (Chapter 3), shared memory (Chapter 7) and asynchronous systems (Chapter 8). • Applications, including image restoration (Chapter 1), fault-tolerance in systolic arrays (Chapter 4) and computer tomography (Chapter 5). • Algorithm Design, which is covered in most of the chapters. The book is aimed at research courses in areas such as VLSI, DSP and Parallel Processing, and as such it could be very useful. The material is up to date and has been well edited. P. D. Picton
Title: Authors:
Assessing Fault Model and Test Quality K. M. Butler and M. R. Mercer
Publisher:
Kluwer Academic Publishers, Norwell, MA, 1992, 132 pp., ~40.75, US$59.95, Dfl.135.00
This text, produced by authors from Texas Instruments Inc. (KMB) and the University of Texas at Austin (MRM), considers whether the stuck-at fault model, so widely used in digital fault testing, is truly viable, considering the dynamic nature of all switching circuits when in operation. The authors' approach is based on the use of Ordered Binary Decision Diagrams (OBDDs), which form an alternative representation for Boolean functions. The majority of pages of the text, however, deal with the introduction of OBDDs and their application to digital test, rather than assessing stuck-at fault model performance. This includes a full chapter on symmetric binary functions which are a special class of Boolean functions for which OBDDs are particularly applicable. It is not until Chapter 9 onwards of this 12-chapter text that fault model behaviour and controllability/observability analysis are introduced. The final conclusion of this publication is that the stuck-at fault model may not be well-matched to common defects in current IC technologies, but there is no accurate method yet available for measuring test set performance that produces reliable, statistically significant results. In total, therefore, this is a very specialised text, perhaps only of interest to those engaged in digital test R&D activities. It is not a text for generalpurpose use, although it does contain a very useful range of detail. S. L. Hurst
319