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Bulk properties of very large diameter silicon single crystals
Journal of Crystal Growth 198/199 (1999) 390—398
Bulk properties of very large diameter silicon single crystals W. von Ammon*, E. Dornberger, P.O. Hansson Wacker Siltronic AG, P.O. 1140, D-84479 Burghausen, Germany
Abstract It has been experimentally found that it will be difficult to grow 300 mm or larger diameter crystals with similar quality as for 200 mm or smaller diameter crystals. This phenomenon can be understood within the frame of the Voronkov theory in which the value of the parameter »/G (»"pull rate, G"temperature gradient at the growth interface) determines which type of defect forms in the growing crystal. Due to fundamental technological constraints, the pull rate of silicon single crystals has to be reduced as the diameter increases. For crystal diameters beyond 300 mm, the reduction of pull rate is so large, that »/G(r) (r"radial position) can probably no longer be kept above the critical value C "1.34;10\ cm K\ min\ over the entire crystal volume by the present growth technology. As a result, the defect behavior of the silicon bulk changes. The aggregation of defects is now dominated by excess Si interstitials instead of vacancies and, hence, L-pits (dislocation loops) are observed instead of microvoids. Unless new methods for the suppression of L-pits can be developed, this will seriously challenge the use of polished wafers in very large diameter device manufacturing lines, as L-pits can severely damage the device performance. A promising solution to the defect problem appears to be p#p! epi wafers. 1999 Elsevier Science B.V. All rights reserved. Keywords: Silicon; Crystal; Czochralski; Defects; Large diameter
1. Introduction With every new generation of semiconductor devices, the complexity and functionality of the devices increases and, hence, more transistors per chip are to be integrated [1]. As the number of transistors per chip grows faster than the chip area can be decreased by smaller design rules, the devices in-
* Corresponding author. Tel.:#49 8677 832008; fax:#49 8677 837303; e-mail: [email protected].
crease in area [2]. However, below a certain number of chips per wafer, the production costs rise dramatically and the device industry is forced to changeover to the next larger wafer diameter. Currently, the transition from 200 to 300 mm wafers is prepared and 300 mm wafers are expected to be manufactured in large scale in 3—4 years. In Japan, a research program has been launched to assess the manufacturing of even 400/450 mm wafers to meet the requirements of the information society in 2010 [3,4]. Simultaneously, the shrinking design rules require a thorough understanding and control of
0022-0248/99/$ — see front matter 1999 Elsevier Science B.V. All rights reserved. PII: S 0 0 2 2 - 0 2 4 8 ( 9 8 ) 0 1 1 4 0 - 3
W. von Ammon et al. / Journal of Crystal Growth 198/199 (1999) 390–398
grown-in defects in the silicon base material. Besides oxygen precipitation, the defect behavior of Czochralski grown silicon single crystals is dominated by the aggregation of intrinsic point defects, i.e. vacancies and Si interstitials, during the crystal growth process [5—10]. The clustering of vacancies results in the formation of microvoids (ca. 100 nm) [11,12], which deteriorate the gate oxide integrity in the devices [13,14] thereby limiting the chip yield of the device production lines. Historically, the microvoids were given different names (crystal originated particles (COPs), gate oxide integrity (GOI) defects, light scattering tomography (LST) defects, flow pattern (FP) defects) according to the technique by which they were first revealed [15—22]. Later on, it was recognized that they were one and the same defect [23,24]. A generation of secondary defects is usually not found for microvoids as they do not buildup sufficient stress in the surrounding crystal lattice. The agglomeration of Si interstitials on the other hand, generates dislocation loops (so-called L-pits) [25], which, due to their large extension (several lm), cause so severe damage to the devices that they often cannot be overcome by invoking the built-in redundancy. With respect to crystal growth technology, it has been shown that the production of very large diameter crystals faces tremendous technological challenges [26,27]. A fundamental constraint arises from the fact that the dissipation of latent heat as well as the increasing thermal stress in the growing crystal limit the maximum pull rate, e.g. for a given thermal stress, the pull rate of a 300 mm crystal is only half of that for a 200 mm crystal (Fig. 1). Experimentally, it was found that a 300 mm crystal may crack during growth, when the calculated thermal stress increases beyond ca. 60 MPa at the point of highest stress.. For 150 and 200 mm crystals, this value seems to be somewhat higher. Furthermore, the smaller surface to volume ratio reduces the efficiency of radiant heat loss, which, in conjunction with the lower pull rate, considerably slows down the cooling rate of the growing crystal. The present paper discusses the impact of the lower pull rate on the radial defect distribution in the bulk of very large diameter wafer as well as the
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Fig. 1. Calculated maximum thermal stress in growing CZ crystals for a given hot zone type depending on the crystal diameter; 䢇 denotes the behavior of the thermal stress as a function of the crystal diameter, when the pull rate » is kept constant and 䊏 describes how the pull rate » has to be varied with increasing crystal diameter to keep the thermal stress constant. The large ellipses denote calculated values based on experimental process conditions where the crystals cracked during growth.
effect of the longer thermal history on the defect density and size distribution. It will also be shown that the advantages of epi wafers become more apparent as the wafer diameter increases.
2. Radial defect distribution It has long been known, that the pull rate of growing silicon crystals has a major influence on the radial and size/density distribution of the various defect types [14,25,28—33]. At high pull rates, vacancy related defects (microvoids) dominate over the entire crystal volume. At medium pull rates, oxidation induced stacking faults (OSF) grow in a small ring-like region at the rim of the crystal. If the pull rate is lowered further, the ring diameter shrinks and, at the same time, L-pits are detected in the area outside the OSF ring. Thus, the OSF ring obviously marks a boundary between vacancy and Si interstitial type defects. Below a critical pull rate, the OSF ring disappears and L-pits are observed in the entire crystal volume only. Up to now, nearly all crystals are grown at high pull rates in the microvoid regime, as these defects are less harmful or can be even annihilated in high temperature
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device processes. For 300 mm crystals, however, it appears to be difficult to obtain only vacancy related defects over the entire crystal volume [26]. For even larger diameter crystals, this problem is expected to aggravate. A theoretical explanation of this experimental fact can be derived from Voronkov’s theory [28], which is widely accepted today. According to his approach, the parameter »/G (»"pull rate, G"axial temperature gradient at the growth interface) determines whether vacancy or Si interstitial aggregates are formed in the growing crystal. If »/G'C , vacancies dominate, which results in the formation of microvoids. For »/G(C , Si interstitials are in excess over vacancies and, therefore, L-pits grow. The crossover between excess vacancies and Si interstitials and, hence, between microvoid and L-pit formation occurs, where »/G"C holds. As G is not constant across the crystal diameter, the dynamics of the excess vacancy/Si interstitial boundary can be described by the equation »/G(r)"C , r being the radial posi tion. G(r) increases from the center to the crystal rim and has to be calculated at the growth interface, as its qualitative behavior already changes to a decreasing function a few centimeters behind the interface [30]. In an asymptotic analysis by Sinno et al. [9,34], a theoretical expression for C was derived which is in good accordance with the experimental value. Their calculations also confirmed that the vacancy/Si interstitial crossover point indeed behaves according to the above equation. The calculated radial vacancy and Si interstitial distributions (before the onset of point defect agglomeration) are shown in Fig. 2. Si interstitials are almost completely eliminated in the inner region, whereas, beyond the vacancy/Si interstitial cross over, the vacancies are rapidly depleted towards the crystal rim. As the pull rate of larger diameter crystals has to be lowered due the above mentioned technological constraints, the value of »/G(r) can no longer be kept above C , unless G is decreased accordingly. G is essentially determined by the thermal environment of the growing crystal, which, in turn, is fixed by the hot zone design. However, » as well as the lateral temperature gradient G at the melt surface
are coupled to G, i.e. if G decreases, G must be
Fig. 2. Radial variation of self-interstitial (C ) and vacancy (C ) ' 4 concentration in a Cz crystal at a temperature of 1200°C for different pull rates.
reduced to keep » at least constant due to the energy balance at the growth interface. But, if G drops below a critical value, it is not possible
anymore to grow crystals of a cylindrical shape, as the growing crystal will tend to form facets. This is not only intolerable for geometrical reasons, but it also destabilizes the whole growth process. Thus, the coupling between G and G sets a lower limit
for G. For current 300 mm crystals, the limited reduction of G cannot compensate the lower pull rate to the extent that »/G(r) can be kept above C over the entire crystal diameter, which results in the formation of L-pits in the outer region close to the crystal rim. However, it seems that this problem can be remedied for future 300 mm growth processes by a proper hot zone design. The use of magnetic fields is presently under investigation, too. With regard to 400 mm and larger diameter crystals, it is doubtful whether a solution can be found in this way. As shown in Fig. 3, the maximum pull rate is expected to drop below the minimum pull rate where a OSF ring and, hence, microvoids are still observable. Thus, the defect behavior of larger diameter crystals will eventually be completely determined by excess Si interstitials. Unless new methods are developed to effectively suppress the L-pit formation, the bulk quality of very large diameter wafers may not be acceptable to the device manufacturers.
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Fig. 3. 䉬 denotes the maximum pull rate limited by the critical thermal stress (calculated for a given hot zone type) at which the crystal is likely to crack during growth. The shaded area shows the pull rate range within which an OSF ring appears on the wafer.
3. Defect density and size distribution An important parameter for the control of grown-in defects is also the thermal history of the as grown crystal. While it has only a negligible influence on the radial distribution of defects (as long as crystals are grown with a constant or smoothly varying pull rate), detailed investigations revealed a strong effect of the crystal cooling rate on the defect density and size [35,36]. If the dwell time in the temperature range between 900°C and 1050°C is considered only, one obtains a simple empirical relation between the void density N and the dwell time t (Eq. (1)): N "Ae\ \R,
(1)
with A being a constant. Computer calculations which simulate the vacancy aggregation, reproduce the above relation rather well. They also confirm that the growth of voids is most relevant in the temperature range 1050—900°C and that the average void size increases with longer dwell times and vice versa. In a recent paper, Voronkov et al. [36] published a theoretically derived formula which also fits the experimental data quite well. As the cooling rate of very large diameter crystals is considerably slower than for standard 200 mm crystals
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Fig. 4. Temperature profile along the axes of 150, 200, 300 and 400 mm diameter Czochralski silicon crystals grown in similar hot zones.
(Fig. 4), the respective average void size should increase, whereas the void density decreases. The impact of the thermal history on the L-pit density/size distribution is currently investigated, but data are only scarcely available up to now. Unlike voids which can be annihilated by a high temperature treatment (e.g. hydrogen or argon annealing above 1000°C or thermal oxidation) [37,38], L-pits appear to be rather stable. Aggregation models, which would allow to simulate the formation of L-pits are currently developed, but results have not yet been published. A prediction of the L-pit density/size distribution with increasing crystal diameter is therefore rather difficult. Furthermore, the size of the actual Si interstitial aggregate is obscured by the generation of secondary defects like dislocation loops which hinders the verification of simulation results. Consequently, we will focus on vacancy defects in this paper. According to the present experience with vacancy defects, the lower defect density improves the gate oxide integrity despite the larger defect size. However, numerous investigations are currently carried out to reduce the residual defect density much further in order to meet the future quality requirements of the device manufacturers. In this case, larger defects are unfavorable as their dissolution requires high temperature treatment which should be avoided for large diameter wafers.
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4. OSF ring Owing to the small »/G value of the present 300 mm growth processes, the crossover between vacancies and Si interstitials usually occurs at a radial position r(R (R"crystal radius) for 300 mm crystals. Consequently, the formation of ring like distributed OSFs is observed. Most device manufacturers, however, specify very low OSF densities which would render those wafers useless. Slow growth processes which would shrink the OSF ring diameter to zero, are no solution due to the L-pit formation. A viable way may be the growth of low oxygen crystals, as low oxygen concentrations are known to suppress the generation of OSFs. A theoretical explanation of this phenomenon may be derived from a recent analysis of Voronkov et al. [36]. According to their approach, the OSF ring develops close to the vacancy/Si interstitial crossover, but slightly on the vacancy rich side. In this narrow region, a large vacancy supersaturation builds up during crystal cooling to temperatures below 1000°C, because the initial vacancy concentration at this radial position has already dropped below the value where vacancy aggregates are formed. Thus, residual vacancies are not consumed by growing void nuclei in this area. As oxygen precipitation is strongly enhanced by a vacancy supersaturation, the first oxygen nuclei are formed at comparatively high temperatures in this narrow region and, hence, the oxygen precipitates grow to sizes, where they can generate OSFs during subsequent wafer oxidation. Low oxygen contents, on the other hand, decrease the oxygen nucleation temperature and, therefore, allow to reduce the precipitate size below the critical value. For many device processes, however, the oxygen content must be high enough to ensure sufficient internal gettering capability of the silicon bulk [39]. Internal gettering may be even more important for 300 mm and larger wafers than for smaller wafers as external gettering on the wafer backside is probably insufficient. Due to the lower process temperatures and reduced cycle times, metallic impurities cannot diffuse far enough to reach the wafer backside. In addition, 300 mm wafers will be double side polished which makes it very difficult to integrate the deposition of a gettering backside layer in the
wafer manufacturing process. Furthermore, the higher susceptibility of very large wafers to slippage during thermal wafer processing actually calls for higher oxygen contents, too. Crystal hardening by nitrogen doping as often applied to crystals grown by the floating zone technique is not recommended for Cz crystals as the presence of nitrogen changes the oxygen precipitation and generates OSFs. In addition, its very small segregation coefficient yields very inhomogeous axial nitrogen profiles in Cz crystals. Thus, it is questionable, whether most device manufacturers can really live with low oxygen material.
5. Oxygen precipitation The crossover between excess vacancy and Si interstitials from the center to the crystal rim in 300 mm crystals also has a strong impact on the radial behavior of oxygen precipitation [40]. In contrast to vacancies, Si interstitial supersaturation retards the nucleation of oxide precipitates, which results in a notable suppression of oxygen precipitation in the outer region (Fig. 5). This may result in insufficient gettering at the periphery of the wafer. For even larger diameter crystals, which are probably entirely Si interstitial rich, the radial precipitation behavior becomes homogeneous again, but, due to the retardation of oxide precipitate nucleation, a higher oxygen content is needed to observe a notable oxygen precipitation. Up to now, the precipitation behavior of Si interstitial rich material is not well investigated as it is not used in the device lines. In vacancy rich crystals, nuclei formation of oxygen precipitation is known to essentially occur at temperatures below 800°C (for Si interstitial rich material the temperature range is expected to be even lower) [41]. Computer simulation of the crystal cooling behavior show, that the cooling profile as a function of time is dependent on the axial position [42], which results in an axially inhomogeneous oxygen precipitation. The larger the crystal diameter, the more pronounced this effect will be and the larger the crystal fraction that will be affected. Although, improvements may be possible by a proper adjustment of process parameters
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Fig. 5. Radial oxygen concentration profile of a 300 mm crystal before (䉱) and after a heat treatment (780°C, 3 h and 1000°C, 16 h in dry oxygen).
and hot zone design, it is likely that wafer annealing to homogenize the precipitation behavior cannot be avoided anymore.
6. Epi wafers The use of epi wafers has been common for the production of microprocessors and other high value logic devices, whereas DRAM manufacturers stay with the significantly cheaper polished wafers due to fierce price competition. With the step to 300 mm or larger diameters, the price ratio between epi and polished wafers is expected to fall, as the cycle time increase of single wafer epi reactors will be relatively moderate. The production costs for polished wafers, on the other hand, are likely to rise significantly. Hence, the incentive to use epi wafers will grow. Besides advantages with respect to the cell design (e.g. better latch up immunity) and a somewhat simpler device process (less process steps), epi wafers offer several attractive properties. The surface layer is nearly free of defects. Although, very recent investigations revealed defects of very low density in the epi layer which are probably minute vacancy clusters [43], they are usually annihilated in the current device processes and, therefore, were of no
concern up to now. Consequently, epi wafers provide excellent gate oxide quality in conjunction with very low levels of light point defects (COPs). There has been concern in the past, that bulk defects of the substrate may grow into the rather thin epi layer of future devices and deteriorate the epi layer quality. This may indeed happen for substrates that contain L-pits. In Fig. 6a it is shown that the L-pits at the periphery of the p! substrate clearly generate defects in the epi layer. Whether or not these defects can be avoided by a proper adjustment of the epi deposition process is presently investigated. A satisfactory remedy of this problem is important, as, otherwise, the above discussed L-pit problem of very large diameter polished wafers cannot be solved by a p!p! epi wafer. A failure of this concept may particularly hit those device manufacturers who have been using polished wafers so far and, therefore, cannot easily adjust their cell design to the standard p#p! epi wafers. As shown in Fig. 6b, the L-pit problem is not observed for p#p!wafers. This may be related to the experimental finding that the vacancy defect region shrinks as a function of the boron dopant concentration and, finally, disappears at ca. 10 at/cm (ca. 10 )cm) [44]. The high boron concentration obviously suppresses the L-pit formation,
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In addition, the high boron concentration has a favorable gettering effect on metallic impurities like Fe [45]. The higher solubility of Fe in the p# substrate due to the Fe—B pair formation depletes residual Fe atoms in the epi layer and traps them in the p# substrate. Moreover, since no OSF ring has to be taken care of, the oxygen content of the crystals can be well in the precipitation range. As a result, p#p! epi wafers also provide superior gettering capability in the device processes. Finally, the high boron concentration also has a notable hardening effect, which makes the wafers less susceptive to slippage in thermal processes.
7. Summary
Fig. 6. (a) Defect distribution on the surface of a p!p! epi wafer measured by light scattering in the dark field narrow mode (surfscan SP1, Tencor Instruments); (b) The same measurement for a p#p! epi wafer.
too, which yields a substrate free of intrinsic point defect aggregates. Thus, the standard p#p! epi wafer looks very promising to offer a solution to the L-pit problem. The defect suppressing effect of the high boron concentration has not yet been understood.
The present status of the experimental and theoretical 300 mm investigations reveals that it is difficult with the current growth technology to grow 300 mm crystals which contain only vacancy aggregates as residual defects over the entire crystal volume. This is a consequence of the fact that the pull rate » has to be lowered with increasing crystal diameter whereas the axial temperature gradient G cannot be decreased accordingly to keep the parameter »/G(r) above the critical value C over the entire crystal radius. Hence, a crossover between excess vacancy and Si interstials occurs which results in the formation of OSFs near the radial position of the vacancy/Si interstitial crossover and L-pits at the wafer periphery. With future 300 mm growth processes which are under development, it is likely that crystals which contain vacancy defects only can be grown again. However, crystals of larger diameters are expected to have Si interstitials in excess and, therefore, the L-pit and OSF ring problem will aggravate. While a low oxygen content can suppress the formation of OSFs, it has no effect on the L-pits. It is also doubtful whether or not all device manufacturers could live with the required low oxygen content. If no technological solution can be found to this problem, the use of polished very large diameter wafers may be seriously challenged as all trials to run smaller wafers with this defect type
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through existing device lines were not successful in the past. Up to now, the p#p! epi wafer seems to be the 300 mm wafer of choice as, on one hand, the cost ratio between epi and polished wafers decreases with increasing wafer diameter and, on the other hand, the p#p! epi wafer is nearly free of defects over the entire wafer area. p!p! epi wafers, which are favored by those device manufacturers who have developed their cell design on polished wafers, will probably be no solution, if L-pits in the substrate cannot be eliminated. The p#p! epi wafer also offers superior internal gettering capability and excellent mechanical strength due to the high boron concentration.
Acknowledgements The authors are greatly indebted to U. Lambert for reviewing the manuscript and providing experimental data and to B. Rexer for simulation results. This work has been supported by the Federal Department of Education, Science, Research, and Technology of the FRG under contract number 01 M 2973 A. The authors alone are responsible for the contents of this publication.
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Bulk properties of very large diameter silicon single crystals W. von Ammon*, E. Dornberger, P.O. Hansson Wacker Siltronic AG, P.O. 1140, D-84479 Burghausen, Germany
Abstract It has been experimentally found that it will be difficult to grow 300 mm or larger diameter crystals with similar quality as for 200 mm or smaller diameter crystals. This phenomenon can be understood within the frame of the Voronkov theory in which the value of the parameter »/G (»"pull rate, G"temperature gradient at the growth interface) determines which type of defect forms in the growing crystal. Due to fundamental technological constraints, the pull rate of silicon single crystals has to be reduced as the diameter increases. For crystal diameters beyond 300 mm, the reduction of pull rate is so large, that »/G(r) (r"radial position) can probably no longer be kept above the critical value C "1.34;10\ cm K\ min\ over the entire crystal volume by the present growth technology. As a result, the defect behavior of the silicon bulk changes. The aggregation of defects is now dominated by excess Si interstitials instead of vacancies and, hence, L-pits (dislocation loops) are observed instead of microvoids. Unless new methods for the suppression of L-pits can be developed, this will seriously challenge the use of polished wafers in very large diameter device manufacturing lines, as L-pits can severely damage the device performance. A promising solution to the defect problem appears to be p#p! epi wafers. 1999 Elsevier Science B.V. All rights reserved. Keywords: Silicon; Crystal; Czochralski; Defects; Large diameter
1. Introduction With every new generation of semiconductor devices, the complexity and functionality of the devices increases and, hence, more transistors per chip are to be integrated [1]. As the number of transistors per chip grows faster than the chip area can be decreased by smaller design rules, the devices in-
* Corresponding author. Tel.:#49 8677 832008; fax:#49 8677 837303; e-mail: [email protected].
crease in area [2]. However, below a certain number of chips per wafer, the production costs rise dramatically and the device industry is forced to changeover to the next larger wafer diameter. Currently, the transition from 200 to 300 mm wafers is prepared and 300 mm wafers are expected to be manufactured in large scale in 3—4 years. In Japan, a research program has been launched to assess the manufacturing of even 400/450 mm wafers to meet the requirements of the information society in 2010 [3,4]. Simultaneously, the shrinking design rules require a thorough understanding and control of
0022-0248/99/$ — see front matter 1999 Elsevier Science B.V. All rights reserved. PII: S 0 0 2 2 - 0 2 4 8 ( 9 8 ) 0 1 1 4 0 - 3
W. von Ammon et al. / Journal of Crystal Growth 198/199 (1999) 390–398
grown-in defects in the silicon base material. Besides oxygen precipitation, the defect behavior of Czochralski grown silicon single crystals is dominated by the aggregation of intrinsic point defects, i.e. vacancies and Si interstitials, during the crystal growth process [5—10]. The clustering of vacancies results in the formation of microvoids (ca. 100 nm) [11,12], which deteriorate the gate oxide integrity in the devices [13,14] thereby limiting the chip yield of the device production lines. Historically, the microvoids were given different names (crystal originated particles (COPs), gate oxide integrity (GOI) defects, light scattering tomography (LST) defects, flow pattern (FP) defects) according to the technique by which they were first revealed [15—22]. Later on, it was recognized that they were one and the same defect [23,24]. A generation of secondary defects is usually not found for microvoids as they do not buildup sufficient stress in the surrounding crystal lattice. The agglomeration of Si interstitials on the other hand, generates dislocation loops (so-called L-pits) [25], which, due to their large extension (several lm), cause so severe damage to the devices that they often cannot be overcome by invoking the built-in redundancy. With respect to crystal growth technology, it has been shown that the production of very large diameter crystals faces tremendous technological challenges [26,27]. A fundamental constraint arises from the fact that the dissipation of latent heat as well as the increasing thermal stress in the growing crystal limit the maximum pull rate, e.g. for a given thermal stress, the pull rate of a 300 mm crystal is only half of that for a 200 mm crystal (Fig. 1). Experimentally, it was found that a 300 mm crystal may crack during growth, when the calculated thermal stress increases beyond ca. 60 MPa at the point of highest stress.. For 150 and 200 mm crystals, this value seems to be somewhat higher. Furthermore, the smaller surface to volume ratio reduces the efficiency of radiant heat loss, which, in conjunction with the lower pull rate, considerably slows down the cooling rate of the growing crystal. The present paper discusses the impact of the lower pull rate on the radial defect distribution in the bulk of very large diameter wafer as well as the
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Fig. 1. Calculated maximum thermal stress in growing CZ crystals for a given hot zone type depending on the crystal diameter; 䢇 denotes the behavior of the thermal stress as a function of the crystal diameter, when the pull rate » is kept constant and 䊏 describes how the pull rate » has to be varied with increasing crystal diameter to keep the thermal stress constant. The large ellipses denote calculated values based on experimental process conditions where the crystals cracked during growth.
effect of the longer thermal history on the defect density and size distribution. It will also be shown that the advantages of epi wafers become more apparent as the wafer diameter increases.
2. Radial defect distribution It has long been known, that the pull rate of growing silicon crystals has a major influence on the radial and size/density distribution of the various defect types [14,25,28—33]. At high pull rates, vacancy related defects (microvoids) dominate over the entire crystal volume. At medium pull rates, oxidation induced stacking faults (OSF) grow in a small ring-like region at the rim of the crystal. If the pull rate is lowered further, the ring diameter shrinks and, at the same time, L-pits are detected in the area outside the OSF ring. Thus, the OSF ring obviously marks a boundary between vacancy and Si interstitial type defects. Below a critical pull rate, the OSF ring disappears and L-pits are observed in the entire crystal volume only. Up to now, nearly all crystals are grown at high pull rates in the microvoid regime, as these defects are less harmful or can be even annihilated in high temperature
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device processes. For 300 mm crystals, however, it appears to be difficult to obtain only vacancy related defects over the entire crystal volume [26]. For even larger diameter crystals, this problem is expected to aggravate. A theoretical explanation of this experimental fact can be derived from Voronkov’s theory [28], which is widely accepted today. According to his approach, the parameter »/G (»"pull rate, G"axial temperature gradient at the growth interface) determines whether vacancy or Si interstitial aggregates are formed in the growing crystal. If »/G'C , vacancies dominate, which results in the formation of microvoids. For »/G(C , Si interstitials are in excess over vacancies and, therefore, L-pits grow. The crossover between excess vacancies and Si interstitials and, hence, between microvoid and L-pit formation occurs, where »/G"C holds. As G is not constant across the crystal diameter, the dynamics of the excess vacancy/Si interstitial boundary can be described by the equation »/G(r)"C , r being the radial posi tion. G(r) increases from the center to the crystal rim and has to be calculated at the growth interface, as its qualitative behavior already changes to a decreasing function a few centimeters behind the interface [30]. In an asymptotic analysis by Sinno et al. [9,34], a theoretical expression for C was derived which is in good accordance with the experimental value. Their calculations also confirmed that the vacancy/Si interstitial crossover point indeed behaves according to the above equation. The calculated radial vacancy and Si interstitial distributions (before the onset of point defect agglomeration) are shown in Fig. 2. Si interstitials are almost completely eliminated in the inner region, whereas, beyond the vacancy/Si interstitial cross over, the vacancies are rapidly depleted towards the crystal rim. As the pull rate of larger diameter crystals has to be lowered due the above mentioned technological constraints, the value of »/G(r) can no longer be kept above C , unless G is decreased accordingly. G is essentially determined by the thermal environment of the growing crystal, which, in turn, is fixed by the hot zone design. However, » as well as the lateral temperature gradient G at the melt surface
are coupled to G, i.e. if G decreases, G must be
Fig. 2. Radial variation of self-interstitial (C ) and vacancy (C ) ' 4 concentration in a Cz crystal at a temperature of 1200°C for different pull rates.
reduced to keep » at least constant due to the energy balance at the growth interface. But, if G drops below a critical value, it is not possible
anymore to grow crystals of a cylindrical shape, as the growing crystal will tend to form facets. This is not only intolerable for geometrical reasons, but it also destabilizes the whole growth process. Thus, the coupling between G and G sets a lower limit
for G. For current 300 mm crystals, the limited reduction of G cannot compensate the lower pull rate to the extent that »/G(r) can be kept above C over the entire crystal diameter, which results in the formation of L-pits in the outer region close to the crystal rim. However, it seems that this problem can be remedied for future 300 mm growth processes by a proper hot zone design. The use of magnetic fields is presently under investigation, too. With regard to 400 mm and larger diameter crystals, it is doubtful whether a solution can be found in this way. As shown in Fig. 3, the maximum pull rate is expected to drop below the minimum pull rate where a OSF ring and, hence, microvoids are still observable. Thus, the defect behavior of larger diameter crystals will eventually be completely determined by excess Si interstitials. Unless new methods are developed to effectively suppress the L-pit formation, the bulk quality of very large diameter wafers may not be acceptable to the device manufacturers.
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Fig. 3. 䉬 denotes the maximum pull rate limited by the critical thermal stress (calculated for a given hot zone type) at which the crystal is likely to crack during growth. The shaded area shows the pull rate range within which an OSF ring appears on the wafer.
3. Defect density and size distribution An important parameter for the control of grown-in defects is also the thermal history of the as grown crystal. While it has only a negligible influence on the radial distribution of defects (as long as crystals are grown with a constant or smoothly varying pull rate), detailed investigations revealed a strong effect of the crystal cooling rate on the defect density and size [35,36]. If the dwell time in the temperature range between 900°C and 1050°C is considered only, one obtains a simple empirical relation between the void density N and the dwell time t (Eq. (1)): N "Ae\ \R,
(1)
with A being a constant. Computer calculations which simulate the vacancy aggregation, reproduce the above relation rather well. They also confirm that the growth of voids is most relevant in the temperature range 1050—900°C and that the average void size increases with longer dwell times and vice versa. In a recent paper, Voronkov et al. [36] published a theoretically derived formula which also fits the experimental data quite well. As the cooling rate of very large diameter crystals is considerably slower than for standard 200 mm crystals
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Fig. 4. Temperature profile along the axes of 150, 200, 300 and 400 mm diameter Czochralski silicon crystals grown in similar hot zones.
(Fig. 4), the respective average void size should increase, whereas the void density decreases. The impact of the thermal history on the L-pit density/size distribution is currently investigated, but data are only scarcely available up to now. Unlike voids which can be annihilated by a high temperature treatment (e.g. hydrogen or argon annealing above 1000°C or thermal oxidation) [37,38], L-pits appear to be rather stable. Aggregation models, which would allow to simulate the formation of L-pits are currently developed, but results have not yet been published. A prediction of the L-pit density/size distribution with increasing crystal diameter is therefore rather difficult. Furthermore, the size of the actual Si interstitial aggregate is obscured by the generation of secondary defects like dislocation loops which hinders the verification of simulation results. Consequently, we will focus on vacancy defects in this paper. According to the present experience with vacancy defects, the lower defect density improves the gate oxide integrity despite the larger defect size. However, numerous investigations are currently carried out to reduce the residual defect density much further in order to meet the future quality requirements of the device manufacturers. In this case, larger defects are unfavorable as their dissolution requires high temperature treatment which should be avoided for large diameter wafers.
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4. OSF ring Owing to the small »/G value of the present 300 mm growth processes, the crossover between vacancies and Si interstitials usually occurs at a radial position r(R (R"crystal radius) for 300 mm crystals. Consequently, the formation of ring like distributed OSFs is observed. Most device manufacturers, however, specify very low OSF densities which would render those wafers useless. Slow growth processes which would shrink the OSF ring diameter to zero, are no solution due to the L-pit formation. A viable way may be the growth of low oxygen crystals, as low oxygen concentrations are known to suppress the generation of OSFs. A theoretical explanation of this phenomenon may be derived from a recent analysis of Voronkov et al. [36]. According to their approach, the OSF ring develops close to the vacancy/Si interstitial crossover, but slightly on the vacancy rich side. In this narrow region, a large vacancy supersaturation builds up during crystal cooling to temperatures below 1000°C, because the initial vacancy concentration at this radial position has already dropped below the value where vacancy aggregates are formed. Thus, residual vacancies are not consumed by growing void nuclei in this area. As oxygen precipitation is strongly enhanced by a vacancy supersaturation, the first oxygen nuclei are formed at comparatively high temperatures in this narrow region and, hence, the oxygen precipitates grow to sizes, where they can generate OSFs during subsequent wafer oxidation. Low oxygen contents, on the other hand, decrease the oxygen nucleation temperature and, therefore, allow to reduce the precipitate size below the critical value. For many device processes, however, the oxygen content must be high enough to ensure sufficient internal gettering capability of the silicon bulk [39]. Internal gettering may be even more important for 300 mm and larger wafers than for smaller wafers as external gettering on the wafer backside is probably insufficient. Due to the lower process temperatures and reduced cycle times, metallic impurities cannot diffuse far enough to reach the wafer backside. In addition, 300 mm wafers will be double side polished which makes it very difficult to integrate the deposition of a gettering backside layer in the
wafer manufacturing process. Furthermore, the higher susceptibility of very large wafers to slippage during thermal wafer processing actually calls for higher oxygen contents, too. Crystal hardening by nitrogen doping as often applied to crystals grown by the floating zone technique is not recommended for Cz crystals as the presence of nitrogen changes the oxygen precipitation and generates OSFs. In addition, its very small segregation coefficient yields very inhomogeous axial nitrogen profiles in Cz crystals. Thus, it is questionable, whether most device manufacturers can really live with low oxygen material.
5. Oxygen precipitation The crossover between excess vacancy and Si interstitials from the center to the crystal rim in 300 mm crystals also has a strong impact on the radial behavior of oxygen precipitation [40]. In contrast to vacancies, Si interstitial supersaturation retards the nucleation of oxide precipitates, which results in a notable suppression of oxygen precipitation in the outer region (Fig. 5). This may result in insufficient gettering at the periphery of the wafer. For even larger diameter crystals, which are probably entirely Si interstitial rich, the radial precipitation behavior becomes homogeneous again, but, due to the retardation of oxide precipitate nucleation, a higher oxygen content is needed to observe a notable oxygen precipitation. Up to now, the precipitation behavior of Si interstitial rich material is not well investigated as it is not used in the device lines. In vacancy rich crystals, nuclei formation of oxygen precipitation is known to essentially occur at temperatures below 800°C (for Si interstitial rich material the temperature range is expected to be even lower) [41]. Computer simulation of the crystal cooling behavior show, that the cooling profile as a function of time is dependent on the axial position [42], which results in an axially inhomogeneous oxygen precipitation. The larger the crystal diameter, the more pronounced this effect will be and the larger the crystal fraction that will be affected. Although, improvements may be possible by a proper adjustment of process parameters
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Fig. 5. Radial oxygen concentration profile of a 300 mm crystal before (䉱) and after a heat treatment (780°C, 3 h and 1000°C, 16 h in dry oxygen).
and hot zone design, it is likely that wafer annealing to homogenize the precipitation behavior cannot be avoided anymore.
6. Epi wafers The use of epi wafers has been common for the production of microprocessors and other high value logic devices, whereas DRAM manufacturers stay with the significantly cheaper polished wafers due to fierce price competition. With the step to 300 mm or larger diameters, the price ratio between epi and polished wafers is expected to fall, as the cycle time increase of single wafer epi reactors will be relatively moderate. The production costs for polished wafers, on the other hand, are likely to rise significantly. Hence, the incentive to use epi wafers will grow. Besides advantages with respect to the cell design (e.g. better latch up immunity) and a somewhat simpler device process (less process steps), epi wafers offer several attractive properties. The surface layer is nearly free of defects. Although, very recent investigations revealed defects of very low density in the epi layer which are probably minute vacancy clusters [43], they are usually annihilated in the current device processes and, therefore, were of no
concern up to now. Consequently, epi wafers provide excellent gate oxide quality in conjunction with very low levels of light point defects (COPs). There has been concern in the past, that bulk defects of the substrate may grow into the rather thin epi layer of future devices and deteriorate the epi layer quality. This may indeed happen for substrates that contain L-pits. In Fig. 6a it is shown that the L-pits at the periphery of the p! substrate clearly generate defects in the epi layer. Whether or not these defects can be avoided by a proper adjustment of the epi deposition process is presently investigated. A satisfactory remedy of this problem is important, as, otherwise, the above discussed L-pit problem of very large diameter polished wafers cannot be solved by a p!p! epi wafer. A failure of this concept may particularly hit those device manufacturers who have been using polished wafers so far and, therefore, cannot easily adjust their cell design to the standard p#p! epi wafers. As shown in Fig. 6b, the L-pit problem is not observed for p#p!wafers. This may be related to the experimental finding that the vacancy defect region shrinks as a function of the boron dopant concentration and, finally, disappears at ca. 10 at/cm (ca. 10 )cm) [44]. The high boron concentration obviously suppresses the L-pit formation,
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In addition, the high boron concentration has a favorable gettering effect on metallic impurities like Fe [45]. The higher solubility of Fe in the p# substrate due to the Fe—B pair formation depletes residual Fe atoms in the epi layer and traps them in the p# substrate. Moreover, since no OSF ring has to be taken care of, the oxygen content of the crystals can be well in the precipitation range. As a result, p#p! epi wafers also provide superior gettering capability in the device processes. Finally, the high boron concentration also has a notable hardening effect, which makes the wafers less susceptive to slippage in thermal processes.
7. Summary
Fig. 6. (a) Defect distribution on the surface of a p!p! epi wafer measured by light scattering in the dark field narrow mode (surfscan SP1, Tencor Instruments); (b) The same measurement for a p#p! epi wafer.
too, which yields a substrate free of intrinsic point defect aggregates. Thus, the standard p#p! epi wafer looks very promising to offer a solution to the L-pit problem. The defect suppressing effect of the high boron concentration has not yet been understood.
The present status of the experimental and theoretical 300 mm investigations reveals that it is difficult with the current growth technology to grow 300 mm crystals which contain only vacancy aggregates as residual defects over the entire crystal volume. This is a consequence of the fact that the pull rate » has to be lowered with increasing crystal diameter whereas the axial temperature gradient G cannot be decreased accordingly to keep the parameter »/G(r) above the critical value C over the entire crystal radius. Hence, a crossover between excess vacancy and Si interstials occurs which results in the formation of OSFs near the radial position of the vacancy/Si interstitial crossover and L-pits at the wafer periphery. With future 300 mm growth processes which are under development, it is likely that crystals which contain vacancy defects only can be grown again. However, crystals of larger diameters are expected to have Si interstitials in excess and, therefore, the L-pit and OSF ring problem will aggravate. While a low oxygen content can suppress the formation of OSFs, it has no effect on the L-pits. It is also doubtful whether or not all device manufacturers could live with the required low oxygen content. If no technological solution can be found to this problem, the use of polished very large diameter wafers may be seriously challenged as all trials to run smaller wafers with this defect type
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through existing device lines were not successful in the past. Up to now, the p#p! epi wafer seems to be the 300 mm wafer of choice as, on one hand, the cost ratio between epi and polished wafers decreases with increasing wafer diameter and, on the other hand, the p#p! epi wafer is nearly free of defects over the entire wafer area. p!p! epi wafers, which are favored by those device manufacturers who have developed their cell design on polished wafers, will probably be no solution, if L-pits in the substrate cannot be eliminated. The p#p! epi wafer also offers superior internal gettering capability and excellent mechanical strength due to the high boron concentration.
Acknowledgements The authors are greatly indebted to U. Lambert for reviewing the manuscript and providing experimental data and to B. Rexer for simulation results. This work has been supported by the Federal Department of Education, Science, Research, and Technology of the FRG under contract number 01 M 2973 A. The authors alone are responsible for the contents of this publication.
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