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Characterisation of semiconductor heterostructures by capacitance methods
MEJ 612
Microelectronics Journal Microelectronics Journal 30 (1999) 665–672
Characterisation of semiconductor heterostructures by capacitance methods 夽 D.W. Palmer 1 Physics and Astronomy Subject Group, University of Sussex, Brighton BN1 9QJ, UK
Abstract Investigations of the steady-state and transient electrical capacitance properties of semiconductor heterostructures allow determination of the conduction-band and valence-band energy offsets that occur at the interfaces between materials of different band-gaps and of the presence of carrier-trapping states both in the materials and at the interfaces. For determination of band offsets, the main technique is C–V measurement, i.e. the measurement of the steady-state small-signal (differential) capacitance as a function of applied voltage, and this paper outlines the C–V Intercept and C–V Charge-Profile Methods. Concerning electron and hole trapping in heterostructures, including that in quantum well structures, the presence, concentrations and energy levels of such carrier trapping states can be effectively determined by the C–V–T and DLTS techniques. This paper outlines the principles of these techniques for studying heterostructures, and gives examples of data and results. 䉷 1999 Elsevier Science Ltd. All rights reserved. Keywords: Semiconductor; Heterostructures; Band offsets; C–V Intercept; C–V Charge-Profiling method; Carrier traps
1. Introduction As electrical capacitance is defined in terms of stored charge, it is clear that measurement of the capacitance of a semiconductor structure can give valuable information about its electronic properties. Of very common consideration is the capacitance of a p–n homostructure diode or Schottky diode in the condition of zero or applied reverse bias, and then the measured capacitance is easily related to the total width of the depletion region within the diode. The capacitances of semiconductor diodes are conventionally measured using a capacitance meter by which a small AC voltage, often at 1.0 MHz, superimposed on a DC reversebias voltage, VR, is applied to the diode being investigated, with the meter then evaluating the capacitance from the magnitude of the AC current 90⬚ out of phase with the applied AC voltage; such a measurement gives the small signal (differential) depletion capacitance CVR, defined as dQVR/dVR, where QVR is the stored charge. Then CVR as a function of VR can provide considerable information about the semiconductor diode or structure; this is what is called ‘‘C–V Profiling’’. 夽
Journe´es Maghreb-Europe: Les Materiaux et Leurs Applications aux Dispositifs Capteurs Physiques, Chimiques et Biologiques (MADICA’98). E-mail address: [email protected] (D.W. Palmer) 1 Present Address: Palmer Semiconductor Associates, ‘‘Olde Stone’’, Lydford, Devon EX20 4BH, UK
This paper outlines how C–V Profiling of a semiconductor heterostructure can be used to measure the energy discontinuities (‘‘offsets’’) in the conduction bands and valence bands at the interface between semiconductor heterostructure layers and how C–V Profiling and Capacitance-Mode Deep Level Transient Spectroscopy (the latter employing the capacitance–time transient that occurs upon sudden change of VR) are used to investigate deep electronic states in the heterostructure. 2. The capacitance–voltage measurement method For a Schottky/n-type semiconductor diode or p ⫹⫹/n homostructure diode, almost all of the near-junction region depleted of charge carriers, i.e. the depletion region, lies in the n-type semiconductor. Considering the stored charge QVR in a junction, of cross-sectional area A, across which there is an externally applied reverse voltage VR, the smallsignal capacitance CVR, equal to dQVR/dVR, can be shown [1,2] to be given by the expression 2e1n ND 0:5 1 CVR 0:5A Vbi ⫹ VR or CVR A1n = xd n
2
where e n is the permittivity of the n-type semiconductor, Vbi
0026-2692/99/$ - see front matter 䉷 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(99)00040-3
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profile ND(x) is related to CVR(VR) by the expression 3 e1n A2 ⫺1 dCVR =dVR ⫺1 ND xd n ⫺CVR
4
where, again, xd n x 1n A=CVR :
5
Thus ND(x) can, in principle, be found by measurement of CVR(VR). However, the profile eND(x) found in that way is an effective space-charge profile eN ⫹(x), which is the space charge profile e[ND(x)]chem due to the chemical donors, modified by space charges due to carrier trapping at lattice defects and impurities [2–4]. Furthermore, what the CVR(VR) data give is really the mobile electron concentration n(x), which, because of electron diffusion, is different from N ⫹(x). Also the edge of the depletion-region is not sharp, and so (xd)n is not an exact measure of the real distance x. Therefore the expressions above are often written, in terms of apparent distances x* and apparent carrier concentration profiles n*(x*), as 3 e1n A2 ⫺1 dCVR =dVR ⫺1 n* x* ⫺CVR
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where x* 1n A=CVR
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and where n*(x*) is not identical to n(x). Thus, even for semiconductor homojunctions, accurate interpretation of the CVR(VR) data requires considerable care. 3. Measurement of band offsets Fig. 1. Possible mutual arrangements of the valence and conduction bands of the two materials of a semiconductor heterostructure; the arrangements (a)–(d) are usually called broken-gap, staggered, staggered and straddled respectively.
is the built-in (‘‘diffusion’’) potential of the junction (dependent on the Fermi energies of the two materials), ND is the donor concentration in the n-type semiconductor, here assumed spatially uniform, and (xd)n is the depletion region width. For example, a 1 mm 2 diode of GaAs having ND equal to 1 × 10 15 cm ⫺3 has a capacitance close to 30 pF for VR equal to 10 V. From the expression (1) we have ⫺2 CVR
2 Vbi ⫹ VR : e 1n N D A 2
3
⫺2 as a function of VR for Therefore, in a graphical plot of CVR ⫹⫹ a Schottky/n-semiconductor or p –n diode, the linear data extrapolated to forward voltage give an intercept on the voltage axis equal to the potential Vbi. The slope of the data allows the value of ND to be determined. For the case where the donor concentration ND is not necessarily uniform with respect to distance x in the semiconductor, it can be shown that the concentration–distance
3.1. Introduction Fig. 1 shows possible mutual arrangements of the conduction bands and valence bands for a double layer heterostructure, for which it is assumed that the energy gaps Eg1 and Eg2, of the two semiconductors comprising the heterostructure, are different in magnitude. The analysis in the present paper denotes the energy discontinuities, DEv and DEc of the valence band and conduction band respectively, as positive for the ‘‘straddled’’ arrangement shown as (d). Then, Eg2 ⫺ Eg1 DEg DEv ⫹ DEc :
8
For a heterostructure diode, the energy band discontinuities (the ‘‘band offsets’’) at the junction between the dissimilar semiconductors can be determined by two C–V methods, closely related to that given above for a homostructure diode. Detailed description of the two methods has been previously published [5], and only the main features of the procedures, here called the ‘‘Intercept Method’’ and the ‘‘Charge-Profiling Method’’, are given in this paper. The labelling convention for the two semiconductors of the heterostructure is that a lower-case letter p or n is used to indicate the semiconductor type of the material having the smaller energy-bandgap, and, correspondingly, that P or N is used for the semiconductor of larger band-gap.
D.W. Palmer / Microelectronics Journal 30 (1999) 665–672
Fig. 2. C–V data [8] for the lattice-matched combination pGa0.77In0.23As0.20Sb0.80/N-GaSb. A value of 0.335 ^ 0.050 eV for DEc was found by using the intercept value of 0.720 ^ 0.030 V, the free hole concentration of 1.2 × 10 16 cm ⫺3 in the GaInAsSb (obtained from the slope of the straight line through the points) and the known magnitude (1.0 ^ 0.2 × 10 18 cm ⫺3) of the free electron concentration in the GaSb. The inset picture shows the I–V data for the diode.
3.2. The intercept method for band-offset determination 3.2.1. Using anisotype (p–N or P–n) heterojunctions By considering the band diagrams for a p-semiconductor and an N-semiconductor before contact and after contact at zero applied bias, it can be shown [5,6] that the energy change eVbi corresponding to the built-in (diffusion) potential Vbi when the two materials are in contact is given by eVbi DEc ⫹ Ec;p ⫺ EF;p ⫺ Ec;N ⫺ EF;N
9
where (Ec,p ⫺ EF,p) is the energy difference between the conduction band edge and the Fermi energy for the p-semiconductor and (Ec,N ⫺ EF,N) is the corresponding energy difference for the N-semiconductor. Thus the conduction-band offset energy is given by the expression h i DEc eVbi ⫺ kB T loge Nc;p =Nc;N · nN;0 =np;0
10
where, for the respective p- and N-type semiconductors, Nc,p and Nc,N are the effective densities of state of the conduction bands and np,0 and nN,0 are the free electron concentrations in the zero-field condition. Therefore DEc can be found if eVbi, np,0 and nN,0 are known for the heterostructure. The values of np,0 and nN,0 can be measured using the C–V method of Section 2 on the individual semiconductors (np,0 being deduced from the measured value of pp,0 for the p-type material), and, as shown below, eVbi can be found by applying the C–V method to the whole heterostructure. Then DEv
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can be deduced using the measured DEc value and the known DEg. In considering the heterojunction, we assume at this point that there are no electron or hole traps at the interface and therefore that the only charges there are the polarisation charges (ie, due to the difference of permittivities of the two semiconductors), and that each of the semiconductors is uniformly doped. Then for an applied reverse bias VR, the total reverse potential difference (VR ⫹ Vbi) between the p and N semiconductors can be related to the depletion region widths (and therefore to the stored charge of magnitude QVR on each side of the junction) on the p-side and N-side by considering the electric fields within the depletion regions and by integration of each of them with respect to distance. Then evaluation of CVR as dQVR/dVR gives the result (where NA,p and ND,N are obtained from C–V measurements on the individual semiconductors) that " #0:5 e1p 1N NA;p ND;N A 11 CVR 2 1p NA;p ⫹ 1N ND;N Vbi ⫹ VR 0:5 from which ⫺2 CVR
2 1p NA;p ⫹ 1N ND;N Vbi ⫹ VR e1p 1N NA;p ND;N A2
12
Thus, as for a Schottky diode or homostructure p–n ⫺2 is linearly dependent on VR, and the intercept, diode, CVR on the forward-bias part of the voltage axis, of the best-fit straight line through the data gives the magnitude of the built-in potential Vbi. Substitution of that value into expression (10) permits the conduction-band offset DEc for the heterostructure to be found, and thence also DEv. In an earliesh example of the application of this intercept method, the heterostructure combination of p-InP and NCdS (these semiconductors having bandgaps of 1.35 and 2.50 eV respectively) was investigated [7]; the work showed a DEc value of 0.56 eV, ie close to half the bandgap difference of 1.15 eV. As a more recent example [8], Fig. 2 shows data for the lattice-matched combination pGa0.77In0.23As0.20Sb0.80/N-GaSb; as can be seen, the Vbi value was 0.72 V, and thence a value of 0.330 ^ 0.050 eV for DEc was deduced. From those data and noting the bandgaps of the two semiconductors as 0.52 and 0.725 eV respectively, it was deduced that the bandgaps had the staggered (partial-overlap) arrangement shown in Fig. 1(b) of the present paper. An Intercept-Method investigation on p-SiC/N-GaN [9] has shown DEc and DEv values of 0.11 ^ 0.10 and 0.48 ^ 0.10 eV, respectively, with the mutual arrangement of the energy bands being as in Fig. 1(c) of the present paper. 3.2.2. Using isotype (n–N or p–P) heterojunctions For an n–N heterostructure (ie, two n-type semiconductors of different energy gaps), the same kind of analysis as for the p–N junction shows that the conduction-band offset DEc and the built-in potential Vbi are related by the
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on the n-side of the n–N interface (in great contrast to the carrier depletion situation on the p-side of a p–N heterojunction), and the result is that, in general, it is not easy to interpret the experimental C–V data for an n–N heterostructure so as to obtain an accurate value of Vbi for insertion in expression (13) above. But in the particular situation of nn,0 q nN,0, the total depletion width is essentially all on the N-side, and CVR is given by the expression 2e1N ND;N 0:5 : 14 CVR 0:5A Vbi ⫹ VR
Fig. 3. C–V data [12] obtained on p ⫹-Si1⫺x⫺yGexCy/p-Si, here for an x value of 0.395 for several values of the carbon content y. From the intercepts of the straight data lines shown, DEv values between 0.33 eV (for y equal to zero) and 0.25 eV (for y equal to 2.47%) were found for that x value; a change of slope in the linear DEv(y) data seemed to occur at y equal to 1.2%.
formula DEc eVbi ⫺ kB Tloge Nc;n =Nc;N · nN;0 =nn;0
13
where the symbols N and n are analogous to those of expression (10) above. Therefore, again, DEc can be deduced if eVbi, nN,0 and nn,0 can be measured. However, the electric-field analysis for the n–N heterojunction is mathematically complicated because of the large electron concentration in the conduction-band dip that exists
It is seen that this is the same as expression (1) for a metal/n-semiconductor Schottky diode or p ⫹⫹ –n diode, and so, again, the value of Vbi is the intercept on the forward ⫺2 as a function of bias side of the voltage axis in a plot of CVR the applied reverse bias VR. The reason for the simplification produced by the condition nn,0 q nN,o is that the electron density in the conduction band dip on the n-side is then so large that the n–N junction is behaving as if it were a metal/ N-semiconductor Schottky diode. However, because of the absence of a conduction-band dip on the N-side, the opposite condition, nN,0 q nn,0, would not produce junction behaviour like that of an n-semiconductor/metal Schottky diode. Thus, provided that the n–N heterojunction can be fabricated such that nn,0 q nN,0 , a C–V measurement will allow determination of Vbi for the junction, and DEc can then be deduced by use of expression (13) above. Such a measurement requires, however, that the junction be at low temperature so as to minimize the current flow through the n–N junction, and therefore that nN,0 has to be found from C–V data obtained also at that low temperature so that there is the same trapping of charge carriers at defects and impurities. Early work using this method showed a DEc value of 0.15 eV (giving DEc/Eg equal to 0.20) for an n-Ge/N–Si structure [10]. A detailed analytical form of this method has been used [11] to investigate the band offsets in strained n ⫹-InxGa1⫺xAs/i-In0.52Al0.48As/n-InxGa1⫺xAs structures; for the x-value limits had of 0.44 and 0.64, it was found that DEc had values of 0.495 and 0.657 eV respectively (giving corresponding DEc/Eg values of 0.710 and 0.823). The analogous p–P heterojunctions can also be studied by the Intercept Method, the formalism being as above except that the C–V data provide directly the valence band discontinuity DEv. Data obtained on p ⫹-Si1⫺x⫺yGexCy/p-Si are shown in Fig. 3 [12]; DEv values between 0.16 and 0.33 eV, dependent on their x and y values, were found. 3.3. The charge profile method
Fig. 4. The apparent and true free electron concentration / distance profiles n*(x*) and n(x) respectively in an n–N heterojunction; n*(x*) is the profile obtained from CVR(VR) measurements by use of expressions (6) and (7) for the two semiconductors. The apparent position xj* of the junction usually differs only slightly from the real position xj.
Because the intercept method described in Section 3.2.2 cannot be applied to measure the built-in potential Vbi for an n–N heterojunction except in the special condition nn,0 q nN,0, an alternative method, generally applicable, is required; the ‘‘Charge-Profile’’ method serves that purpose
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and has been powerfully and successfully employed in many recent investigations of band offsets. In Fig. 4, n(x) is the true free electron concentration as a function of real distance x in the n–N heterojunction, and n*(x*) is the apparent free electron concentration as a function of apparent distance x* as determined, from CVR(VR) measurements, by the expressions (6) and (7). Here, CVR is the measured capacitance of the whole Schottky-barrier/ heterojunction structure for an applied reverse bias VR. The n–N heterojunction is located at the real distance xj from the Schottky barrier. As explained in Section 2, n*(x*) is not identical to n(x). However, because of charge conservation, it must be that Z∞ Z∞ n* x* dx* n x dx 15 0
0
and, using that, it was shown [13], and later with extra detail [14], that the built-in potential is given by Z∞ e=1N ND x* ⫺ n* x* x* ⫺ xj dx* 16 Vbi 0
Fig. 5. Apparent free electron concentration / distance profiles n*(x*) as measured (solid line) and as computer-simulated (dashed line) for a carefully fabricated lattice-matched n-In0.53Ga0.47As/N-InP structure [15]. The detailed analysis using the charge-profile method and computer-simulation fitting indicated an DEc value of 0.22 ^ 0.02 eV and a non-polarisation interface charge density of only about 6 × 10 9 cm ⫺2. The shaded peak was interpreted as due to electrons having been transferred, at the lower temperatures, from the electron-accumulation region at the interface to a defect or impurity trap uniformly distributed in the In0.53Ga0.47As layer; DLTS measurements showed that this trap had an electron emission energy to the conduction band of 0.10 ^ 0.02 eV.
where ND(x*) is the donor-doping concentration on the N side at apparent position x*. Thus the experimental investigation requires accurate determination of n*(x*) by use of expressions (6) and (7) applied to the measured C–V data, together with prior knowledge of ND(x*) and of xj. Then using the Vbi value obtained by evaluation of expression (16), the conduction band offset DEc is found from expression (13). Furthermore [13,14], the density of non-polarisation charges at the n–N interface is given by Z∞ sint ND x* ⫺ n* x* dx* 17 0
Fig. 6. Measured and computer-simulated n*(x*) data [16] for the nearlattice-matched heterostructure n-AlxG1⫺xAs/N-In0.5Ga0.5P for x 0.29; for this AlxGa1⫺xAs composition, the mutual band arrangement was that of (c) of Fig. 1, the magnitude of DEc being 0.110 eV.
and application of that formula, using measured C–V data, allows valuable information to be obtained concerning carrier traps at the heterostructure interface. For accurate use of this Charge-Profile Method for determination of the energy-band offsets and of the non-polarisation interface charge density s int, the heterostructure being investigated needs to be fabricated carefully so that the donor-doping profile ND(x) on the N-side is known accurately (and, preferably, is uniform), there are no effective electron traps (especially on the N-side), the real thickness of the n-layer is known accurately, and the donor-doping concentration on the n-side is known at least moderately well and, preferably, that this layer also contains no electron traps. Since it is usually necessary also for the heterostructure sample to be at low temperature for the measurement (so as to reduce the leakage current), the values of DEc, DEv and s int obtained in the experiment will be those for that low temperature. The method has been applied very effectively in various investigations, often by fitting computer-simulated n*(x*) curves to the experimental data. Fig. 5 shows n*(x*) data reported for a carefully fabricated lattice-matched nIn0.53Ga0.47As/N-InP structure [15]; detailed analysis of the
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Fig. 7. DLTS data for VPE-grown n-GaAs, showing a peak due to the wellknown lattice defect called EL2, and for n-InxGa1⫺xAs layers, of three different indium fractions, grown by MBE onto n-GaAs [23]. The DLTS peaks in the respective InxGa1⫺xAs layers were interpreted as due also to EL2 defects whose electron-emission energies, to the conduction band, depend on both the energy gap of the InxGa1⫺xAs and the local indiumatom arrangement around the particular EL2 defect.
data by expressions (16), (13) and (17) above indicated a temperature-independent DEc value of 0.22 ^ 0.02 eV and a non-polarisation interface-charge density s int having the very low value of 6 × 10 9 cm ⫺2. Measured and simulated n*(x*) data for the almost lattice-matched combination nAlxGa1⫺xAs/N-In0.5Ga0.5P have been reported [16] for 0 ⬍ x ⬍ 0.29; data for x 0.29 are given in Fig. 6. The results showed DEc values of ⫹ 0.090 eV (band situation as Fig. 1(d)) for x equal to 0 and of ⫺ 0.110 eV (band situation as Fig. 1(c)) for x equal to 0.29, with DEc changing sign at an x value of 0.12. In a valuable investigation [17] of electron trapping within a semiconductor quantum well, C–V data obtained for a GaAs/In0.24Ga0.76As/GaAs structure were analysed, by use of expressions corresponding to (6) and (7) of the present paper, so as to give the distance profile n*(x*) of the apparent electron density through the structure; computer simulation was then used to determine the value of DEc, the quantum-well depth, that gave a very good fit to the measured n*(x*) function, and a DEc value of 0.165 eV (giving DEc/Eg equal to 0.6) was thus found. Multi-quantum-well structures, for example of AlGaAs/GaAs/AlGaAs [18], have also been investigated by C–V profiling. In further C–V investigations on quantum well structures of those materials fabricated as infra-red detectors, strong
Fig. 8. DLTS spectra for an Al0.25Ga0.75As / In0.5Ga0.5P structure [24] stated to be of rather low quality. Different regions of the heterostructure were probed in the DLTS measurements by changing the applied reverse-bias VR and the applied forward-going pulse-height VPH, and this allowed interpretation of the peaks as due to lattice defects within the AlGaAs layer (E1), within the InGaAs layer (E2) and at the interface between the two materials (E3). As indicated in the inset Arrhenius plot, the defects producing the E3 peak had a central electron emission energy of 0.62 eV; but the width of the E3 peak demonstrated a wide emission-energy range.
effects of the frequency of the capacitance-measurement signal have been observed [19], the data being interpreted in terms of non-equilibrium transient electron injection due to the inertia of the charging and discharging of the GaAs quantum wells through the AlGaAs barriers. For an n-GaAs/ N-ZnSe heterostructure, DEc and s int values of ca. 0.05 eV and 3 × 10 11 cm ⫺2 respectively have been found [20].
4. Investigation of deep carrier-trapping electronic states Of considerable importance to the device applications of semiconductor heterostructures is that they are likely to contain deep electronic states that can trap electrons and holes and therefore produce very significant effects on the heterostructure properties. Such electronic states can be due to incomplete atom–atom bonding, lattice defects or impurities at the interface itself, to dislocations or point defects that may be formed near the interface in one or both of the semiconductor materials as a result of lattice mismatch or lattice relaxation, or to the fundamental conduction states or valence band states of one-, two- or three-dimensional quantum wells. The capacitance-measurement techniques of C–V, C–V– T (capacitance–voltage profiling as a function of sample temperature) and DLTS (Deep Level Transient Spectroscopy), that are well known for investigation of deep electronic states in Schottky or p–n homostructure diodes
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Fig. 9. (a) Trapping of an electron by a semiconductor quantum well and and its thermally induced release in a DLTS experiment [25]; (b) DLTS data showing the peaks from two separate quantum wells, each of width 12 nm, in an Al0.2Ga0.8As/InxGa1⫺xAs multi-layer structure [25]; the electron emission energies were 0.19 eV for QW1 (having x 0.13) and 0.305 eV for QW2 (having x 0.18).
[2,21,22], can be very effectively employed also for studies of all the three kinds of heterostructure deep level states specified in the previous paragraph. The main principle is that the capture of electrons or holes by the deep states removes the carriers from the conduction band or valence band respectively and so changes the electrical capacitance CVR of the semiconductor structure;
raising the sample temperature may then (depending on the magnitude of the electronic transition energy) cause thermal excitation of the electrons or holes back to their respective energy bands, and so return the diode capacitance to its value before the carrier capture by the deep states. Thus CVR(T) data can give information on carrier-trapping defects and impurities. In the DLTS technique, the
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information on the electronic transition energy involved is obtained by instrumentally examining the sample-temperature dependence of the capacitance transient C(t) during the trap-emptying phase in a repetitive filling and emptying sequence implemented by pulsed reverse biasing. Use of a capacitance-transient analysing circuit set to respond to a particular small range of transient time-constants, while the sample temperature is progressively changed (usually from low temperature to high temperature), allows production of a deep-state spectrum that shows peaks at the successive temperatures at which the time constant for carrier emission from each such state corresponds to the set time of the transient-analysing circuit. Analysis of such spectra for different analyser set-times enables the electronic transition energy for each deep-state spectral peak to be deduced. As an example of the application of DLTS to heterostructures, Fig. 7 shows data demonstrating that the growth of (lattice-mismatched) n-InxGa1⫺xAs by Molecular-Beam Epitaxy on GaAs can, unexpectedly, cause the formation of the point defect called EL2 within the deposited InxGa1⫺xAs layer [23]; the EL2 defect seems most likely to be the arsenic anti-site (in effect, a group of five arsenic atoms), and that production of it was attributed to the climb, during MBE growth in arsenic-rich conditions, of dislocations arising from lattice relaxation of the InxGa1⫺xAs. The DLTS spectrum of Fig. 8 for an Al0.25Ga0.75 As/In0.5Ga0.5P structure, also lattice-mismatched, shows peaks respectively attributed to lattice defects within the AlGaAs layer (E1), within the InGaAs layer (E2) and at the AlGaAs/InGaAs interface (E3) [24]. The way in which DLTS can be applied to study semiconductor quantum well states is illustrated in Fig. 9(a). Data, from such an investigation, showing the two DLTS peaks due respectively to electron emission from two separate InxGa1⫺xAs quantum wells having the same widths but different compositions, x, in an Al0.2Ga0.8As/InxGa1⫺xAs multi-layer structure [25] are shown in Fig. 9(b); the results of that study were used to determine the dependence of DEc / DEg on the indium content x. DLTS studies have been made also on semiconductor quantum dots; for InP quantum dots, approximately 13 nm in height and 40 nm in diameter, in Ga0.5In0.5P, an electron emission energy of 0.22 eV for the one-electron ground state, and a decrease of that energy for increased electron filling of the dots, have been reported [26]. 5. Summary and conclusions It is clear that measurements by the Capacitance–Voltage and Capacitance-Mode Deep Level Transient Spectroscopy techniques can provide valuable information concerning semiconductor heterostructures. Such measurements are fairly easy to make if the samples are appropriate and well fabricated, but accurate interpretation of the data needs very considerable care.
For the determination of band offsets, the C–V Intercept Method can work well if the density of non-polarisation interface charges is low, and if the doping and carrier traps in the respective layers are spatially uniform. However, the C–V Charge-Profiling Method is more generally applicable and can give accurate values of the band offsets and of the densities of non-polarisation interface charges. DLTS can be very effective for investigating the energy levels and concentrations of carrier traps (defects and impurities) both at the interface and in the layers, and can be applied to semiconductor quantum wells and quantum dots to study their intrinsic electron and hole states.
References [1] S.M. Sze, Semiconductor Devices: Physics and Technology, Wiley, 1985. [2] D.W. Palmer, in: R.A. Stradling, P.C. Klipstein (Eds.), Growth and Characterisation of Semiconductors, Adam Hilger, UK, 1990, pp. 187–224. [3] L.C. Kimerling, J. Appl. Phys. 45 (1974) 1839–1845. [4] P. Blood, J.W. Orton, Rep. Prog. Phys. 41 (1978) 157–182. [5] S.R. Forrest, in: F. Capasso, G. Margaritondo (Eds.), Heterojunction Band Discontinuities, North Holland, 1987, pp. 311 Chap. 8. [6] D.A. Neamen, Semiconductor Physics and Devices: Basic Principles, Irwin, USA, 1992. [7] J.L. Shay, S. Wagner, J.C. Philips, Appl. Phys. Lett. 28 (1976) 31. [8] M. Mebarki, D. Boukredimi, S. Sadik, J.L. Lazzari, J. Appl. Phys. 73 (1993) 2360–2363. [9] J.T. Torvik, M. Leksono, J.I. Pankove, B. Van Zeghbroeck, H.M. Ng, T.D. Moustakas, Appl. Phys. Lett. 72 (1998) 1371–1373. [10] C. Van Opdorp, H.K.J. Kanerva, Solid State Electronics 10 (1967) 401. [11] J.-H. Huang, T.Y. Chang, J. Appl. Phys. 76 (1994) 2893–2903. [12] C.L. Chang, A. St Amour, J.C. Sturm, Appl. Phys. Lett. 70 (1997) 1557–1559. [13] H. Kroemer, Wu-Yi Chien, J.S. Harris Jr., D.D. Edwall, Appl. Phys. Lett. 36 (1980) 295–297. [14] H. Kroemer, Appl. Phys. Lett. 46 (1985) 504–505. [15] C.D. Lee, S.R. Forrest, J. Appl. Phys. 69 (1991) 342–351. [16] I.-J. Kim, Y.-H. Cho, K.-S. Kim, B.-D. Choe, Appl. Phys. Lett. 68 (1996) 3488–3490. [17] S. Subramanian, B.M. Arora, A.K. Srivastava, G. Fernandes, S. Banerjee, J. Appl. Phys. 74 (1993) 7618–7620. [18] M. Ershov, V. Ryzhil, K. Saito, J. Phys: D Appl. Phys. 28 (1995) 2118–2122. [19] M. Ershov, H.C. Liu, L. Li, M. Buchanan, Z.R. Wasilewski, V. Ryzhil, Appl. Phys. Lett. 70 (1997) 1828–1830. [20] T. Matsumoto, N. Kokubo, K. Kawakami, T. Kato, J. Cryst. Growth 117 (1992) 578–582. [21] D.V. Lang, L.C. Kimerling, Inst. Phys. Conf. Series 23 (1975) 581. [22] D.C. Look, Electrical Characterisation of GaAs Materials and Devices, Wiley, 1989. [23] A.C. Irvine, D.W. Palmer, Phys. Rev. Lett. 68 (1992) 2168–2171. [24] Y.-H. Cho, B.-D. Choe, Y. Kim, H. Lim, J. Appl. Phys. 81 (1997) 7362–7366. [25] N. Debbar, D. Biswas, P. Bhattacharya, J.E. Oh, Inst. Phys. Conf. Series 96 (1989) 299–302. [26] S. Anand, N. Carlsson, M.-E. Pistol, L. Samuelson, W. Seifert, Appl. Phys. Lett. 67 (1995) 3016–3018.
Microelectronics Journal Microelectronics Journal 30 (1999) 665–672
Characterisation of semiconductor heterostructures by capacitance methods 夽 D.W. Palmer 1 Physics and Astronomy Subject Group, University of Sussex, Brighton BN1 9QJ, UK
Abstract Investigations of the steady-state and transient electrical capacitance properties of semiconductor heterostructures allow determination of the conduction-band and valence-band energy offsets that occur at the interfaces between materials of different band-gaps and of the presence of carrier-trapping states both in the materials and at the interfaces. For determination of band offsets, the main technique is C–V measurement, i.e. the measurement of the steady-state small-signal (differential) capacitance as a function of applied voltage, and this paper outlines the C–V Intercept and C–V Charge-Profile Methods. Concerning electron and hole trapping in heterostructures, including that in quantum well structures, the presence, concentrations and energy levels of such carrier trapping states can be effectively determined by the C–V–T and DLTS techniques. This paper outlines the principles of these techniques for studying heterostructures, and gives examples of data and results. 䉷 1999 Elsevier Science Ltd. All rights reserved. Keywords: Semiconductor; Heterostructures; Band offsets; C–V Intercept; C–V Charge-Profiling method; Carrier traps
1. Introduction As electrical capacitance is defined in terms of stored charge, it is clear that measurement of the capacitance of a semiconductor structure can give valuable information about its electronic properties. Of very common consideration is the capacitance of a p–n homostructure diode or Schottky diode in the condition of zero or applied reverse bias, and then the measured capacitance is easily related to the total width of the depletion region within the diode. The capacitances of semiconductor diodes are conventionally measured using a capacitance meter by which a small AC voltage, often at 1.0 MHz, superimposed on a DC reversebias voltage, VR, is applied to the diode being investigated, with the meter then evaluating the capacitance from the magnitude of the AC current 90⬚ out of phase with the applied AC voltage; such a measurement gives the small signal (differential) depletion capacitance CVR, defined as dQVR/dVR, where QVR is the stored charge. Then CVR as a function of VR can provide considerable information about the semiconductor diode or structure; this is what is called ‘‘C–V Profiling’’. 夽
Journe´es Maghreb-Europe: Les Materiaux et Leurs Applications aux Dispositifs Capteurs Physiques, Chimiques et Biologiques (MADICA’98). E-mail address: [email protected] (D.W. Palmer) 1 Present Address: Palmer Semiconductor Associates, ‘‘Olde Stone’’, Lydford, Devon EX20 4BH, UK
This paper outlines how C–V Profiling of a semiconductor heterostructure can be used to measure the energy discontinuities (‘‘offsets’’) in the conduction bands and valence bands at the interface between semiconductor heterostructure layers and how C–V Profiling and Capacitance-Mode Deep Level Transient Spectroscopy (the latter employing the capacitance–time transient that occurs upon sudden change of VR) are used to investigate deep electronic states in the heterostructure. 2. The capacitance–voltage measurement method For a Schottky/n-type semiconductor diode or p ⫹⫹/n homostructure diode, almost all of the near-junction region depleted of charge carriers, i.e. the depletion region, lies in the n-type semiconductor. Considering the stored charge QVR in a junction, of cross-sectional area A, across which there is an externally applied reverse voltage VR, the smallsignal capacitance CVR, equal to dQVR/dVR, can be shown [1,2] to be given by the expression 2e1n ND 0:5 1 CVR 0:5A Vbi ⫹ VR or CVR A1n = xd n
2
where e n is the permittivity of the n-type semiconductor, Vbi
0026-2692/99/$ - see front matter 䉷 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(99)00040-3
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profile ND(x) is related to CVR(VR) by the expression 3 e1n A2 ⫺1 dCVR =dVR ⫺1 ND xd n ⫺CVR
4
where, again, xd n x 1n A=CVR :
5
Thus ND(x) can, in principle, be found by measurement of CVR(VR). However, the profile eND(x) found in that way is an effective space-charge profile eN ⫹(x), which is the space charge profile e[ND(x)]chem due to the chemical donors, modified by space charges due to carrier trapping at lattice defects and impurities [2–4]. Furthermore, what the CVR(VR) data give is really the mobile electron concentration n(x), which, because of electron diffusion, is different from N ⫹(x). Also the edge of the depletion-region is not sharp, and so (xd)n is not an exact measure of the real distance x. Therefore the expressions above are often written, in terms of apparent distances x* and apparent carrier concentration profiles n*(x*), as 3 e1n A2 ⫺1 dCVR =dVR ⫺1 n* x* ⫺CVR
6
where x* 1n A=CVR
7
and where n*(x*) is not identical to n(x). Thus, even for semiconductor homojunctions, accurate interpretation of the CVR(VR) data requires considerable care. 3. Measurement of band offsets Fig. 1. Possible mutual arrangements of the valence and conduction bands of the two materials of a semiconductor heterostructure; the arrangements (a)–(d) are usually called broken-gap, staggered, staggered and straddled respectively.
is the built-in (‘‘diffusion’’) potential of the junction (dependent on the Fermi energies of the two materials), ND is the donor concentration in the n-type semiconductor, here assumed spatially uniform, and (xd)n is the depletion region width. For example, a 1 mm 2 diode of GaAs having ND equal to 1 × 10 15 cm ⫺3 has a capacitance close to 30 pF for VR equal to 10 V. From the expression (1) we have ⫺2 CVR
2 Vbi ⫹ VR : e 1n N D A 2
3
⫺2 as a function of VR for Therefore, in a graphical plot of CVR ⫹⫹ a Schottky/n-semiconductor or p –n diode, the linear data extrapolated to forward voltage give an intercept on the voltage axis equal to the potential Vbi. The slope of the data allows the value of ND to be determined. For the case where the donor concentration ND is not necessarily uniform with respect to distance x in the semiconductor, it can be shown that the concentration–distance
3.1. Introduction Fig. 1 shows possible mutual arrangements of the conduction bands and valence bands for a double layer heterostructure, for which it is assumed that the energy gaps Eg1 and Eg2, of the two semiconductors comprising the heterostructure, are different in magnitude. The analysis in the present paper denotes the energy discontinuities, DEv and DEc of the valence band and conduction band respectively, as positive for the ‘‘straddled’’ arrangement shown as (d). Then, Eg2 ⫺ Eg1 DEg DEv ⫹ DEc :
8
For a heterostructure diode, the energy band discontinuities (the ‘‘band offsets’’) at the junction between the dissimilar semiconductors can be determined by two C–V methods, closely related to that given above for a homostructure diode. Detailed description of the two methods has been previously published [5], and only the main features of the procedures, here called the ‘‘Intercept Method’’ and the ‘‘Charge-Profiling Method’’, are given in this paper. The labelling convention for the two semiconductors of the heterostructure is that a lower-case letter p or n is used to indicate the semiconductor type of the material having the smaller energy-bandgap, and, correspondingly, that P or N is used for the semiconductor of larger band-gap.
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Fig. 2. C–V data [8] for the lattice-matched combination pGa0.77In0.23As0.20Sb0.80/N-GaSb. A value of 0.335 ^ 0.050 eV for DEc was found by using the intercept value of 0.720 ^ 0.030 V, the free hole concentration of 1.2 × 10 16 cm ⫺3 in the GaInAsSb (obtained from the slope of the straight line through the points) and the known magnitude (1.0 ^ 0.2 × 10 18 cm ⫺3) of the free electron concentration in the GaSb. The inset picture shows the I–V data for the diode.
3.2. The intercept method for band-offset determination 3.2.1. Using anisotype (p–N or P–n) heterojunctions By considering the band diagrams for a p-semiconductor and an N-semiconductor before contact and after contact at zero applied bias, it can be shown [5,6] that the energy change eVbi corresponding to the built-in (diffusion) potential Vbi when the two materials are in contact is given by eVbi DEc ⫹ Ec;p ⫺ EF;p ⫺ Ec;N ⫺ EF;N
9
where (Ec,p ⫺ EF,p) is the energy difference between the conduction band edge and the Fermi energy for the p-semiconductor and (Ec,N ⫺ EF,N) is the corresponding energy difference for the N-semiconductor. Thus the conduction-band offset energy is given by the expression h i DEc eVbi ⫺ kB T loge Nc;p =Nc;N · nN;0 =np;0
10
where, for the respective p- and N-type semiconductors, Nc,p and Nc,N are the effective densities of state of the conduction bands and np,0 and nN,0 are the free electron concentrations in the zero-field condition. Therefore DEc can be found if eVbi, np,0 and nN,0 are known for the heterostructure. The values of np,0 and nN,0 can be measured using the C–V method of Section 2 on the individual semiconductors (np,0 being deduced from the measured value of pp,0 for the p-type material), and, as shown below, eVbi can be found by applying the C–V method to the whole heterostructure. Then DEv
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can be deduced using the measured DEc value and the known DEg. In considering the heterojunction, we assume at this point that there are no electron or hole traps at the interface and therefore that the only charges there are the polarisation charges (ie, due to the difference of permittivities of the two semiconductors), and that each of the semiconductors is uniformly doped. Then for an applied reverse bias VR, the total reverse potential difference (VR ⫹ Vbi) between the p and N semiconductors can be related to the depletion region widths (and therefore to the stored charge of magnitude QVR on each side of the junction) on the p-side and N-side by considering the electric fields within the depletion regions and by integration of each of them with respect to distance. Then evaluation of CVR as dQVR/dVR gives the result (where NA,p and ND,N are obtained from C–V measurements on the individual semiconductors) that " #0:5 e1p 1N NA;p ND;N A 11 CVR 2 1p NA;p ⫹ 1N ND;N Vbi ⫹ VR 0:5 from which ⫺2 CVR
2 1p NA;p ⫹ 1N ND;N Vbi ⫹ VR e1p 1N NA;p ND;N A2
12
Thus, as for a Schottky diode or homostructure p–n ⫺2 is linearly dependent on VR, and the intercept, diode, CVR on the forward-bias part of the voltage axis, of the best-fit straight line through the data gives the magnitude of the built-in potential Vbi. Substitution of that value into expression (10) permits the conduction-band offset DEc for the heterostructure to be found, and thence also DEv. In an earliesh example of the application of this intercept method, the heterostructure combination of p-InP and NCdS (these semiconductors having bandgaps of 1.35 and 2.50 eV respectively) was investigated [7]; the work showed a DEc value of 0.56 eV, ie close to half the bandgap difference of 1.15 eV. As a more recent example [8], Fig. 2 shows data for the lattice-matched combination pGa0.77In0.23As0.20Sb0.80/N-GaSb; as can be seen, the Vbi value was 0.72 V, and thence a value of 0.330 ^ 0.050 eV for DEc was deduced. From those data and noting the bandgaps of the two semiconductors as 0.52 and 0.725 eV respectively, it was deduced that the bandgaps had the staggered (partial-overlap) arrangement shown in Fig. 1(b) of the present paper. An Intercept-Method investigation on p-SiC/N-GaN [9] has shown DEc and DEv values of 0.11 ^ 0.10 and 0.48 ^ 0.10 eV, respectively, with the mutual arrangement of the energy bands being as in Fig. 1(c) of the present paper. 3.2.2. Using isotype (n–N or p–P) heterojunctions For an n–N heterostructure (ie, two n-type semiconductors of different energy gaps), the same kind of analysis as for the p–N junction shows that the conduction-band offset DEc and the built-in potential Vbi are related by the
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on the n-side of the n–N interface (in great contrast to the carrier depletion situation on the p-side of a p–N heterojunction), and the result is that, in general, it is not easy to interpret the experimental C–V data for an n–N heterostructure so as to obtain an accurate value of Vbi for insertion in expression (13) above. But in the particular situation of nn,0 q nN,0, the total depletion width is essentially all on the N-side, and CVR is given by the expression 2e1N ND;N 0:5 : 14 CVR 0:5A Vbi ⫹ VR
Fig. 3. C–V data [12] obtained on p ⫹-Si1⫺x⫺yGexCy/p-Si, here for an x value of 0.395 for several values of the carbon content y. From the intercepts of the straight data lines shown, DEv values between 0.33 eV (for y equal to zero) and 0.25 eV (for y equal to 2.47%) were found for that x value; a change of slope in the linear DEv(y) data seemed to occur at y equal to 1.2%.
formula DEc eVbi ⫺ kB Tloge Nc;n =Nc;N · nN;0 =nn;0
13
where the symbols N and n are analogous to those of expression (10) above. Therefore, again, DEc can be deduced if eVbi, nN,0 and nn,0 can be measured. However, the electric-field analysis for the n–N heterojunction is mathematically complicated because of the large electron concentration in the conduction-band dip that exists
It is seen that this is the same as expression (1) for a metal/n-semiconductor Schottky diode or p ⫹⫹ –n diode, and so, again, the value of Vbi is the intercept on the forward ⫺2 as a function of bias side of the voltage axis in a plot of CVR the applied reverse bias VR. The reason for the simplification produced by the condition nn,0 q nN,o is that the electron density in the conduction band dip on the n-side is then so large that the n–N junction is behaving as if it were a metal/ N-semiconductor Schottky diode. However, because of the absence of a conduction-band dip on the N-side, the opposite condition, nN,0 q nn,0, would not produce junction behaviour like that of an n-semiconductor/metal Schottky diode. Thus, provided that the n–N heterojunction can be fabricated such that nn,0 q nN,0 , a C–V measurement will allow determination of Vbi for the junction, and DEc can then be deduced by use of expression (13) above. Such a measurement requires, however, that the junction be at low temperature so as to minimize the current flow through the n–N junction, and therefore that nN,0 has to be found from C–V data obtained also at that low temperature so that there is the same trapping of charge carriers at defects and impurities. Early work using this method showed a DEc value of 0.15 eV (giving DEc/Eg equal to 0.20) for an n-Ge/N–Si structure [10]. A detailed analytical form of this method has been used [11] to investigate the band offsets in strained n ⫹-InxGa1⫺xAs/i-In0.52Al0.48As/n-InxGa1⫺xAs structures; for the x-value limits had of 0.44 and 0.64, it was found that DEc had values of 0.495 and 0.657 eV respectively (giving corresponding DEc/Eg values of 0.710 and 0.823). The analogous p–P heterojunctions can also be studied by the Intercept Method, the formalism being as above except that the C–V data provide directly the valence band discontinuity DEv. Data obtained on p ⫹-Si1⫺x⫺yGexCy/p-Si are shown in Fig. 3 [12]; DEv values between 0.16 and 0.33 eV, dependent on their x and y values, were found. 3.3. The charge profile method
Fig. 4. The apparent and true free electron concentration / distance profiles n*(x*) and n(x) respectively in an n–N heterojunction; n*(x*) is the profile obtained from CVR(VR) measurements by use of expressions (6) and (7) for the two semiconductors. The apparent position xj* of the junction usually differs only slightly from the real position xj.
Because the intercept method described in Section 3.2.2 cannot be applied to measure the built-in potential Vbi for an n–N heterojunction except in the special condition nn,0 q nN,0, an alternative method, generally applicable, is required; the ‘‘Charge-Profile’’ method serves that purpose
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and has been powerfully and successfully employed in many recent investigations of band offsets. In Fig. 4, n(x) is the true free electron concentration as a function of real distance x in the n–N heterojunction, and n*(x*) is the apparent free electron concentration as a function of apparent distance x* as determined, from CVR(VR) measurements, by the expressions (6) and (7). Here, CVR is the measured capacitance of the whole Schottky-barrier/ heterojunction structure for an applied reverse bias VR. The n–N heterojunction is located at the real distance xj from the Schottky barrier. As explained in Section 2, n*(x*) is not identical to n(x). However, because of charge conservation, it must be that Z∞ Z∞ n* x* dx* n x dx 15 0
0
and, using that, it was shown [13], and later with extra detail [14], that the built-in potential is given by Z∞ e=1N ND x* ⫺ n* x* x* ⫺ xj dx* 16 Vbi 0
Fig. 5. Apparent free electron concentration / distance profiles n*(x*) as measured (solid line) and as computer-simulated (dashed line) for a carefully fabricated lattice-matched n-In0.53Ga0.47As/N-InP structure [15]. The detailed analysis using the charge-profile method and computer-simulation fitting indicated an DEc value of 0.22 ^ 0.02 eV and a non-polarisation interface charge density of only about 6 × 10 9 cm ⫺2. The shaded peak was interpreted as due to electrons having been transferred, at the lower temperatures, from the electron-accumulation region at the interface to a defect or impurity trap uniformly distributed in the In0.53Ga0.47As layer; DLTS measurements showed that this trap had an electron emission energy to the conduction band of 0.10 ^ 0.02 eV.
where ND(x*) is the donor-doping concentration on the N side at apparent position x*. Thus the experimental investigation requires accurate determination of n*(x*) by use of expressions (6) and (7) applied to the measured C–V data, together with prior knowledge of ND(x*) and of xj. Then using the Vbi value obtained by evaluation of expression (16), the conduction band offset DEc is found from expression (13). Furthermore [13,14], the density of non-polarisation charges at the n–N interface is given by Z∞ sint ND x* ⫺ n* x* dx* 17 0
Fig. 6. Measured and computer-simulated n*(x*) data [16] for the nearlattice-matched heterostructure n-AlxG1⫺xAs/N-In0.5Ga0.5P for x 0.29; for this AlxGa1⫺xAs composition, the mutual band arrangement was that of (c) of Fig. 1, the magnitude of DEc being 0.110 eV.
and application of that formula, using measured C–V data, allows valuable information to be obtained concerning carrier traps at the heterostructure interface. For accurate use of this Charge-Profile Method for determination of the energy-band offsets and of the non-polarisation interface charge density s int, the heterostructure being investigated needs to be fabricated carefully so that the donor-doping profile ND(x) on the N-side is known accurately (and, preferably, is uniform), there are no effective electron traps (especially on the N-side), the real thickness of the n-layer is known accurately, and the donor-doping concentration on the n-side is known at least moderately well and, preferably, that this layer also contains no electron traps. Since it is usually necessary also for the heterostructure sample to be at low temperature for the measurement (so as to reduce the leakage current), the values of DEc, DEv and s int obtained in the experiment will be those for that low temperature. The method has been applied very effectively in various investigations, often by fitting computer-simulated n*(x*) curves to the experimental data. Fig. 5 shows n*(x*) data reported for a carefully fabricated lattice-matched nIn0.53Ga0.47As/N-InP structure [15]; detailed analysis of the
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Fig. 7. DLTS data for VPE-grown n-GaAs, showing a peak due to the wellknown lattice defect called EL2, and for n-InxGa1⫺xAs layers, of three different indium fractions, grown by MBE onto n-GaAs [23]. The DLTS peaks in the respective InxGa1⫺xAs layers were interpreted as due also to EL2 defects whose electron-emission energies, to the conduction band, depend on both the energy gap of the InxGa1⫺xAs and the local indiumatom arrangement around the particular EL2 defect.
data by expressions (16), (13) and (17) above indicated a temperature-independent DEc value of 0.22 ^ 0.02 eV and a non-polarisation interface-charge density s int having the very low value of 6 × 10 9 cm ⫺2. Measured and simulated n*(x*) data for the almost lattice-matched combination nAlxGa1⫺xAs/N-In0.5Ga0.5P have been reported [16] for 0 ⬍ x ⬍ 0.29; data for x 0.29 are given in Fig. 6. The results showed DEc values of ⫹ 0.090 eV (band situation as Fig. 1(d)) for x equal to 0 and of ⫺ 0.110 eV (band situation as Fig. 1(c)) for x equal to 0.29, with DEc changing sign at an x value of 0.12. In a valuable investigation [17] of electron trapping within a semiconductor quantum well, C–V data obtained for a GaAs/In0.24Ga0.76As/GaAs structure were analysed, by use of expressions corresponding to (6) and (7) of the present paper, so as to give the distance profile n*(x*) of the apparent electron density through the structure; computer simulation was then used to determine the value of DEc, the quantum-well depth, that gave a very good fit to the measured n*(x*) function, and a DEc value of 0.165 eV (giving DEc/Eg equal to 0.6) was thus found. Multi-quantum-well structures, for example of AlGaAs/GaAs/AlGaAs [18], have also been investigated by C–V profiling. In further C–V investigations on quantum well structures of those materials fabricated as infra-red detectors, strong
Fig. 8. DLTS spectra for an Al0.25Ga0.75As / In0.5Ga0.5P structure [24] stated to be of rather low quality. Different regions of the heterostructure were probed in the DLTS measurements by changing the applied reverse-bias VR and the applied forward-going pulse-height VPH, and this allowed interpretation of the peaks as due to lattice defects within the AlGaAs layer (E1), within the InGaAs layer (E2) and at the interface between the two materials (E3). As indicated in the inset Arrhenius plot, the defects producing the E3 peak had a central electron emission energy of 0.62 eV; but the width of the E3 peak demonstrated a wide emission-energy range.
effects of the frequency of the capacitance-measurement signal have been observed [19], the data being interpreted in terms of non-equilibrium transient electron injection due to the inertia of the charging and discharging of the GaAs quantum wells through the AlGaAs barriers. For an n-GaAs/ N-ZnSe heterostructure, DEc and s int values of ca. 0.05 eV and 3 × 10 11 cm ⫺2 respectively have been found [20].
4. Investigation of deep carrier-trapping electronic states Of considerable importance to the device applications of semiconductor heterostructures is that they are likely to contain deep electronic states that can trap electrons and holes and therefore produce very significant effects on the heterostructure properties. Such electronic states can be due to incomplete atom–atom bonding, lattice defects or impurities at the interface itself, to dislocations or point defects that may be formed near the interface in one or both of the semiconductor materials as a result of lattice mismatch or lattice relaxation, or to the fundamental conduction states or valence band states of one-, two- or three-dimensional quantum wells. The capacitance-measurement techniques of C–V, C–V– T (capacitance–voltage profiling as a function of sample temperature) and DLTS (Deep Level Transient Spectroscopy), that are well known for investigation of deep electronic states in Schottky or p–n homostructure diodes
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Fig. 9. (a) Trapping of an electron by a semiconductor quantum well and and its thermally induced release in a DLTS experiment [25]; (b) DLTS data showing the peaks from two separate quantum wells, each of width 12 nm, in an Al0.2Ga0.8As/InxGa1⫺xAs multi-layer structure [25]; the electron emission energies were 0.19 eV for QW1 (having x 0.13) and 0.305 eV for QW2 (having x 0.18).
[2,21,22], can be very effectively employed also for studies of all the three kinds of heterostructure deep level states specified in the previous paragraph. The main principle is that the capture of electrons or holes by the deep states removes the carriers from the conduction band or valence band respectively and so changes the electrical capacitance CVR of the semiconductor structure;
raising the sample temperature may then (depending on the magnitude of the electronic transition energy) cause thermal excitation of the electrons or holes back to their respective energy bands, and so return the diode capacitance to its value before the carrier capture by the deep states. Thus CVR(T) data can give information on carrier-trapping defects and impurities. In the DLTS technique, the
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information on the electronic transition energy involved is obtained by instrumentally examining the sample-temperature dependence of the capacitance transient C(t) during the trap-emptying phase in a repetitive filling and emptying sequence implemented by pulsed reverse biasing. Use of a capacitance-transient analysing circuit set to respond to a particular small range of transient time-constants, while the sample temperature is progressively changed (usually from low temperature to high temperature), allows production of a deep-state spectrum that shows peaks at the successive temperatures at which the time constant for carrier emission from each such state corresponds to the set time of the transient-analysing circuit. Analysis of such spectra for different analyser set-times enables the electronic transition energy for each deep-state spectral peak to be deduced. As an example of the application of DLTS to heterostructures, Fig. 7 shows data demonstrating that the growth of (lattice-mismatched) n-InxGa1⫺xAs by Molecular-Beam Epitaxy on GaAs can, unexpectedly, cause the formation of the point defect called EL2 within the deposited InxGa1⫺xAs layer [23]; the EL2 defect seems most likely to be the arsenic anti-site (in effect, a group of five arsenic atoms), and that production of it was attributed to the climb, during MBE growth in arsenic-rich conditions, of dislocations arising from lattice relaxation of the InxGa1⫺xAs. The DLTS spectrum of Fig. 8 for an Al0.25Ga0.75 As/In0.5Ga0.5P structure, also lattice-mismatched, shows peaks respectively attributed to lattice defects within the AlGaAs layer (E1), within the InGaAs layer (E2) and at the AlGaAs/InGaAs interface (E3) [24]. The way in which DLTS can be applied to study semiconductor quantum well states is illustrated in Fig. 9(a). Data, from such an investigation, showing the two DLTS peaks due respectively to electron emission from two separate InxGa1⫺xAs quantum wells having the same widths but different compositions, x, in an Al0.2Ga0.8As/InxGa1⫺xAs multi-layer structure [25] are shown in Fig. 9(b); the results of that study were used to determine the dependence of DEc / DEg on the indium content x. DLTS studies have been made also on semiconductor quantum dots; for InP quantum dots, approximately 13 nm in height and 40 nm in diameter, in Ga0.5In0.5P, an electron emission energy of 0.22 eV for the one-electron ground state, and a decrease of that energy for increased electron filling of the dots, have been reported [26]. 5. Summary and conclusions It is clear that measurements by the Capacitance–Voltage and Capacitance-Mode Deep Level Transient Spectroscopy techniques can provide valuable information concerning semiconductor heterostructures. Such measurements are fairly easy to make if the samples are appropriate and well fabricated, but accurate interpretation of the data needs very considerable care.
For the determination of band offsets, the C–V Intercept Method can work well if the density of non-polarisation interface charges is low, and if the doping and carrier traps in the respective layers are spatially uniform. However, the C–V Charge-Profiling Method is more generally applicable and can give accurate values of the band offsets and of the densities of non-polarisation interface charges. DLTS can be very effective for investigating the energy levels and concentrations of carrier traps (defects and impurities) both at the interface and in the layers, and can be applied to semiconductor quantum wells and quantum dots to study their intrinsic electron and hole states.
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