- Email: [email protected]
Charge pumping in thin film transistors
MICROELECTRONIC ENGINEERING
ELSEVIER
Microelectronic Engineering 28 (1995) 379-382
Charge Pumping in Thin Film Transistors N. S. Saks*, S. Batrab and M. Manningb “Code 6813, Naval Research Lab, Washington, D.C. 20375 U.S.A. bMicron Semiconductor, Inc., Boise, ID. 83706 U.S.A. Abstract Charge pumping (CP) has been used to study defects in p-channel poly-crystalline silicon thin film transistors (TFTs). At high frequencies (>- 1 kHz), we observe anomalous CP behavior in TFTs due to (a) the high resistivity of, and/or slow electron trapping in, the poly-Si channel and (b) the existence of a TFT drain offset region. At low frequencies, the CP technique still appears to provide a use&l measure of the TFT grain boundary defect density. Introduction The electrical characteristics of TFTs are controlled by electrically-active defects at grain boundaries in the poly-Si channel. Due to its very high sensitivity [ 11, charge pumping may be a useful and unique technique for characterizing these defects. For example, charge pumping is performed directly on small TFTs, rather than requiring large (and perhaps inappropriate) test structures such as required for capacitance-voltage analysis. There are only a few previous CP studies in TFTs [2,3]. Koyonagi et al. [2] reported CP experiments on large { 15x20 pm (1 x w)} n-channel TFTs fabricated on 100 nm thick poly-Si. They observed a well-behaved CP signal which was (properly) proportional to the CP frequency. A lower defect density was determined in TFTs fabricated at 950 vs. 6OO”C,as might be expected due to a larger grain siie at high temperature. Balasinski et al. [3] reported CP results on smaller (2 x 0.6 pm) p-channel TFTs. Their CP data show a significant reduction in defect density after annealing in HZat 400°C [3]. One disadvantage of these CP TFT results (and this work also), is that the CP current arises from both fast interface traps (as in single-crystal FETs) and grain boundary defects within the thickness of the inversion layer in the poly-Si channel. A CP model for separating these two contributions does not DRAIN presently exist. As in refs [2-31, we assume here that grain boundary defects dominate. TFT Structure DRAIN Devices studied are bottom-gate, p-channel SoURCE TFTs, typically -1.0 x 1.9 pm (length x width) (Fig. 1). A test structure with 20 TFTs in parallel was used in order to obtain a reasonably large CP signal. The test structures also have a lateral N’ contact (not shown in Fig. 1) to the 50 nm thick poly-Si channel, which is required to collect the CP current. For SRAM applications, TFTs typically Figure 1. Cross section of bottom-gate p-channel TFT test structure for CP experiments. 0167-9317/95/$09.50 0 1995 - Elsevier Science B.V. All rights reserved. SSDI 0167.9317(95)00080-l
N.S. Saks et al. / Microelectronic Engineering 28 (1995) 379-382
380
employ a lightly-doped drain offset (LDO) as shown in Fig. 1. In the LDO region, the n-type poly-Si is compensated by a boron implant, which creates a higher resistivity region to reduce the OFF-state leakage current. CP results are presented here for TFTs with and without LDO. Experimental
Results
A typical experimental charge-pump current I, is shown in Fig. 2 vs. the base (low) level of a fixed-amplitude CP gate pulse for a TFT without LDO. The 1.O kHz pulse has a 4V amplitude and fixed 0.2 ms rise and fall times. The CP signal in Fig. 2 appears qualitatively correct since I,, approaches zero at large negative and positive Vbase.However, these TFT results are also significantly different from a normal single-crystal FET. I,, is normally independent of V,,,, in a wide central region, with steeply rising transitions from I,,=O. For the TFT, I,, is not flat in the central region, and the transition regions are relatively broad. Furthermore, analysis of the transition regions does not yield appropriate values for the TFT threshold and flatband voltages as it should (see ref [ 11) (data not shown). From CP theory, I,, should be proportional to the frequency of the ac pulse, using constant rise and fall times [l]. To test this dependence, the I,, frequency dependence of the TFTs was measured at V,,,=- 0.W (i.e., at peak I& as shown in Fig. 3. At frequencies >-1 kHz, I,, is significantly smaller than the expected linear dependence indicated by the solid line in Fig. 3, Thus it appears that CP measurements on this TFT are incorrect at high frequencies, but may be correct at low frequencies. From a practical point of view, this result is undesirable because high CP frequencies are preferred in order to increase I,, in these very small TFTs. Incorrect CP frequency dependence is probably caused by the high poly-Si channel resistance. For proper CP operation, high electron densities must accumulate at the poly-Si/SiO, interface when the gate pulse is positive. These electrons recombine with holes trapped at the defects while the CP pulse was negative, causing a CP recombination current to flow. However, if the series resistance of the poly-Si channel is too high, electrons cannot readily flow from the N’ contact through the poly, cutting off the CP current. Thus Icpis low at high frequencies, but correct at low frequencies, as in Fig. 2. Three additional observations support this explanation: (1) The total charge recombined per CP cycle, Q,,,,, (=I$), was measured as a function of electron and hole till times tfiuas shown in Fig. 4. For a normal FET, Q,,e is independent of to, at times longer than -10 ns (a typical carrier capture time during CP). In Fig. 4, Qcycleis
10'
+++
TB”‘B”‘n.+-.
0 -6
-4
-2
0
10’
2 Vbase
[email protected]
4
6
(V)
Figure 2. Charge pumpingcurrent Icp vs. Vbase for TFT without drain offset region.
8
1@2
103 Frequency
Figure
IO’
10s
10‘
(Hz)
3. Icp tiequency dependence for TFT in Fig. 2 (symbols). The solid line shows the expected linear dependence of Icp on tiequency.
N.S. Saks et al. / Microelectronic Engineering 28 (1995) 379-382
105
381
trise=tfall=O_3po
_/
,’
,’
Vat-4V Vbasc--2.5V
t
&
10-7
10.'
10-S
10-4
10-S
FILL
TIME
(6)
10-2
10-J
101
102
10’
104
CP FREQUENCY
105
Figure 4. Hole or electron fill times are varied with
Figure 5. I, as a function of CP frequency in TFTs
all other CP parameters
with 25 and 50 mn poly-Si channel thicknesses.
constant.
10‘
(Hz)
independent of the hole fill time (for constant electron fill time=1 ms) as expected. However, Q,,, is not independent of electron fill time. Qcyclcis abnormally small at short electron fill times, and appears to be correct only at long (>-3 ms) e-fill times , which is in rough agreement with the frequency at which I, begins to deviate from linear dependence in Fig. 2. This result demonstrates that electrons are not readily supplied to the TFT, perhaps because of a high resistance poly-Si channel. The poly-Si sheet resistance p, measured on separate test devices, is =0.1-l MQ/square--orders of magnitude higher than a normal single-crystal FET substrate. It is unclear whether this p value is high enough to cause this effect just due to an RC circuit delay. (2) In Fig. 5, I,_+is shown vs. frequency for TFTs from two wafers with different poly-Si channel thicknesses, 25 and 50 nm. I,, is clearly abnormally small for 25 nm compared to 50 nm poly. This result clearly demonstrates that the abnormally low I,, arises from behavior in the poly-Si channel. Since the measured p for the 25 nm poly is only about a factor of two larger than for the 50 nm poly (as expected), while I, is reduced by a much larger factor, it appears that the reduction in I, has a very strong dependence on p. This suggests that the poly might even be Mollydepleted, especially in the 25 nm poly, leading to the observed strongly non-linear behavior. (3) In Fig. 6, I,, is shown vs. time after a TFT is turned on. A large, slow I,, transient occurs atler turn-on. I,, initially overshoots its equilibrium value, typically by a factor of two or more, so and then slowly relaxes back towards equilibrium. Similar slow transient effects were observed previously in n-channel amorphous silicon TFTs [4], 20 which were ascribed to slow electron trapping in the channel. Whatever the mechanism, these data show 3 that slow time-dependent effects can arise from the -_ -‘lo ----.-.----._._.____.-.----.-----. silicon channel, which may affect CP operation. CP in TFTs with LDO
The effect of a TFT LDO region on CP characteristics is shown in Fig. 7. The LDO region has a significant effect on the CP data: (1) The absolute magnitude of the I, is much higher in the LDO vs. non-LDO TFTs (compare Figs. 2 and 7).
0 10-4
10-s
10-d
10”
10”
10.
TIME (s)
Figure 6. Drain-to-source current I, in a TFT without LDO as a function of time after the gate is pulsed from OFF (V,=OV) to ON (V,= -5V).
382
N.S. Saks et al. / Microelectronic Engineering 28 (1995) 379-382
Since device geometries are the same, higher I, in the LDO TFT may simply reflect a higher
120 100
~‘~“‘~‘~*~~~*’
-
++ + +
f=lOOO Hz Vnc-4V
+ grain boundary defect density which could + + 80 arise from an unknown variation between + + + process lots. Alternatively, the increase in I,, ?$60+ + ++ ++++++ could result from charge recombination in the + 3 40 + LDO region. (2) A large distortion appears + + on the right-hand side of the I,, peak in Fig. 7. + 20 - + + + This distortion presumably arises from the + + 0”’ ‘I ‘I .‘. ‘. c. a ‘LDO region, since it is not observed in the -8 -6 -4 -2 0 2 4 6 8 non-LDO TFT. A similar dual-peak CP signal Vbase (V) was reported on TFTs with LDO by Balasinski et a1.[3] There are several possible causes: Figure 7 I,, in TFT with LDO region. Distortion on (a) A true CP signal may arise from defects in right is due to LDO region. the LDO region as proposed in ref. [3]. The CP signal from this region is shifted to more positive V,, because of a change in threshold voltage due to the additional LDO boron doping. (b) Existence of the LDO region may create potential energy barriers which block free movement carriers in this region. Initial experiments here on the frequency dependence of the distortion in Fig. 7 suggest that it is probably due to these barriers. Summary/Conclusions In this paper, we have reported initial results on charge pumping in p-channel TFTs. We find
that CP in these TFTs differs substantially from normal single-crystal FETs, unlike previous reports on n-channel TFTs [2]. In particular, an improper frequency dependence is observed at high CP frequencies (>- 1 kHz). We have reported considerable experimental evidence which ties this effect to the high resistivity of the poly-Si channel. We have also observed that I, in TFTs with LDO is distorted with a dual peak. Preliminary analysis suggests that the LDO-related peak may be an artifact caused by potential energy barriers, and is not a true CP signal, Finally, the trap density in a non-LDO TFT was measured by changing the CP rise and fall times [l] (data not shown). The calculated trap density is - 10” traps/cm3-eV, consistent with previous results [5]. Despite experimental difficulties, it appears that CP will prove to be a useful technique for studying defects in TFTs, if the CP test frequency is kept low, and long electron and hole fill times are employed. Much work remains to completely understand CP in TFTs. A detailed model needs to be developed for the I, frequency dependence. The source of the CP signal from the LDO regions must be characterized more carefully. Standard CP analysis [l] must be modified to reflect charge trapping and emission at grain boundary defects in the poly-Si channel rather than traps at the Si-SiO, interface. Finally, a technique is needed to differentiate between charge pumping from interface traps and grain boundary defects, References: [l] G. Groeseneken, H.E.Maes, N. Beltran, and R.F. DeKeersmaecker, IEEE Trans. Elec. Dev. ED-31,42 (1984). [2] M. Koyonagi, Y. Baba, K. Hata, I-W. Wu, A.G. Lewis, M. Fuse, and R. Bruce, IEEE Electron Dev. Lett. 13, 152, Mar 1992. Also, Proc. 1990 IEDM, p. 863. [3] A. Balasinskl, R. Sundaresan, R. Hodges, F. Bryant, K.W. Hung, J. Worley, and F.T. Liou, Meeting ofthe Electrochemical Socieg, Miami Beach, Fl., Oct. 1 l-16, 1994. [4] M. Hack et al., PhilMug. E, 69, p. 327 (1994). [5] T. J. King, M.Hack, and I. Wu, J. Appl. Phys., 908, Jan. 1994.
ELSEVIER
Microelectronic Engineering 28 (1995) 379-382
Charge Pumping in Thin Film Transistors N. S. Saks*, S. Batrab and M. Manningb “Code 6813, Naval Research Lab, Washington, D.C. 20375 U.S.A. bMicron Semiconductor, Inc., Boise, ID. 83706 U.S.A. Abstract Charge pumping (CP) has been used to study defects in p-channel poly-crystalline silicon thin film transistors (TFTs). At high frequencies (>- 1 kHz), we observe anomalous CP behavior in TFTs due to (a) the high resistivity of, and/or slow electron trapping in, the poly-Si channel and (b) the existence of a TFT drain offset region. At low frequencies, the CP technique still appears to provide a use&l measure of the TFT grain boundary defect density. Introduction The electrical characteristics of TFTs are controlled by electrically-active defects at grain boundaries in the poly-Si channel. Due to its very high sensitivity [ 11, charge pumping may be a useful and unique technique for characterizing these defects. For example, charge pumping is performed directly on small TFTs, rather than requiring large (and perhaps inappropriate) test structures such as required for capacitance-voltage analysis. There are only a few previous CP studies in TFTs [2,3]. Koyonagi et al. [2] reported CP experiments on large { 15x20 pm (1 x w)} n-channel TFTs fabricated on 100 nm thick poly-Si. They observed a well-behaved CP signal which was (properly) proportional to the CP frequency. A lower defect density was determined in TFTs fabricated at 950 vs. 6OO”C,as might be expected due to a larger grain siie at high temperature. Balasinski et al. [3] reported CP results on smaller (2 x 0.6 pm) p-channel TFTs. Their CP data show a significant reduction in defect density after annealing in HZat 400°C [3]. One disadvantage of these CP TFT results (and this work also), is that the CP current arises from both fast interface traps (as in single-crystal FETs) and grain boundary defects within the thickness of the inversion layer in the poly-Si channel. A CP model for separating these two contributions does not DRAIN presently exist. As in refs [2-31, we assume here that grain boundary defects dominate. TFT Structure DRAIN Devices studied are bottom-gate, p-channel SoURCE TFTs, typically -1.0 x 1.9 pm (length x width) (Fig. 1). A test structure with 20 TFTs in parallel was used in order to obtain a reasonably large CP signal. The test structures also have a lateral N’ contact (not shown in Fig. 1) to the 50 nm thick poly-Si channel, which is required to collect the CP current. For SRAM applications, TFTs typically Figure 1. Cross section of bottom-gate p-channel TFT test structure for CP experiments. 0167-9317/95/$09.50 0 1995 - Elsevier Science B.V. All rights reserved. SSDI 0167.9317(95)00080-l
N.S. Saks et al. / Microelectronic Engineering 28 (1995) 379-382
380
employ a lightly-doped drain offset (LDO) as shown in Fig. 1. In the LDO region, the n-type poly-Si is compensated by a boron implant, which creates a higher resistivity region to reduce the OFF-state leakage current. CP results are presented here for TFTs with and without LDO. Experimental
Results
A typical experimental charge-pump current I, is shown in Fig. 2 vs. the base (low) level of a fixed-amplitude CP gate pulse for a TFT without LDO. The 1.O kHz pulse has a 4V amplitude and fixed 0.2 ms rise and fall times. The CP signal in Fig. 2 appears qualitatively correct since I,, approaches zero at large negative and positive Vbase.However, these TFT results are also significantly different from a normal single-crystal FET. I,, is normally independent of V,,,, in a wide central region, with steeply rising transitions from I,,=O. For the TFT, I,, is not flat in the central region, and the transition regions are relatively broad. Furthermore, analysis of the transition regions does not yield appropriate values for the TFT threshold and flatband voltages as it should (see ref [ 11) (data not shown). From CP theory, I,, should be proportional to the frequency of the ac pulse, using constant rise and fall times [l]. To test this dependence, the I,, frequency dependence of the TFTs was measured at V,,,=- 0.W (i.e., at peak I& as shown in Fig. 3. At frequencies >-1 kHz, I,, is significantly smaller than the expected linear dependence indicated by the solid line in Fig. 3, Thus it appears that CP measurements on this TFT are incorrect at high frequencies, but may be correct at low frequencies. From a practical point of view, this result is undesirable because high CP frequencies are preferred in order to increase I,, in these very small TFTs. Incorrect CP frequency dependence is probably caused by the high poly-Si channel resistance. For proper CP operation, high electron densities must accumulate at the poly-Si/SiO, interface when the gate pulse is positive. These electrons recombine with holes trapped at the defects while the CP pulse was negative, causing a CP recombination current to flow. However, if the series resistance of the poly-Si channel is too high, electrons cannot readily flow from the N’ contact through the poly, cutting off the CP current. Thus Icpis low at high frequencies, but correct at low frequencies, as in Fig. 2. Three additional observations support this explanation: (1) The total charge recombined per CP cycle, Q,,,,, (=I$), was measured as a function of electron and hole till times tfiuas shown in Fig. 4. For a normal FET, Q,,e is independent of to, at times longer than -10 ns (a typical carrier capture time during CP). In Fig. 4, Qcycleis
10'
+++
TB”‘B”‘n.+-.
0 -6
-4
-2
0
10’
2 Vbase
[email protected]
4
6
(V)
Figure 2. Charge pumpingcurrent Icp vs. Vbase for TFT without drain offset region.
8
1@2
103 Frequency
Figure
IO’
10s
10‘
(Hz)
3. Icp tiequency dependence for TFT in Fig. 2 (symbols). The solid line shows the expected linear dependence of Icp on tiequency.
N.S. Saks et al. / Microelectronic Engineering 28 (1995) 379-382
105
381
trise=tfall=O_3po
_/
,’
,’
Vat-4V Vbasc--2.5V
t
&
10-7
10.'
10-S
10-4
10-S
FILL
TIME
(6)
10-2
10-J
101
102
10’
104
CP FREQUENCY
105
Figure 4. Hole or electron fill times are varied with
Figure 5. I, as a function of CP frequency in TFTs
all other CP parameters
with 25 and 50 mn poly-Si channel thicknesses.
constant.
10‘
(Hz)
independent of the hole fill time (for constant electron fill time=1 ms) as expected. However, Q,,, is not independent of electron fill time. Qcyclcis abnormally small at short electron fill times, and appears to be correct only at long (>-3 ms) e-fill times , which is in rough agreement with the frequency at which I, begins to deviate from linear dependence in Fig. 2. This result demonstrates that electrons are not readily supplied to the TFT, perhaps because of a high resistance poly-Si channel. The poly-Si sheet resistance p, measured on separate test devices, is =0.1-l MQ/square--orders of magnitude higher than a normal single-crystal FET substrate. It is unclear whether this p value is high enough to cause this effect just due to an RC circuit delay. (2) In Fig. 5, I,_+is shown vs. frequency for TFTs from two wafers with different poly-Si channel thicknesses, 25 and 50 nm. I,, is clearly abnormally small for 25 nm compared to 50 nm poly. This result clearly demonstrates that the abnormally low I,, arises from behavior in the poly-Si channel. Since the measured p for the 25 nm poly is only about a factor of two larger than for the 50 nm poly (as expected), while I, is reduced by a much larger factor, it appears that the reduction in I, has a very strong dependence on p. This suggests that the poly might even be Mollydepleted, especially in the 25 nm poly, leading to the observed strongly non-linear behavior. (3) In Fig. 6, I,, is shown vs. time after a TFT is turned on. A large, slow I,, transient occurs atler turn-on. I,, initially overshoots its equilibrium value, typically by a factor of two or more, so and then slowly relaxes back towards equilibrium. Similar slow transient effects were observed previously in n-channel amorphous silicon TFTs [4], 20 which were ascribed to slow electron trapping in the channel. Whatever the mechanism, these data show 3 that slow time-dependent effects can arise from the -_ -‘lo ----.-.----._._.____.-.----.-----. silicon channel, which may affect CP operation. CP in TFTs with LDO
The effect of a TFT LDO region on CP characteristics is shown in Fig. 7. The LDO region has a significant effect on the CP data: (1) The absolute magnitude of the I, is much higher in the LDO vs. non-LDO TFTs (compare Figs. 2 and 7).
0 10-4
10-s
10-d
10”
10”
10.
TIME (s)
Figure 6. Drain-to-source current I, in a TFT without LDO as a function of time after the gate is pulsed from OFF (V,=OV) to ON (V,= -5V).
382
N.S. Saks et al. / Microelectronic Engineering 28 (1995) 379-382
Since device geometries are the same, higher I, in the LDO TFT may simply reflect a higher
120 100
~‘~“‘~‘~*~~~*’
-
++ + +
f=lOOO Hz Vnc-4V
+ grain boundary defect density which could + + 80 arise from an unknown variation between + + + process lots. Alternatively, the increase in I,, ?$60+ + ++ ++++++ could result from charge recombination in the + 3 40 + LDO region. (2) A large distortion appears + + on the right-hand side of the I,, peak in Fig. 7. + 20 - + + + This distortion presumably arises from the + + 0”’ ‘I ‘I .‘. ‘. c. a ‘LDO region, since it is not observed in the -8 -6 -4 -2 0 2 4 6 8 non-LDO TFT. A similar dual-peak CP signal Vbase (V) was reported on TFTs with LDO by Balasinski et a1.[3] There are several possible causes: Figure 7 I,, in TFT with LDO region. Distortion on (a) A true CP signal may arise from defects in right is due to LDO region. the LDO region as proposed in ref. [3]. The CP signal from this region is shifted to more positive V,, because of a change in threshold voltage due to the additional LDO boron doping. (b) Existence of the LDO region may create potential energy barriers which block free movement carriers in this region. Initial experiments here on the frequency dependence of the distortion in Fig. 7 suggest that it is probably due to these barriers. Summary/Conclusions In this paper, we have reported initial results on charge pumping in p-channel TFTs. We find
that CP in these TFTs differs substantially from normal single-crystal FETs, unlike previous reports on n-channel TFTs [2]. In particular, an improper frequency dependence is observed at high CP frequencies (>- 1 kHz). We have reported considerable experimental evidence which ties this effect to the high resistivity of the poly-Si channel. We have also observed that I, in TFTs with LDO is distorted with a dual peak. Preliminary analysis suggests that the LDO-related peak may be an artifact caused by potential energy barriers, and is not a true CP signal, Finally, the trap density in a non-LDO TFT was measured by changing the CP rise and fall times [l] (data not shown). The calculated trap density is - 10” traps/cm3-eV, consistent with previous results [5]. Despite experimental difficulties, it appears that CP will prove to be a useful technique for studying defects in TFTs, if the CP test frequency is kept low, and long electron and hole fill times are employed. Much work remains to completely understand CP in TFTs. A detailed model needs to be developed for the I, frequency dependence. The source of the CP signal from the LDO regions must be characterized more carefully. Standard CP analysis [l] must be modified to reflect charge trapping and emission at grain boundary defects in the poly-Si channel rather than traps at the Si-SiO, interface. Finally, a technique is needed to differentiate between charge pumping from interface traps and grain boundary defects, References: [l] G. Groeseneken, H.E.Maes, N. Beltran, and R.F. DeKeersmaecker, IEEE Trans. Elec. Dev. ED-31,42 (1984). [2] M. Koyonagi, Y. Baba, K. Hata, I-W. Wu, A.G. Lewis, M. Fuse, and R. Bruce, IEEE Electron Dev. Lett. 13, 152, Mar 1992. Also, Proc. 1990 IEDM, p. 863. [3] A. Balasinskl, R. Sundaresan, R. Hodges, F. Bryant, K.W. Hung, J. Worley, and F.T. Liou, Meeting ofthe Electrochemical Socieg, Miami Beach, Fl., Oct. 1 l-16, 1994. [4] M. Hack et al., PhilMug. E, 69, p. 327 (1994). [5] T. J. King, M.Hack, and I. Wu, J. Appl. Phys., 908, Jan. 1994.