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Charging effects in Ge nanocrystals embedded in SiO2 matrix for non volatile memory applications
Materials Science and Engineering C 26 (2006) 360 – 363 www.elsevier.com/locate/msec
Charging effects in Ge nanocrystals embedded in SiO2 matrix for non volatile memory applications M. Kanoun a,*, T. Baron b, E. Gautier c, A. Souifi a a
Laboratoire de Physique de La Matie`re, UMR-CNRS 5511, INSA De Lyon, Bat. 502, 7 avenue Jean Capelle 69621 Villeurbanne cedex, France b LTM/CNRS, LETI/DTS CEA/GRE, 17 Avenue des martyrs 38 054 Grenoble cedex 9, France c Laboratoire IMN, 2 rue de la Houssinie`re 44322 Nantes cedex 3, France Available online 5 January 2006
Abstract Charging effects in germanium nanocrystals (nc-Ge) embedded in SiO2 matrix fabricated by low pressure chemical vapor deposition have been studied by the mean of capacitance – voltage (C – V) combined with current – voltage (I – V) analysis. The C – V measurements showed hysteresis phenomena indicating holes charging in the Ge islands. The I – V measurements at ambient temperature exhibited an N-shaped form attributed to screening effects of positive charges stored in the nc-Ge. The same measurement at low temperatures shows that the hole trapping is a thermally activated process and the I – V analysis with different ramp rates were used in order to investigate the charging phenomena. D 2005 Elsevier B.V. All rights reserved. Keywords: Nanocrystals; C – V; I – V charging; Memory
1. Introduction The use of nanocrystals has been proposed by Tiwari et al. [1] in order to develop highly integrated few electron memories. The use of a floating gate composed of isolated dots reduces the problems of charge loss encountered in conventional Flash memories, allowing thinner injection oxides and, hence, smaller operating voltages, better endurance, and faster write/erase speeds [1,2]. The memory function of these devices has been attributed to the charge exchange between nanocrystals and the inversion layer. After the first proposal of a memory transistor using silicon nanocrystals (nc-Si) as floating gates, other works have confirmed that non volatile memories (NVM) using PMOS or NMOS transistors can be achieved. In order to improve the data retention in NVMs, it seems interesting to use Ge nanocrystals (nc-Ge) rather than nc-Si because of its smaller band gap. Indeed King et al. [4] have recently demonstrated the superior properties of Ge based nanocrystals memories over those based on Si, in terms of the writing/erasing time. Indeed non volatile memories with implanted Ge nanocrystals have been demonstrated [3– 5]. Isolated nc-Ge in SiO2 layers can be * Corresponding author. Tel.: +33 674679299; fax: +33 472436082. E-mail addresses: [email protected] (M. Kanoun), [email protected] (A. Souifi). 0928-4931/$ - see front matter D 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.msec.2005.10.039
obtained by various other techniques such as oxidation and reduction of Ge/Si islands [6], UV-assisted oxidation of Si1 x Gex alloys [7], and rapid thermal oxidation (RTO) of ncGe [8– 11] or (Ge + SiO2) [12]. The fabrication of a non volatile memory cell requires a perfect control of 4 main parameters: (i) the tunnel oxide thickness, (ii) the nanocrystal density, (iii) the nanocrystal diameter, and (iv) the control oxide thickness. In the structures obtained by Ge implantation, it is possible to have a rather good control of the tunnel oxide thickness by using a low energy process. However, other parameters such as densities, diameters, and crystalline quality are not fully controlled. For all the nc-Ge memory structures presented in Ref. [6– 12], the formation of nanocrystals is obtained after oxidation steps. In most of these experiments, it appears quite difficult to control very thin tunnel oxide layers. Nevertheless, in spite of the technological limitations for industrial applications, most of the nc-Ge structures have demonstrated that the Ge/SiO2 system has good electrical data retention properties. In this paper, we propose an electrical study of memory effects in nc-Ge/SiO2 fabricated by Low Pressure Chemical Vapor deposition (LPCVD). The capacitance versus voltage (C – V) and current versus voltage (I –V) measurements have been done in order to study the memory effect in nc-Ge/SiO2. Temperature dependent I – V measurements and current – voltage with different ramp rates have been used in order to
M. Kanoun et al. / Materials Science and Engineering C 26 (2006) 360 – 363
361 from 2 V to -5 V Sample D from -5 V to 2 V Sample D from 2 V to -5 V Sample A from -5 V to 2 V Sample A
1.0
C/Cox
0.8 0.6 0.4 0.2 -5
-4
-3
-2
-1
0
1
2
Gate Voltage Fig. 2. C – V curves recorded at 10 kHz for samples A and D. The gate voltage is swept from inversion to the accumulation then from the accumulation to the inversion.
investigate the data retention mechanism and then to study the displacement of the charges through the tunnel oxide. 2. Experiment details The substrates used in this study are p-type 200 mm Si (100) wafers covered by a thermal SiO2 layer (tunnel oxide). Si nuclei and nc-Ge were grown in a single reduced pressure chemical vapour deposition (CVD) reactor designed by Applied Materials, in which the SiH4 and GeH4 gaseous precursors are diluted in H2. The nc-Ge are grown using a two-step process. First, the SiO2 surface is functionalized by the deposition of Si nuclei using SiH4 as a gaseous precursor. Second, once the Si nuclei are deposited, we stop the SiH4 gas flow, and GeH4 is introduced to selectively grown on the Si nuclei [13,14]. Fig. 1 shows a typical HR-TEM image of Nc-Ges embedded in SiO2 using this process. The NC’s density and diameter size are given by a statistic counting of Scan Electron Microscopy (SEM) images. They are about 6 1011 cm 2 8.5 nm, respectively. The tunnel oxide thickness has been varied from 1.2 to 2.5 nm, while the control oxide remains constant at 10 nm. The samples investigated in this study are described in the Table 1. For the electrical measurements we have deposited a 250 nm thick aluminium gate in order to obtain MOS capacitors. The devices have a square shape with surfaces ranging from 100 100 to 400 400 Am2. C – V and I – V curves have been recorded using a HP 4284 and a HP 4156, respectively.
(+ 2 to 5 V) and forward ( 5 to +2 V) voltage scan is performed, the structures are, respectively, biased from inversion to accumulation conditions, and then from accumulation to inversion. Using such conditions, we observe a significant shift of the C – V curves on the left during the forward scan. This result is consistent with a positive charge trapping in the oxide. As one can see on Fig. 2, the voltage shift is larger for sample D which has a thicker tunnel oxide. This result is explained by the longer retention time of carriers due to exponential decrease of tunnelling mechanism as the thickness increases. The negative voltage shift can be attributed either to a hole trapping mechanism from the substrate, or to an electron emission from the nc-Ge. In our experimental conditions, the phenomenon is more probably attributed to the hole trapping process. Note that for sample A, with a 1.2 nm tunnel oxide, we also observe a variation of the slope of the C – V curve after charge injection. Our hypothesis is that the nc-Ge are sufficiently close to the Si/ SiO2 interface, and their electric charge can modify the density of free carrier in the substrate. In fact, for very thin tunnel oxides, it is possible to consider the Ge dots as an interface traps. This assumption could explain why the slope is very sharp for thick tunnel oxides before and after hole’s charging.
Sample A dtun = 1.2 nm
1E-8
J(A.cm-2)
Fig. 1. HRTEM image of a crystalline isolated Ge nanocrystal. The mean size is equal to 8.5 nm.
3. Results and discussion 1E-9
Fig. 2 shows a comparison of a typical high frequency C –V measurement normalized for devices A and D. When a reverse -6 Table 1 Description of the samples used
-4
-2
0
VG(V)
Samples
A
B
C
D
Tunnel oxide (nm)
1.2
1.5
2
2.5
Fig. 3. Current density versus voltage characteristics of samples A. The I – V curve of sample A exhibits a pick in the accumulation region (negative voltage).
M. Kanoun et al. / Materials Science and Engineering C 26 (2006) 360 – 363
As we can also observe in Fig. 3, the I – V curve exhibits two peaks at low voltage (about 0.25 and 1.35 V) in the accumulation region. This result is reproducible only for the two samples with the thinnest tunnel oxides (samples A and B). These peaks have been observed by other authors at low [17] temperature and at the ambient one [15,16] and are attributed either to the resonant tunneling or to charging effects in the nanocrystals. In our case the first assumption is excluded because of the dissymmetry of the studied structure [13,14]. Indeed, the thickness of the control oxide is 10 nm and that of the tunnel one is 1.2 nm. For this reason we can attribute this current pick to displacement of holes from the accumulation layer to the nc-Ge through the tunnel oxide. In order to confirm assumption two ways have been investigated: The first method consist on low temperature I –V measurements. As shown in Fig. 4 recorded at 77 K, a first measurement on a virgin capacitance exhibits two current peaks respectively at 0.25 and 1.35 V. When a second voltage sweep is done, these picks are shifted by about 2 V on the left in agreement with a strong hole trapping effect. The process is shown to be fully reversible, since it has been possible to discharge the trapped holes by applying a positive bias at + 7 V. Then, when a new sweep is performed, the initial I – V curve is nearly recovered. Such experiments confirm our hypothesis of hole trapping. Such I – V ‘‘hysteresis’’ after several scans is not observed at room temperature because the hole de-trapping mechanism is thermally activated. The second way consists on I – V measurements with different voltage ramps. Before discussing the experimental results let’s introduce the definition of delay time in a current measurement. When a charging effect occurs in a diode structure, out equilibrium state is established, then a change in the potential and the electric field is produced through the structure. In this case we can observe a depending-time-component in the current I – V behaviour. Therefore, we have to distinguish between the static and dynamic I – V characteristics. To obtain the static
Curent density (A. Cm-2)
10-9
10-10
10-11 virgine at 77K first measurement (sample A) Append 1 at 77 K Append 2 at 77 K An append after inversion scan at 77 K
10-12 -6
-4
-2
0
VG(V) Fig. 4. Low temperature I – V measurements (77 K) showing a hysteresis. The current’s pick recovers its initial position after a sweep in the inversion region.
2.7x10-8
J(A.cm-2)
362
dtun 1.5 nm
Os
1.8x10-8 5s 9.0x10-9
12 s
20 s 30 s
0.0 -3
-2
-1
0
VG Fig. 5. Current – voltage measurements for different delays.
characteristics, it is necessary to wait for a certain time until the current becomes a steady state. We define the waiting time until the current measurement after applying each voltage as Fdelay time_, hereafter. I – V characteristics measured under a short delay time show the dynamic behaviour. In Fig. 5, we present the I –V characteristics at low voltages (from 0 to 3 V) using a staircase voltage with different step delays varying from 1 up to 30 s. For short step time delay (faster measurements), the maximum of the current peak is larger. When the step delay increases, the current dip is smaller and tends to disappear for very large time. This result shows that the current is due to a charge displacement with a very large time constant. Since this phenomenon is observed in the accumulation regime of a p-type Si substrate, we attribute it to a hole charging in the dots, from the valence band of the substrate. Indeed, the control oxide is relatively thicker (10 nm) to the tunnel one (1.2 nm), so no current flows through the structure at low voltages until the Fowler – Nordheim injection at high voltage ( 6 V). 4. Conclusion The fabrication of NVM structures using Ge nanocrystals embedded in SiO2 has been demonstrated. The LPCVD process developed in this work is shown to be well suited for a real control of the tunnel oxide thickness. Moreover, the deposition conditions allow a separate control of nc-Ge density and size, as demonstrated by high resolution transmission electron microscopy. The I –V analyses have demonstrated charging effects, and a hysteresis is observed only at low temperatures. These types of measurements show that the phenomenon is reversible, since it is possible to arise the stocked charges. Using current versus voltage measurements at different ramp rates on NVM structures, we have demonstrated that the transient current is due to a hole charging phenomenon. The current peak is higher for the short time delays and tend to disappear for the larger one. The advantages of Ge dots rather than Si are mainly due to a larger barrier height for data retention (4.9 eV) and a heavy effective mass for holes (m h* = 7 m 0). Combined with a good control of nc-Ge properties, the use of Ge dots with large diameters (15 nm) seems to be a promising way for memory applications.
M. Kanoun et al. / Materials Science and Engineering C 26 (2006) 360 – 363
Acknowledgements This work has been done in the frame of ‘‘DOTSET’’ project by Re´gion Rhoˆne-Alpes. References [1] S. Tiwari, F. Rana, H. Hanafi, A. Hrtstein, E.F. Crabbe´, K. Chan, Appl. Phys. Lett. 68 (1996) 1377. [2] S. Tiwari, F. Rana, K. Chan, L. Shi, H. Hanafi, Appl. Phys. Lett. 69 (1996) 1232. [3] B. De Salvo, G. Ghibaudo, G. Pananakakis, B. Guillaumot, T. Baron, Superlattices Microstruct. 28 (2000) 339. [4] Y.C. King, T.J. King, C. Hu, IEEE Trans. Electron Devices 48 (2001) 696. [5] H.I. Hanafi, S. Tiwari, I. Khan, IEEE Trans. Electron Devices 43 (9) (1996) 1553. [6] T. Sass, V. Zela, A. Gustafsson, I. Pietzonka, W. Seifert, Appl. Phys. Lett. 81 (2002) 3455. [7] V. Craciun, I.W. Boyd, A.H. Reader, W.J. Kersten, F.J.G. Hakkens, P.H. Oosting, D.E.W. Vandenhoudt, J. Appl. Phys. 75 (1994) 1972. [8] A. Kanjilal, J. Lundsgaard Hansen, P. Gaiduk, A. Nylandsted Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, D. Tsoukalas, Appl. Phys. Lett. 82 (2003) 1212.
363
[9] H. Fukuda, T. Kobayashi, T. Endoh, S. Nomura, A. Sakai, Y. Ueda, Appl. Surf. Sci. 130 – 132 (1998) 776. [10] Y. Kim, H.J. Cheong, K.H. Park, T.H. Chung, H.J. Bark, J. Yi, S.H. Bang, J.H. Cho, Semicond. Sci. Technol. 17 (2002) 1039. [11] W.K. Choi, W.K. Chim, C.L. Heng, L.W. Teo, Vincent Ho, V. Ng, D.A. Antoniadis, E.A. Fitzgerald, Appl. Phys. Lett. 80 (2002) 2014. [12] T. Baron, B. Pelissier, L. Perniola, F. Mazen, J.M. Hartmann, G. Rolland, Appl. Phys. Lett. 83 (2003) 1444. [13] B. De Salvo, G. Ghibaudo, P. Luthereau, T. Baron, B. Guillaumot, G. Reimbold, Solid-State Electron. 45 (2001) 1513. [14] D.N. Kouvatsos, V. Ioannou-Sougleridis, A.G. Nassiopoulou, Appl. Phys. Lett. 82 (2003) 397. [15] T. Maeda, E. Suzuki, I. Sakata, M. Yamanaka, K. Ishii, Nanotechnology 10 (1999) 127. [16] T. Maeda, E. Suzuki, Isao Sakata, M. Yamanaka, K. Ishii, Nanotechnology 10 (1999) 127. [17] P. Dimitrakis, E. Kapetanakis, P. Normand, D. Skarlatos, D. Tsoukalas, K. Beltsios, A. Claverie, G. Benessayag, C. Bonafos, D. Chassaing, V. Soncini, Mater. Sci. Eng., B, Solid-State Mater. Adv. Technol. 101 (2003) 14.
Charging effects in Ge nanocrystals embedded in SiO2 matrix for non volatile memory applications M. Kanoun a,*, T. Baron b, E. Gautier c, A. Souifi a a
Laboratoire de Physique de La Matie`re, UMR-CNRS 5511, INSA De Lyon, Bat. 502, 7 avenue Jean Capelle 69621 Villeurbanne cedex, France b LTM/CNRS, LETI/DTS CEA/GRE, 17 Avenue des martyrs 38 054 Grenoble cedex 9, France c Laboratoire IMN, 2 rue de la Houssinie`re 44322 Nantes cedex 3, France Available online 5 January 2006
Abstract Charging effects in germanium nanocrystals (nc-Ge) embedded in SiO2 matrix fabricated by low pressure chemical vapor deposition have been studied by the mean of capacitance – voltage (C – V) combined with current – voltage (I – V) analysis. The C – V measurements showed hysteresis phenomena indicating holes charging in the Ge islands. The I – V measurements at ambient temperature exhibited an N-shaped form attributed to screening effects of positive charges stored in the nc-Ge. The same measurement at low temperatures shows that the hole trapping is a thermally activated process and the I – V analysis with different ramp rates were used in order to investigate the charging phenomena. D 2005 Elsevier B.V. All rights reserved. Keywords: Nanocrystals; C – V; I – V charging; Memory
1. Introduction The use of nanocrystals has been proposed by Tiwari et al. [1] in order to develop highly integrated few electron memories. The use of a floating gate composed of isolated dots reduces the problems of charge loss encountered in conventional Flash memories, allowing thinner injection oxides and, hence, smaller operating voltages, better endurance, and faster write/erase speeds [1,2]. The memory function of these devices has been attributed to the charge exchange between nanocrystals and the inversion layer. After the first proposal of a memory transistor using silicon nanocrystals (nc-Si) as floating gates, other works have confirmed that non volatile memories (NVM) using PMOS or NMOS transistors can be achieved. In order to improve the data retention in NVMs, it seems interesting to use Ge nanocrystals (nc-Ge) rather than nc-Si because of its smaller band gap. Indeed King et al. [4] have recently demonstrated the superior properties of Ge based nanocrystals memories over those based on Si, in terms of the writing/erasing time. Indeed non volatile memories with implanted Ge nanocrystals have been demonstrated [3– 5]. Isolated nc-Ge in SiO2 layers can be * Corresponding author. Tel.: +33 674679299; fax: +33 472436082. E-mail addresses: [email protected] (M. Kanoun), [email protected] (A. Souifi). 0928-4931/$ - see front matter D 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.msec.2005.10.039
obtained by various other techniques such as oxidation and reduction of Ge/Si islands [6], UV-assisted oxidation of Si1 x Gex alloys [7], and rapid thermal oxidation (RTO) of ncGe [8– 11] or (Ge + SiO2) [12]. The fabrication of a non volatile memory cell requires a perfect control of 4 main parameters: (i) the tunnel oxide thickness, (ii) the nanocrystal density, (iii) the nanocrystal diameter, and (iv) the control oxide thickness. In the structures obtained by Ge implantation, it is possible to have a rather good control of the tunnel oxide thickness by using a low energy process. However, other parameters such as densities, diameters, and crystalline quality are not fully controlled. For all the nc-Ge memory structures presented in Ref. [6– 12], the formation of nanocrystals is obtained after oxidation steps. In most of these experiments, it appears quite difficult to control very thin tunnel oxide layers. Nevertheless, in spite of the technological limitations for industrial applications, most of the nc-Ge structures have demonstrated that the Ge/SiO2 system has good electrical data retention properties. In this paper, we propose an electrical study of memory effects in nc-Ge/SiO2 fabricated by Low Pressure Chemical Vapor deposition (LPCVD). The capacitance versus voltage (C – V) and current versus voltage (I –V) measurements have been done in order to study the memory effect in nc-Ge/SiO2. Temperature dependent I – V measurements and current – voltage with different ramp rates have been used in order to
M. Kanoun et al. / Materials Science and Engineering C 26 (2006) 360 – 363
361 from 2 V to -5 V Sample D from -5 V to 2 V Sample D from 2 V to -5 V Sample A from -5 V to 2 V Sample A
1.0
C/Cox
0.8 0.6 0.4 0.2 -5
-4
-3
-2
-1
0
1
2
Gate Voltage Fig. 2. C – V curves recorded at 10 kHz for samples A and D. The gate voltage is swept from inversion to the accumulation then from the accumulation to the inversion.
investigate the data retention mechanism and then to study the displacement of the charges through the tunnel oxide. 2. Experiment details The substrates used in this study are p-type 200 mm Si (100) wafers covered by a thermal SiO2 layer (tunnel oxide). Si nuclei and nc-Ge were grown in a single reduced pressure chemical vapour deposition (CVD) reactor designed by Applied Materials, in which the SiH4 and GeH4 gaseous precursors are diluted in H2. The nc-Ge are grown using a two-step process. First, the SiO2 surface is functionalized by the deposition of Si nuclei using SiH4 as a gaseous precursor. Second, once the Si nuclei are deposited, we stop the SiH4 gas flow, and GeH4 is introduced to selectively grown on the Si nuclei [13,14]. Fig. 1 shows a typical HR-TEM image of Nc-Ges embedded in SiO2 using this process. The NC’s density and diameter size are given by a statistic counting of Scan Electron Microscopy (SEM) images. They are about 6 1011 cm 2 8.5 nm, respectively. The tunnel oxide thickness has been varied from 1.2 to 2.5 nm, while the control oxide remains constant at 10 nm. The samples investigated in this study are described in the Table 1. For the electrical measurements we have deposited a 250 nm thick aluminium gate in order to obtain MOS capacitors. The devices have a square shape with surfaces ranging from 100 100 to 400 400 Am2. C – V and I – V curves have been recorded using a HP 4284 and a HP 4156, respectively.
(+ 2 to 5 V) and forward ( 5 to +2 V) voltage scan is performed, the structures are, respectively, biased from inversion to accumulation conditions, and then from accumulation to inversion. Using such conditions, we observe a significant shift of the C – V curves on the left during the forward scan. This result is consistent with a positive charge trapping in the oxide. As one can see on Fig. 2, the voltage shift is larger for sample D which has a thicker tunnel oxide. This result is explained by the longer retention time of carriers due to exponential decrease of tunnelling mechanism as the thickness increases. The negative voltage shift can be attributed either to a hole trapping mechanism from the substrate, or to an electron emission from the nc-Ge. In our experimental conditions, the phenomenon is more probably attributed to the hole trapping process. Note that for sample A, with a 1.2 nm tunnel oxide, we also observe a variation of the slope of the C – V curve after charge injection. Our hypothesis is that the nc-Ge are sufficiently close to the Si/ SiO2 interface, and their electric charge can modify the density of free carrier in the substrate. In fact, for very thin tunnel oxides, it is possible to consider the Ge dots as an interface traps. This assumption could explain why the slope is very sharp for thick tunnel oxides before and after hole’s charging.
Sample A dtun = 1.2 nm
1E-8
J(A.cm-2)
Fig. 1. HRTEM image of a crystalline isolated Ge nanocrystal. The mean size is equal to 8.5 nm.
3. Results and discussion 1E-9
Fig. 2 shows a comparison of a typical high frequency C –V measurement normalized for devices A and D. When a reverse -6 Table 1 Description of the samples used
-4
-2
0
VG(V)
Samples
A
B
C
D
Tunnel oxide (nm)
1.2
1.5
2
2.5
Fig. 3. Current density versus voltage characteristics of samples A. The I – V curve of sample A exhibits a pick in the accumulation region (negative voltage).
M. Kanoun et al. / Materials Science and Engineering C 26 (2006) 360 – 363
As we can also observe in Fig. 3, the I – V curve exhibits two peaks at low voltage (about 0.25 and 1.35 V) in the accumulation region. This result is reproducible only for the two samples with the thinnest tunnel oxides (samples A and B). These peaks have been observed by other authors at low [17] temperature and at the ambient one [15,16] and are attributed either to the resonant tunneling or to charging effects in the nanocrystals. In our case the first assumption is excluded because of the dissymmetry of the studied structure [13,14]. Indeed, the thickness of the control oxide is 10 nm and that of the tunnel one is 1.2 nm. For this reason we can attribute this current pick to displacement of holes from the accumulation layer to the nc-Ge through the tunnel oxide. In order to confirm assumption two ways have been investigated: The first method consist on low temperature I –V measurements. As shown in Fig. 4 recorded at 77 K, a first measurement on a virgin capacitance exhibits two current peaks respectively at 0.25 and 1.35 V. When a second voltage sweep is done, these picks are shifted by about 2 V on the left in agreement with a strong hole trapping effect. The process is shown to be fully reversible, since it has been possible to discharge the trapped holes by applying a positive bias at + 7 V. Then, when a new sweep is performed, the initial I – V curve is nearly recovered. Such experiments confirm our hypothesis of hole trapping. Such I – V ‘‘hysteresis’’ after several scans is not observed at room temperature because the hole de-trapping mechanism is thermally activated. The second way consists on I – V measurements with different voltage ramps. Before discussing the experimental results let’s introduce the definition of delay time in a current measurement. When a charging effect occurs in a diode structure, out equilibrium state is established, then a change in the potential and the electric field is produced through the structure. In this case we can observe a depending-time-component in the current I – V behaviour. Therefore, we have to distinguish between the static and dynamic I – V characteristics. To obtain the static
Curent density (A. Cm-2)
10-9
10-10
10-11 virgine at 77K first measurement (sample A) Append 1 at 77 K Append 2 at 77 K An append after inversion scan at 77 K
10-12 -6
-4
-2
0
VG(V) Fig. 4. Low temperature I – V measurements (77 K) showing a hysteresis. The current’s pick recovers its initial position after a sweep in the inversion region.
2.7x10-8
J(A.cm-2)
362
dtun 1.5 nm
Os
1.8x10-8 5s 9.0x10-9
12 s
20 s 30 s
0.0 -3
-2
-1
0
VG Fig. 5. Current – voltage measurements for different delays.
characteristics, it is necessary to wait for a certain time until the current becomes a steady state. We define the waiting time until the current measurement after applying each voltage as Fdelay time_, hereafter. I – V characteristics measured under a short delay time show the dynamic behaviour. In Fig. 5, we present the I –V characteristics at low voltages (from 0 to 3 V) using a staircase voltage with different step delays varying from 1 up to 30 s. For short step time delay (faster measurements), the maximum of the current peak is larger. When the step delay increases, the current dip is smaller and tends to disappear for very large time. This result shows that the current is due to a charge displacement with a very large time constant. Since this phenomenon is observed in the accumulation regime of a p-type Si substrate, we attribute it to a hole charging in the dots, from the valence band of the substrate. Indeed, the control oxide is relatively thicker (10 nm) to the tunnel one (1.2 nm), so no current flows through the structure at low voltages until the Fowler – Nordheim injection at high voltage ( 6 V). 4. Conclusion The fabrication of NVM structures using Ge nanocrystals embedded in SiO2 has been demonstrated. The LPCVD process developed in this work is shown to be well suited for a real control of the tunnel oxide thickness. Moreover, the deposition conditions allow a separate control of nc-Ge density and size, as demonstrated by high resolution transmission electron microscopy. The I –V analyses have demonstrated charging effects, and a hysteresis is observed only at low temperatures. These types of measurements show that the phenomenon is reversible, since it is possible to arise the stocked charges. Using current versus voltage measurements at different ramp rates on NVM structures, we have demonstrated that the transient current is due to a hole charging phenomenon. The current peak is higher for the short time delays and tend to disappear for the larger one. The advantages of Ge dots rather than Si are mainly due to a larger barrier height for data retention (4.9 eV) and a heavy effective mass for holes (m h* = 7 m 0). Combined with a good control of nc-Ge properties, the use of Ge dots with large diameters (15 nm) seems to be a promising way for memory applications.
M. Kanoun et al. / Materials Science and Engineering C 26 (2006) 360 – 363
Acknowledgements This work has been done in the frame of ‘‘DOTSET’’ project by Re´gion Rhoˆne-Alpes. References [1] S. Tiwari, F. Rana, H. Hanafi, A. Hrtstein, E.F. Crabbe´, K. Chan, Appl. Phys. Lett. 68 (1996) 1377. [2] S. Tiwari, F. Rana, K. Chan, L. Shi, H. Hanafi, Appl. Phys. Lett. 69 (1996) 1232. [3] B. De Salvo, G. Ghibaudo, G. Pananakakis, B. Guillaumot, T. Baron, Superlattices Microstruct. 28 (2000) 339. [4] Y.C. King, T.J. King, C. Hu, IEEE Trans. Electron Devices 48 (2001) 696. [5] H.I. Hanafi, S. Tiwari, I. Khan, IEEE Trans. Electron Devices 43 (9) (1996) 1553. [6] T. Sass, V. Zela, A. Gustafsson, I. Pietzonka, W. Seifert, Appl. Phys. Lett. 81 (2002) 3455. [7] V. Craciun, I.W. Boyd, A.H. Reader, W.J. Kersten, F.J.G. Hakkens, P.H. Oosting, D.E.W. Vandenhoudt, J. Appl. Phys. 75 (1994) 1972. [8] A. Kanjilal, J. Lundsgaard Hansen, P. Gaiduk, A. Nylandsted Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, D. Tsoukalas, Appl. Phys. Lett. 82 (2003) 1212.
363
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