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Computation of the base resistance of bipolar transistors from layout details including quasi three-dimensional effects
Solid-State
Ehronics
Vol. 31,
No. 8, pp. 1235-1241,
1988
0038-I 101/88
COMPUTATION TRANSISTORS QUASI
$3.00 + 0.00
Copyright0 1988PergamonPressplc
Primedin Great Britain.All rightsreserved
OF THE BASE RESISTANCE OF BIPOLAR FROM LAYOUT DETAILS INCLUDING THREE-DIMENSIONAL EFFECTS FRANCOIS HUBERT and DAVID J. ROULSTON
Electrical Engineering Department, University of Waterloo, Waterloo, Ontario, Canada N2L 3Gl (Received 3 October 1987; in revisedform
6 February 1988)
Abstract-The base resistance which results from the base current bending at the base contact and at the edge of the emitter perimeter is computed (at low currents and low frequencies) using a quasi three-dimensional (Quasi 3-D) solution which uses “counled” 2-D solutions of the cross-section and layout resistances. Empirical equations derived from compute; simulations are presented for the resistance ai the base contact and at the emitter periphery for three different types of base doping profiles. The quasi 3-D solution is used to evaluate the resistance of a test structure (JFET) and good agreement between simulation and experiment is obtained.
1.
INTRODUCTION
The base resistance of bipolar transistors may be computed using simple approximate analytic equations based on 1-D and 2-D current flow models[ l-51 and empirical equations which take into account the geometry of the device[6]. These all neglect the 3-D nature of the transistor since the current bending at and under the base contact and around the emitter perimeter, is not considered. This paper presents a method of solving the 3-D
effects using “coupled” 2-D simulations of the crosssection and of the plane (layout) view of a transistor. After a description of the proposed quasi 3-D solution, the cross-section of typical bipolar transistors will be analyzed and the resistance increase due to current bending at the base contact and emitter edges will be described. These results are then coupled to the plane 2-D simulation of the layout and equations, which may be used to compute the increase in base resistance due to the 3-D current bending, will be presented. This work may be extended to the computation of the resistance of other structures such as pinched resistors and JFETs, and an example is given. 2. PROPOSEDQUASI 3-D SCHEME Extensive studies of the layout of bipolar transistors have been performed using 2-D distributed representations of the transistor[5,6]. These methods essentially assume that the resistivity and thickness of the various regions are uniform in the vertical dimension, i.e. current only flows in the horizontal plane. This is illustrated in Fig. l(a) where it is shown that the cross-section through which the base current flows, is uniform. In a majority of transistors, the base current is 3-D since the current bends at the base contact and at the emitter edge, as illustrated in Fig. SSE Ilr&E!
l(b). Also, the doping profile of typical transistors is such that the resistivity near the collector-base junction is much greater than that at the surface. The cross-section shown in Fig. l(b) may be simulated using the approximate representation of Fig. l(c). Each horizontal rectangle represents a region with constant resistivity corresponding to the doping profile histogram of Fig. l(c). This structure is simulated for various doping profiles (described later) in order to define the increase in resistance to be “coupled” to simulations of the layout. The quasi 3-D simulation of the base resistance is achieved by modifying the layout representation such that the emitter is surrounded by a resistive region which takes into account the vertical current bending solved through simulations of the cross-section. This is shown in Fig. 2 where the typical 2-D resistive grid used in Refs [5] and [6] (Fig. 2a) is modified to include the current bending at the emitter periphery (Fig. 2b). The 3-D correction region which surrounds the emitter is only grid element wide and does not represent any physical layout distances. This is why the region surrounding the emitter is larger by one grid spacing. The sheet resistance of the 3-D correction region, which is a function of the neutral base width and of the base doping profile, is defined in the following section. The intrinsic and extrinsic regions consist of constant resistivity regions, and current sources are connected at each intrinsic nodes in order to emulate a uniform emitter current density, as described in Refs [5] and [6]. d.c. and a.c. current crowding effects are neglected. 3. CROSS-SECTIONAL STUDY The cross-section of typical transistors is simulated using the 2-D simulator described above. The doping profiles considered represent approximately three typical types of bipolar transistors: “power”, “linear”
1235
FRAN~OIS HUBERT and DAVID J. ROULSTON
1236
(a) EMITTER
)
i
BASE CONTACT BASE DOPING
v
BASE DOPING
i _Y X
(cl
Fig. 1. Cross sectional view. (a) Simple 2-D computer solutions assume uniform resistivities, uniform thickness and no current bending at the contacts. (b) In a typical transistor, current bends as it leaves the base contact and reaches the intrinsic region, also the resistivity varies with depth. (c) An approximation
and
“VLSI”
of the cross-section in (b) is carried out using many adjacent regions of different and a small contact at the location of the intrinsic region.
transistor
profiles.
have been fitted expressions, of the form: profiles
using
The
base
modified
4, (x ) = NeP, - KS exp[ - (X ix,
doping
resistance
(in number
of squares).
resistivities
This increase
is:
Gaussian
(2)
PI
(1)
where NePi is the epitaxial collector doping level, Nhr is the base surface concentration, x is the depth into the silicon (x = 0 at the surface), X, is the characteristic length of the profile and Nxb is the exponent of the modified Gaussian. Table 1 summarizes the information used to describe the three typical base profiles selected. The “power” transistor is a discrete double diffused microwave power transistor. The “linear” transistor is a medium power integrated transistor with washed emitter and deep base diffusion to allow for efficient lateral PNP transistors. The “VLSI” transistor is a shallow junction device with selfaligned polysilicon emitter. The main difference in the normalized shapes of the doping profiles is the steepness near the collector-base junction. The steeper the profile near the junction (in this study, the “VLSI” transistor has the steeper profile) the slower the resistivity increases with depth and the lesser the effects of current bending. The resistance due to current bending at the base contact is analyzed first. A. Resistance at a contact The resistance increase due to current bending at the base contacts is evaluated through 2-D simulations of the cross-section shown in Fig. I(c), for the case of W, = X,. The difference between the computed result (RJd) and the estimated results (R,,,, obtained from consideration of the number of squares only, i.e. (Lb/X,) with laminar current flow) is normalized by the extrinsic base sheet resistance in R/square) to solve for an effective increase in (P,,,
(a)
S
“L L % I
q
BASE CONTACT
q?xt
7-
qfint
1
pp
3D
Y
J
f
t
SC
1
i
(b) Fig. 2. Typical layout representation in a 2-D simulator. Current sources are used at each emitter node (region with sheet resistance of p,“, R/square) to represent the emitter current flow. (a) As previously used and (b) modified to simulate the increase in resistance due to the vertical current bending at the emitter periphery.
Base resistance of bipolar transistors Table I.
Base doping profile
parameters
NWI cm-
N, crne3
& pm
Nxb -
X, fim
P,.t D/W
Power
1.5 x IO”
Linear VLSI
1.0 x 10’6 1.6 x 10”
2.0 x IO” I.5 x 10’8 8.0 x 10’8
0.324 1.360 0.222
2 2 4
0.80 3.04 0.35
158 216 470
Type
Values of NC,* of 1.7, 2.1 and 2.7 have been obtained for the “power”, “linear” and “VLSI” profiles, respectively. Variation of the distance between the two contacts in the computer simulations has not been found to vary NcM. The resistance due to current bending at and under the contact (&) is:
Nc3d 4 G’ Rc3d=Pext W,+2L,(l
1237
-exp[-(WJS)])
1’
(3)
where NcJd in the above eqn (2) is the normalized increase in extrinsic resistance (in number of squares) due to current bending at the base contact, as defined above. WCis the contact width (distance perpendicular to base current flow) shown equal to the emitter width (W) in Fig. 2, J!,, is the contact length, W, is the distance between the edge of the contact and the edge of the base region (shown equal to W, in Fig. 2), and S is the overall width of the base region. G’ is the assumed thickness in the z direction of the crosssection simulated using the program. It is expressed as a fraction of the junction depth. In our work, G’ is 0.1. &d is simply added to the extrinsic base resistance described later. This term is usually of the order of a few ohms and reduces as the contact perimeter is increased. B. Resistance around emitter periphery Since the intrinsic region is pinched below the surface by the emitter region, current must bend at the emitter periphery. This results in a non-negligible resistance which is a function of the emitter periphery, the shape of the base doping profile (particularly near the collector-base junction), and the neutral base width (W,). Simulations have been performed using the structure shown in the inset of Fig. 3 for the doping profiles defined above. The resistance between the two terminals is computed for various values of neutral base width to base junction depth ratio (W,/X,), and is subtracted from a reference case of (W, =X,) and normalized by the extrinsic sheet resistance. The resulting relative increase in the extrinsic resistance is a dimensionless factor equivalent to a number of square, defined as N3d. Figure 3 shows N3dplotted vs the normalized base width for the three doping profiles considered here. Variation of the distance between the two contacts (Lb in Fig. 3) has been found to be negligible. For example, simulations of the linear profile, for (W,,/X,) of 0.5, yield an N3d of 4.98 for L, of 3 pm, and N3d of 5.04 for an L, of 6 pm.
0
0
0.5 NORMALIZED BI\SE WIDTH (Wb/xJ)
I.0
Fig. 3. Increase in resistance due to current bending at the emitter periphery for three typical base doping profiles. The inset shows the structure simulated with the 2-D simulator.
The sheet resistance to be used in the quasi 3-D simulations (as shown in Fig. 2b) may be computed from the knowledge of N3d.
where p3d is in n/square, N3d is obtained from Fig. 3 (given W, and the device type), A’,is the base junction depth, G’ defines the thickness of the cross-section used in the computer simulations as a function of Xj (G’ is 0.1 in this work) and G is the dimension of one side of a mesh in the layout view (see Fig. 2) of the distributed network representation (for example, if the emitter is 4 x 4 pm2 and if 4 meshes on a side are used, G is then equal to 1 pm). p;d is an effective resistivity in a-pm (or Q-cm, depending on the units used to define I. and W) around the emitter periphery. 4. QUASI 3-D BASE RESISTANCE
COMPUTATION
The effect of the vertical current bending is studied by comparing quasi 3-D computer simulations to the 2-D base resistance computed using the expressions presented in Ref. [6] (i.e. 2-D simulations without coupled cross-sectional simulations). Two cases are studied: the single base contact and the double base contact layout. The parameters of interest are the effect of the 3-D correction region around the emitter (varied through pM) and the effect of the emitter to base edge spacing (& = (WJL) for the single base contact and Ebs2= (2 W,/L) for the double base contact layout). Two limit cases must be considered: (1) transistor with a walled emitter (Ebs or Ebs2of zero) and (2) transistor with a fully surrounded emitter (Ebs or Ebsz tending to infinity). The single base contact layout of Fig. 2 is considered first. A. Single base contact Computer simulations have been performed for a wide range of Ebs values (O-0.7) and various sheet
FRAN~OISH&BERTand DAVIDJ. ROULSTON
1238
/
I_
SINGLE
NORMALIZED
EASE
CONTACT
3-O
LAYOUT
CORRECTION
I
SHEET
RESISTIVITY
(Pi, ‘P,,+.Wl Fig. 4. Increase
in extrinsic
base resistance due to the current bending at the edge of the emitter single base contact layout of Fig. 2.
resistance values, using the representation of Fig. 2. The normalized result (difference between simulations using the quasi 3-D layout of Fig. 2(b) and the 2-D simulations results[6] using Fig. 2a) are plotted in Fig. 4. The limit cases of Ebs = 0 and Ebs-+ CCare also shown. The current bending at the emitter periphery is found to increase the extrinsic base resistance of the structure. No change in intrinsic resistance when compared to the results of Refs [5] and [6] have been observed. An empirical equation has been derived in order to describe the computer simulation results of Fig. 4, and to permit computation of the extrinsic resistance due to quasi 3-D effects as a function of device geometry and sheet resistances. N,,,r = e
[J + 3 exp(-
6&,
d~)l~
(5)
where
x 11- exp( - 20Eb,)I (6) where N,,,, is the increase in extrinsic base resistance (in number of squares) due to cross-sectional effects, for the single base contact transistor layout, pid is resistivity defined by eqn (4), W is the emitter width and L is the emitter length (see Fig. 2). The form of eqn (5) has been selected such that the asymptotic slopes shown in Fig. 4 are properly represented: for walled structures (EbS = 0) and non-walled structures with an emitter fully surrounded by a contact (Ebs-+ oo), the increase in extrinsic base resistance is directly proportional to increases in the current bending at the emitter periphery (expressed through the normalized 3-D correction sheet resistivity) with a slope of 1 and l/4 respectively. The term defined as “D” and the exponential relationship in eqn (5) represent the variation in the effective emitter perimeter with Ebs.
for the
The total extrinsic base resistance of a single base contact transistor, including contact and emitter cross-sectional effects, may be computed by:
R bx3dl
-
Rbtx,
+
43,
+
Pext
Nb3d,
.
(7)
where Rbbx,is the 2-D extrinsic base resistance defined in Ref. [6], Rc3d is defined by eqn (3) and iVbsd, is defined by eqn (5) above. Equation (5) is valid for any aspect ratios, any geometries and resistivities. The typical error between eqn (5) and the computer simulation is less than 0.05 squares.
B. Double base contact The double base contact layout considered is shown in Fig. 5(a). Due to symmetry, Fig. 5(b) represents exactly half the double base contact structure or a single base contact transistor with a partially walled (side opposite the base contact) emitter. This layout is simulated using the techniques described above and the correction in extrinsic base resistance due to the quasi 3-D effects (in number of squares) is plotted for various cross-sections and geometries in Fig. 6. An empirical equation may be used to represent the results of Fig. 6 and to compute the extrinsic resistance. N b3d?
=
y
{l
+
~~P[-6~bs~(P~d/(P~x~
w))l)
(8)
where
x 11 - exp(-2OE&l,
(9)
where Nb3d2 is the extrinsic resitance correction (in number of squares), for the one contact partially walled layout of Fig. 5(b). Equation (8) is similar to eqn (5) but modified to represent the different asymptotic behaviour of N,,,: for Ebsz> 0.
Base resistance of bipolar transistors
Pmt a-
s
& (a)
Lb-
B
(b)
w
Fig. 5. (a) Double base contact transistor layout. (b) Half of the above or a single base contact structure with a partially walled emitter. The extrinsic base resistance including 3-D effects is therefore: R ~,rm= Rw R bxMlp
-
+ WR,M
Rbbx,p + R,
the quasi
+ ~ex~&d
+ P.w %-z
(10) (11)
for the double base contact transistor eqn (10) and the single contact partially walled emitter eqn (11). R bbx2 or Rbbx@ may be computed using a 2-D simulator or using the empirical equations presented in Ref. [6]. Equation (8) agrees with computer simulations over the full range of Ebsz and many geometries, and the error is typically less than 0.05 squares.
1239
JFET is carried out. The layout of the structure is shown in Fig. 7. The extrinsic sheet resistance (p,,,) of the P type base region is 217 +_5 R/square and the pinched sheet resistance is 9000 + 100 R. The measured gate dimension is 9 x 59 pm2 (L. x W), the base junction depth (X,) is 3.0 and the neutral channel thickness (W,) is 1.5 (dimensions in microns). The measured resistance is Rd = 1570 f 10 fL The computation of the resistance between the 2 contacts neglecting the gate is 92 R using the layout of Fig. 7 and the 2-D simulator. The gate resistance to be added to this figure is 9000(9/59) or 1372 R. The difference between the sum of these two figures and the measured Rd is attributed to the cross-sectional effects. The resistance at the source and drain contacts is evaluated using eqn (3), assuming a “linear” type process. The resistance at one of the contacts is Rc3,,= 2.9 R (using eqn (3), a contact width of 30, contact length L, of 9, contact to base spacing of 15 and a base region width of 59 pm). The resistance due to the current bending at the edge of the gate is evaluated using Fig. 3 and eqns (5) and (8), noting that the structure is effectively walled (i.e. Ebs or Ebs2 of zero). From Fig. 3, N3d is found to be 5.0 since (W,/X,) is 0.5. The correction resistivity around the emitter is therefore pi,, = (5 x 217 x 3 x 0.1) = 0.03255 Rem, and the resistance correction factor is N b3d,= 0.0254 (found using eqns (5) or (8), since the structure is walled, both yield the same result). The source-drain resistance of the JFET is therefore computed using eqn (7) (with an extra factor of 2 since there are two contacts and current flows through the two edges of the gate): (12)
&M = Rsdzd+ 2(%, + PextNb3dr ) 5. EXPERIMENTAL
VERIFICATION
In order to easily verify the above quasi 3-D technique, and since the separate measurement of the intrinsic and extrinsic base resistance of a transistor of the is rather difficult, the measurement source-drain resistance (R,) of a bipolar compatible
= (92 + 1372) + 2[2.9 + (217 x 0.0254)]
(13)
= 1481 R
(14)
r----l i l--1
GATE 1 I
0
3X3pn2
HALF DOUBLE BASE CONTACT LAW
i 0 NORMALIZED
0.5 3-D CORRECTION ( Pid ‘P,,P
1.0 SHEET RESISTIVITY
I
1
Fig. 6. Increase in extrinsic base resistance due to the current bending at the edge of the emitter for the double base contact layout of Fig. 5(b).
’
; I
I
,
I
I
L--J
Fig. 7. Layout of the test JFET used to experimentally verify .__ . the quasi 3-D method.
FRANCOIS HUBERT and DAVID J. ROULSTON
1240
r’
ONE BASE
L Fig. 8. Layout
6. TYPICAL APPLICATION
above
equations
are
OF THE FORMULAE
used
to examine
Table 2. Computed base resistance of single and double base contact transistor of unity aspect ratio 2-D I Base contact 2 Base contacts
0.4 x 0.4 pm2
Quasi 3-D
f&b,
R bbX
187.0 117.9
600.4 262.7
AR,,,
53.9 33. I
line indicates
the
The increase in extrinsic resistance due to 3-D effects is found to be 9% and 13% for the non-walled single and double base contact layouts of Fig. 8. respectively. This increase in extrinsic resistance reduces as the base width to base junction depth ratio approaches 1 (i.e. as the emitter becomes shallower) and as the base doping profile becomes more uniform. It is the largest for walled, small aspect ratio transistors.
the
component of base resistance of a VLSI shallow junction transistor with a polysilicon contacted emitter, due to vertical current bending at the emitter periphery and at the base contacts. Two different layouts are considered, both shown in Fig. 8. These are the single base contact (base edge away from base contact shown dashed) and the double base contact layouts. The emitter and base contacts are 2 x 2 pm* (unity aspect ratio), the alignment tolerance is (dimensions in pm) 0.6 (W, and W, of 0.6, Ebs = 0.3 and Ebs2 = 0.6), L, = S = 3.2. The base profile is described using the modified Gaussian defined by eqn (1) and the data of Table 1 (“VLSI” transistor with X, of 0.35 pm, and pext of 470 n/square). The emitter-base junction depth is 0.18 and the neutral base width, computed using the device simulator BIPOLE[7], is 0.12. The intrinsic sheet resistance is 3230 R/square. The 3-D correction sheet resistance is computed using eqn (4) and Fig. 3 is used to define N3d (N,d = 9 for (W,/X,) = 0.34). The relative resistance increase due to current bending at the emitter periphery is computed using eqn (5) (single base contact) and eqn (8) (double base contact). The resistance due to current bending at the base contacts is 8.2 R per contact, as computed using eqn (3) (N,,, of 2.7 as described above). The total increase in extrinsic base resistance due to the 3-D effects when compared to 2-D simulations, defined as AR,,,, is summarized in Table 2, along with the 2-D simulation results (in 0) obtained using equations presented in Ref. [6].
Layout
BOUNDARY
of the simulated bipolar transistor using 2 pm design rules. The dashed base perimeter for the single base contact case.
where R,,, is the resistance computed using the 2-D program and a simple consideration of the number of squares for the pinched resistance. This compares very well with the measured value of 1570n (5.7% error). Since the gate is relatively long, the 3-D effect is very small.
The
0
CONTACT
R&X
654.3 295.8
7. CONCLUSIONS
A quasi 3-D method of solving for the base resistance of bipolar transistors using a 2-D distributed network solver is proposed. The technique is used to study the resistance due to current bending at the base contact and at the edge the emitter region. Three different base doping profiles have been considered and empirical equations are given in order to compute the resistance. The technique is used to compute the source+&ain resistance of a JFET, and very good agreement between measurement and simulations (or empirical equations) as achieved when the quasi 3-D method is applied. The typical increase in extrinsic base resistance due to vertical current bending (when compared to 2-D simulations) is of the order of more than 10%. This reduces as the ratio of neutral base width to collector-base junction depth increases, and as the base doping profile becomes more uniform.
Acknowledgemenr-This
work was supported by the Natural Sciences and Engineering Research Council of Canada. Ottawa.
Note added in proof Two modifications in Ref. [6] should be carried out in order to improve the accuracy of the calculation of the intrinsic base resistance and extrinsic base resistance of single base contact transistors with non-unity aspect ratios. In the computation of the intrinsic base resistance reduction factor (K,), the factor C, (eqn (13) in Ref. [6]) should be defined as: C, = (I/E&Z + (2/E,,)
+ 5[( W/L) - l]“‘t”H
’ ‘(1. (15)
The extra factor of 5 in front of the last term of eqn (13) of Ref. [6] does not affect K, when unity aspect ratio ((W/L) = 1) transistor are considered.
Base resistance of bipolar transistors In the computation of the extrinsic base resistance of the single base contact transistor, the factor Nbe, (eqn (15) in Ref. [6]) should be defined as: Nbc, = ( W/L)-0.2387(2.87E~~2~) (16) The change of the first exponent in eqn (15) of Ref. [6] to -0.2387 does not affect N,, when unity aspect ratio transistors are considered.
1241
REFERENCES 1. J. M. Early, Bell Syst. tech. J. 32, 1271 (1953). 2. J. M. Early, Bell Syst. tech. J. 33, 517 (1954). 3. J. R. Hauser, IEEE Trans. Electron Dev. ED-11, 238 (1964). A. B. Philips, Transistor Engineering, pp. 21 I-216. 4. c McGraw-Hill, New York: (1962). E. A. Valsamakis, IEEE Trans. Electron Dev. ED-33, ” 303 (1986). 6 F. H&ert and D. J. Roulston, Solid-St. Electron. 31, 283 (1988). D. J. Roulston, IEEE Custom Integrated Circuits Conf.. Rochester, New York, 229-232 (1980).
Ehronics
Vol. 31,
No. 8, pp. 1235-1241,
1988
0038-I 101/88
COMPUTATION TRANSISTORS QUASI
$3.00 + 0.00
Copyright0 1988PergamonPressplc
Primedin Great Britain.All rightsreserved
OF THE BASE RESISTANCE OF BIPOLAR FROM LAYOUT DETAILS INCLUDING THREE-DIMENSIONAL EFFECTS FRANCOIS HUBERT and DAVID J. ROULSTON
Electrical Engineering Department, University of Waterloo, Waterloo, Ontario, Canada N2L 3Gl (Received 3 October 1987; in revisedform
6 February 1988)
Abstract-The base resistance which results from the base current bending at the base contact and at the edge of the emitter perimeter is computed (at low currents and low frequencies) using a quasi three-dimensional (Quasi 3-D) solution which uses “counled” 2-D solutions of the cross-section and layout resistances. Empirical equations derived from compute; simulations are presented for the resistance ai the base contact and at the emitter periphery for three different types of base doping profiles. The quasi 3-D solution is used to evaluate the resistance of a test structure (JFET) and good agreement between simulation and experiment is obtained.
1.
INTRODUCTION
The base resistance of bipolar transistors may be computed using simple approximate analytic equations based on 1-D and 2-D current flow models[ l-51 and empirical equations which take into account the geometry of the device[6]. These all neglect the 3-D nature of the transistor since the current bending at and under the base contact and around the emitter perimeter, is not considered. This paper presents a method of solving the 3-D
effects using “coupled” 2-D simulations of the crosssection and of the plane (layout) view of a transistor. After a description of the proposed quasi 3-D solution, the cross-section of typical bipolar transistors will be analyzed and the resistance increase due to current bending at the base contact and emitter edges will be described. These results are then coupled to the plane 2-D simulation of the layout and equations, which may be used to compute the increase in base resistance due to the 3-D current bending, will be presented. This work may be extended to the computation of the resistance of other structures such as pinched resistors and JFETs, and an example is given. 2. PROPOSEDQUASI 3-D SCHEME Extensive studies of the layout of bipolar transistors have been performed using 2-D distributed representations of the transistor[5,6]. These methods essentially assume that the resistivity and thickness of the various regions are uniform in the vertical dimension, i.e. current only flows in the horizontal plane. This is illustrated in Fig. l(a) where it is shown that the cross-section through which the base current flows, is uniform. In a majority of transistors, the base current is 3-D since the current bends at the base contact and at the emitter edge, as illustrated in Fig. SSE Ilr&E!
l(b). Also, the doping profile of typical transistors is such that the resistivity near the collector-base junction is much greater than that at the surface. The cross-section shown in Fig. l(b) may be simulated using the approximate representation of Fig. l(c). Each horizontal rectangle represents a region with constant resistivity corresponding to the doping profile histogram of Fig. l(c). This structure is simulated for various doping profiles (described later) in order to define the increase in resistance to be “coupled” to simulations of the layout. The quasi 3-D simulation of the base resistance is achieved by modifying the layout representation such that the emitter is surrounded by a resistive region which takes into account the vertical current bending solved through simulations of the cross-section. This is shown in Fig. 2 where the typical 2-D resistive grid used in Refs [5] and [6] (Fig. 2a) is modified to include the current bending at the emitter periphery (Fig. 2b). The 3-D correction region which surrounds the emitter is only grid element wide and does not represent any physical layout distances. This is why the region surrounding the emitter is larger by one grid spacing. The sheet resistance of the 3-D correction region, which is a function of the neutral base width and of the base doping profile, is defined in the following section. The intrinsic and extrinsic regions consist of constant resistivity regions, and current sources are connected at each intrinsic nodes in order to emulate a uniform emitter current density, as described in Refs [5] and [6]. d.c. and a.c. current crowding effects are neglected. 3. CROSS-SECTIONAL STUDY The cross-section of typical transistors is simulated using the 2-D simulator described above. The doping profiles considered represent approximately three typical types of bipolar transistors: “power”, “linear”
1235
FRAN~OIS HUBERT and DAVID J. ROULSTON
1236
(a) EMITTER
)
i
BASE CONTACT BASE DOPING
v
BASE DOPING
i _Y X
(cl
Fig. 1. Cross sectional view. (a) Simple 2-D computer solutions assume uniform resistivities, uniform thickness and no current bending at the contacts. (b) In a typical transistor, current bends as it leaves the base contact and reaches the intrinsic region, also the resistivity varies with depth. (c) An approximation
and
“VLSI”
of the cross-section in (b) is carried out using many adjacent regions of different and a small contact at the location of the intrinsic region.
transistor
profiles.
have been fitted expressions, of the form: profiles
using
The
base
modified
4, (x ) = NeP, - KS exp[ - (X ix,
doping
resistance
(in number
of squares).
resistivities
This increase
is:
Gaussian
(2)
PI
(1)
where NePi is the epitaxial collector doping level, Nhr is the base surface concentration, x is the depth into the silicon (x = 0 at the surface), X, is the characteristic length of the profile and Nxb is the exponent of the modified Gaussian. Table 1 summarizes the information used to describe the three typical base profiles selected. The “power” transistor is a discrete double diffused microwave power transistor. The “linear” transistor is a medium power integrated transistor with washed emitter and deep base diffusion to allow for efficient lateral PNP transistors. The “VLSI” transistor is a shallow junction device with selfaligned polysilicon emitter. The main difference in the normalized shapes of the doping profiles is the steepness near the collector-base junction. The steeper the profile near the junction (in this study, the “VLSI” transistor has the steeper profile) the slower the resistivity increases with depth and the lesser the effects of current bending. The resistance due to current bending at the base contact is analyzed first. A. Resistance at a contact The resistance increase due to current bending at the base contacts is evaluated through 2-D simulations of the cross-section shown in Fig. I(c), for the case of W, = X,. The difference between the computed result (RJd) and the estimated results (R,,,, obtained from consideration of the number of squares only, i.e. (Lb/X,) with laminar current flow) is normalized by the extrinsic base sheet resistance in R/square) to solve for an effective increase in (P,,,
(a)
S
“L L % I
q
BASE CONTACT
q?xt
7-
qfint
1
pp
3D
Y
J
f
t
SC
1
i
(b) Fig. 2. Typical layout representation in a 2-D simulator. Current sources are used at each emitter node (region with sheet resistance of p,“, R/square) to represent the emitter current flow. (a) As previously used and (b) modified to simulate the increase in resistance due to the vertical current bending at the emitter periphery.
Base resistance of bipolar transistors Table I.
Base doping profile
parameters
NWI cm-
N, crne3
& pm
Nxb -
X, fim
P,.t D/W
Power
1.5 x IO”
Linear VLSI
1.0 x 10’6 1.6 x 10”
2.0 x IO” I.5 x 10’8 8.0 x 10’8
0.324 1.360 0.222
2 2 4
0.80 3.04 0.35
158 216 470
Type
Values of NC,* of 1.7, 2.1 and 2.7 have been obtained for the “power”, “linear” and “VLSI” profiles, respectively. Variation of the distance between the two contacts in the computer simulations has not been found to vary NcM. The resistance due to current bending at and under the contact (&) is:
Nc3d 4 G’ Rc3d=Pext W,+2L,(l
1237
-exp[-(WJS)])
1’
(3)
where NcJd in the above eqn (2) is the normalized increase in extrinsic resistance (in number of squares) due to current bending at the base contact, as defined above. WCis the contact width (distance perpendicular to base current flow) shown equal to the emitter width (W) in Fig. 2, J!,, is the contact length, W, is the distance between the edge of the contact and the edge of the base region (shown equal to W, in Fig. 2), and S is the overall width of the base region. G’ is the assumed thickness in the z direction of the crosssection simulated using the program. It is expressed as a fraction of the junction depth. In our work, G’ is 0.1. &d is simply added to the extrinsic base resistance described later. This term is usually of the order of a few ohms and reduces as the contact perimeter is increased. B. Resistance around emitter periphery Since the intrinsic region is pinched below the surface by the emitter region, current must bend at the emitter periphery. This results in a non-negligible resistance which is a function of the emitter periphery, the shape of the base doping profile (particularly near the collector-base junction), and the neutral base width (W,). Simulations have been performed using the structure shown in the inset of Fig. 3 for the doping profiles defined above. The resistance between the two terminals is computed for various values of neutral base width to base junction depth ratio (W,/X,), and is subtracted from a reference case of (W, =X,) and normalized by the extrinsic sheet resistance. The resulting relative increase in the extrinsic resistance is a dimensionless factor equivalent to a number of square, defined as N3d. Figure 3 shows N3dplotted vs the normalized base width for the three doping profiles considered here. Variation of the distance between the two contacts (Lb in Fig. 3) has been found to be negligible. For example, simulations of the linear profile, for (W,,/X,) of 0.5, yield an N3d of 4.98 for L, of 3 pm, and N3d of 5.04 for an L, of 6 pm.
0
0
0.5 NORMALIZED BI\SE WIDTH (Wb/xJ)
I.0
Fig. 3. Increase in resistance due to current bending at the emitter periphery for three typical base doping profiles. The inset shows the structure simulated with the 2-D simulator.
The sheet resistance to be used in the quasi 3-D simulations (as shown in Fig. 2b) may be computed from the knowledge of N3d.
where p3d is in n/square, N3d is obtained from Fig. 3 (given W, and the device type), A’,is the base junction depth, G’ defines the thickness of the cross-section used in the computer simulations as a function of Xj (G’ is 0.1 in this work) and G is the dimension of one side of a mesh in the layout view (see Fig. 2) of the distributed network representation (for example, if the emitter is 4 x 4 pm2 and if 4 meshes on a side are used, G is then equal to 1 pm). p;d is an effective resistivity in a-pm (or Q-cm, depending on the units used to define I. and W) around the emitter periphery. 4. QUASI 3-D BASE RESISTANCE
COMPUTATION
The effect of the vertical current bending is studied by comparing quasi 3-D computer simulations to the 2-D base resistance computed using the expressions presented in Ref. [6] (i.e. 2-D simulations without coupled cross-sectional simulations). Two cases are studied: the single base contact and the double base contact layout. The parameters of interest are the effect of the 3-D correction region around the emitter (varied through pM) and the effect of the emitter to base edge spacing (& = (WJL) for the single base contact and Ebs2= (2 W,/L) for the double base contact layout). Two limit cases must be considered: (1) transistor with a walled emitter (Ebs or Ebs2of zero) and (2) transistor with a fully surrounded emitter (Ebs or Ebsz tending to infinity). The single base contact layout of Fig. 2 is considered first. A. Single base contact Computer simulations have been performed for a wide range of Ebs values (O-0.7) and various sheet
FRAN~OISH&BERTand DAVIDJ. ROULSTON
1238
/
I_
SINGLE
NORMALIZED
EASE
CONTACT
3-O
LAYOUT
CORRECTION
I
SHEET
RESISTIVITY
(Pi, ‘P,,+.Wl Fig. 4. Increase
in extrinsic
base resistance due to the current bending at the edge of the emitter single base contact layout of Fig. 2.
resistance values, using the representation of Fig. 2. The normalized result (difference between simulations using the quasi 3-D layout of Fig. 2(b) and the 2-D simulations results[6] using Fig. 2a) are plotted in Fig. 4. The limit cases of Ebs = 0 and Ebs-+ CCare also shown. The current bending at the emitter periphery is found to increase the extrinsic base resistance of the structure. No change in intrinsic resistance when compared to the results of Refs [5] and [6] have been observed. An empirical equation has been derived in order to describe the computer simulation results of Fig. 4, and to permit computation of the extrinsic resistance due to quasi 3-D effects as a function of device geometry and sheet resistances. N,,,r = e
[J + 3 exp(-
6&,
d~)l~
(5)
where
x 11- exp( - 20Eb,)I (6) where N,,,, is the increase in extrinsic base resistance (in number of squares) due to cross-sectional effects, for the single base contact transistor layout, pid is resistivity defined by eqn (4), W is the emitter width and L is the emitter length (see Fig. 2). The form of eqn (5) has been selected such that the asymptotic slopes shown in Fig. 4 are properly represented: for walled structures (EbS = 0) and non-walled structures with an emitter fully surrounded by a contact (Ebs-+ oo), the increase in extrinsic base resistance is directly proportional to increases in the current bending at the emitter periphery (expressed through the normalized 3-D correction sheet resistivity) with a slope of 1 and l/4 respectively. The term defined as “D” and the exponential relationship in eqn (5) represent the variation in the effective emitter perimeter with Ebs.
for the
The total extrinsic base resistance of a single base contact transistor, including contact and emitter cross-sectional effects, may be computed by:
R bx3dl
-
Rbtx,
+
43,
+
Pext
Nb3d,
.
(7)
where Rbbx,is the 2-D extrinsic base resistance defined in Ref. [6], Rc3d is defined by eqn (3) and iVbsd, is defined by eqn (5) above. Equation (5) is valid for any aspect ratios, any geometries and resistivities. The typical error between eqn (5) and the computer simulation is less than 0.05 squares.
B. Double base contact The double base contact layout considered is shown in Fig. 5(a). Due to symmetry, Fig. 5(b) represents exactly half the double base contact structure or a single base contact transistor with a partially walled (side opposite the base contact) emitter. This layout is simulated using the techniques described above and the correction in extrinsic base resistance due to the quasi 3-D effects (in number of squares) is plotted for various cross-sections and geometries in Fig. 6. An empirical equation may be used to represent the results of Fig. 6 and to compute the extrinsic resistance. N b3d?
=
y
{l
+
~~P[-6~bs~(P~d/(P~x~
w))l)
(8)
where
x 11 - exp(-2OE&l,
(9)
where Nb3d2 is the extrinsic resitance correction (in number of squares), for the one contact partially walled layout of Fig. 5(b). Equation (8) is similar to eqn (5) but modified to represent the different asymptotic behaviour of N,,,: for Ebsz> 0.
Base resistance of bipolar transistors
Pmt a-
s
& (a)
Lb-
B
(b)
w
Fig. 5. (a) Double base contact transistor layout. (b) Half of the above or a single base contact structure with a partially walled emitter. The extrinsic base resistance including 3-D effects is therefore: R ~,rm= Rw R bxMlp
-
+ WR,M
Rbbx,p + R,
the quasi
+ ~ex~&d
+ P.w %-z
(10) (11)
for the double base contact transistor eqn (10) and the single contact partially walled emitter eqn (11). R bbx2 or Rbbx@ may be computed using a 2-D simulator or using the empirical equations presented in Ref. [6]. Equation (8) agrees with computer simulations over the full range of Ebsz and many geometries, and the error is typically less than 0.05 squares.
1239
JFET is carried out. The layout of the structure is shown in Fig. 7. The extrinsic sheet resistance (p,,,) of the P type base region is 217 +_5 R/square and the pinched sheet resistance is 9000 + 100 R. The measured gate dimension is 9 x 59 pm2 (L. x W), the base junction depth (X,) is 3.0 and the neutral channel thickness (W,) is 1.5 (dimensions in microns). The measured resistance is Rd = 1570 f 10 fL The computation of the resistance between the 2 contacts neglecting the gate is 92 R using the layout of Fig. 7 and the 2-D simulator. The gate resistance to be added to this figure is 9000(9/59) or 1372 R. The difference between the sum of these two figures and the measured Rd is attributed to the cross-sectional effects. The resistance at the source and drain contacts is evaluated using eqn (3), assuming a “linear” type process. The resistance at one of the contacts is Rc3,,= 2.9 R (using eqn (3), a contact width of 30, contact length L, of 9, contact to base spacing of 15 and a base region width of 59 pm). The resistance due to the current bending at the edge of the gate is evaluated using Fig. 3 and eqns (5) and (8), noting that the structure is effectively walled (i.e. Ebs or Ebs2 of zero). From Fig. 3, N3d is found to be 5.0 since (W,/X,) is 0.5. The correction resistivity around the emitter is therefore pi,, = (5 x 217 x 3 x 0.1) = 0.03255 Rem, and the resistance correction factor is N b3d,= 0.0254 (found using eqns (5) or (8), since the structure is walled, both yield the same result). The source-drain resistance of the JFET is therefore computed using eqn (7) (with an extra factor of 2 since there are two contacts and current flows through the two edges of the gate): (12)
&M = Rsdzd+ 2(%, + PextNb3dr ) 5. EXPERIMENTAL
VERIFICATION
In order to easily verify the above quasi 3-D technique, and since the separate measurement of the intrinsic and extrinsic base resistance of a transistor of the is rather difficult, the measurement source-drain resistance (R,) of a bipolar compatible
= (92 + 1372) + 2[2.9 + (217 x 0.0254)]
(13)
= 1481 R
(14)
r----l i l--1
GATE 1 I
0
3X3pn2
HALF DOUBLE BASE CONTACT LAW
i 0 NORMALIZED
0.5 3-D CORRECTION ( Pid ‘P,,P
1.0 SHEET RESISTIVITY
I
1
Fig. 6. Increase in extrinsic base resistance due to the current bending at the edge of the emitter for the double base contact layout of Fig. 5(b).
’
; I
I
,
I
I
L--J
Fig. 7. Layout of the test JFET used to experimentally verify .__ . the quasi 3-D method.
FRANCOIS HUBERT and DAVID J. ROULSTON
1240
r’
ONE BASE
L Fig. 8. Layout
6. TYPICAL APPLICATION
above
equations
are
OF THE FORMULAE
used
to examine
Table 2. Computed base resistance of single and double base contact transistor of unity aspect ratio 2-D I Base contact 2 Base contacts
0.4 x 0.4 pm2
Quasi 3-D
f&b,
R bbX
187.0 117.9
600.4 262.7
AR,,,
53.9 33. I
line indicates
the
The increase in extrinsic resistance due to 3-D effects is found to be 9% and 13% for the non-walled single and double base contact layouts of Fig. 8. respectively. This increase in extrinsic resistance reduces as the base width to base junction depth ratio approaches 1 (i.e. as the emitter becomes shallower) and as the base doping profile becomes more uniform. It is the largest for walled, small aspect ratio transistors.
the
component of base resistance of a VLSI shallow junction transistor with a polysilicon contacted emitter, due to vertical current bending at the emitter periphery and at the base contacts. Two different layouts are considered, both shown in Fig. 8. These are the single base contact (base edge away from base contact shown dashed) and the double base contact layouts. The emitter and base contacts are 2 x 2 pm* (unity aspect ratio), the alignment tolerance is (dimensions in pm) 0.6 (W, and W, of 0.6, Ebs = 0.3 and Ebs2 = 0.6), L, = S = 3.2. The base profile is described using the modified Gaussian defined by eqn (1) and the data of Table 1 (“VLSI” transistor with X, of 0.35 pm, and pext of 470 n/square). The emitter-base junction depth is 0.18 and the neutral base width, computed using the device simulator BIPOLE[7], is 0.12. The intrinsic sheet resistance is 3230 R/square. The 3-D correction sheet resistance is computed using eqn (4) and Fig. 3 is used to define N3d (N,d = 9 for (W,/X,) = 0.34). The relative resistance increase due to current bending at the emitter periphery is computed using eqn (5) (single base contact) and eqn (8) (double base contact). The resistance due to current bending at the base contacts is 8.2 R per contact, as computed using eqn (3) (N,,, of 2.7 as described above). The total increase in extrinsic base resistance due to the 3-D effects when compared to 2-D simulations, defined as AR,,,, is summarized in Table 2, along with the 2-D simulation results (in 0) obtained using equations presented in Ref. [6].
Layout
BOUNDARY
of the simulated bipolar transistor using 2 pm design rules. The dashed base perimeter for the single base contact case.
where R,,, is the resistance computed using the 2-D program and a simple consideration of the number of squares for the pinched resistance. This compares very well with the measured value of 1570n (5.7% error). Since the gate is relatively long, the 3-D effect is very small.
The
0
CONTACT
R&X
654.3 295.8
7. CONCLUSIONS
A quasi 3-D method of solving for the base resistance of bipolar transistors using a 2-D distributed network solver is proposed. The technique is used to study the resistance due to current bending at the base contact and at the edge the emitter region. Three different base doping profiles have been considered and empirical equations are given in order to compute the resistance. The technique is used to compute the source+&ain resistance of a JFET, and very good agreement between measurement and simulations (or empirical equations) as achieved when the quasi 3-D method is applied. The typical increase in extrinsic base resistance due to vertical current bending (when compared to 2-D simulations) is of the order of more than 10%. This reduces as the ratio of neutral base width to collector-base junction depth increases, and as the base doping profile becomes more uniform.
Acknowledgemenr-This
work was supported by the Natural Sciences and Engineering Research Council of Canada. Ottawa.
Note added in proof Two modifications in Ref. [6] should be carried out in order to improve the accuracy of the calculation of the intrinsic base resistance and extrinsic base resistance of single base contact transistors with non-unity aspect ratios. In the computation of the intrinsic base resistance reduction factor (K,), the factor C, (eqn (13) in Ref. [6]) should be defined as: C, = (I/E&Z + (2/E,,)
+ 5[( W/L) - l]“‘t”H
’ ‘(1. (15)
The extra factor of 5 in front of the last term of eqn (13) of Ref. [6] does not affect K, when unity aspect ratio ((W/L) = 1) transistor are considered.
Base resistance of bipolar transistors In the computation of the extrinsic base resistance of the single base contact transistor, the factor Nbe, (eqn (15) in Ref. [6]) should be defined as: Nbc, = ( W/L)-0.2387(2.87E~~2~) (16) The change of the first exponent in eqn (15) of Ref. [6] to -0.2387 does not affect N,, when unity aspect ratio transistors are considered.
1241
REFERENCES 1. J. M. Early, Bell Syst. tech. J. 32, 1271 (1953). 2. J. M. Early, Bell Syst. tech. J. 33, 517 (1954). 3. J. R. Hauser, IEEE Trans. Electron Dev. ED-11, 238 (1964). A. B. Philips, Transistor Engineering, pp. 21 I-216. 4. c McGraw-Hill, New York: (1962). E. A. Valsamakis, IEEE Trans. Electron Dev. ED-33, ” 303 (1986). 6 F. H&ert and D. J. Roulston, Solid-St. Electron. 31, 283 (1988). D. J. Roulston, IEEE Custom Integrated Circuits Conf.. Rochester, New York, 229-232 (1980).