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Debug Registers Quick Reference
APPENDIX E
Debug Registers Quick Reference Overview The Cortex-M0 debug system contains a number of programmable registers. These registers can be accessed by an in-circuit debuggers only and cannot be accessed by the application software. This quick reference is intended for tools developers, or if you are using a debugger that supports debug scripts (e.g., RealView Debugger), you can use debug scripts to access to these registers to carry out testing operations automatically. The debug system in the Cortex-M0 is partitioned into the following segments: • • • •
Debug support in the processor core Breakpoint unit Data watchpoint unit ROM table.
System-on-chip developers can add debug support components if required. If additional debug components are added, another ROM table unit can also be added to the system so that a debugger can identify available debug components included in the system. The debug support is configurable; some Cortex-M0 based products might not have any debug support.
Core Debug Registers The processor core contains a number of registers for debug purpose.
Address
Name
0xE000ED24
SHCSR
0xE000ED30
DFSR
0xE000EDF0
DHCSR
0xE000EDF4
DCRSR
Descriptions System Handler Control and State Registerdindicate system exception status Debug Fault Status Registerdallow debugger to determine the cause of halting Debug Halting Control and Status Registerdcontrol processor debug activities like halting, single stepping, restart Debug Core Register Selector Registerdcontrol read and write of core registers during halt (Continued)
461
462 Appendix E Address
Name
0xE000EDF8
DCRDR
0xE000EDFC
DEMCR
0xE000EFD0 to 0xE000EFFC
PIDs, CIDs
Descriptions Debug Core Register Data Registerddata transfer register for reading or writing core registers during halt Debug Exception Monitor Control Registerdfor enabling of data watchpoint unit and vector catch feature; vector catch allows the debugger to halt the processor if the processor is reset or if a hard fault exception is triggered ID registers
System Handler Control and State Register (0xE000ED24) Bits
Field
Type
Reset Value
Descriptions
31:16 15
Reserved SVCALLPENDED
d RO
d 0
14:0
Reserved
d
d
Reserved 1 indicates SVC execution is pended; accessible from debugger only Reserved
Debug Fault Status Register (0xE000ED30) Bits
Field
Type
Reset Value
Descriptions
31:5 4 3 2 1 0
Reserved EXTERNAL VCATCH DWTTRAP BKPT HALTED
d RWc RWc RWc RWc RWc
d 0 0 0 0 0
Reserved EDBGRQ was asserted Vector catch occurred Data watchpoint occurred Breakpoint occurred Halted by debugger or single stepping
Debug Halting Control and Status Register (0xE000EDF0) Bits
Field
Type
Reset Value
Descriptions Debug Key. During write, the value of 0xA05F must be used on the top 16-bit. Otherwise the write is ignored. Reset status flag (sticky). Core has been reset or being reset; this bit is clear on read. Instruction is completed since last read; this bit is clear on reset.
31:16
DBGKEY (during write)
WO
d
25
S_RESET_ST (during read)
RO
d
24
S_RETIRE_ST (during read)
RO
d
(Continued)
Debug Registers Quick Reference 463 Bits
Field
Type
Reset Value
Descriptions When this bit is 1, the core is in lockup state. When this bit is 1, the core is sleeping. When this bit is 1, the core is halted. When this bit is 1, the core completed a register read or register write operation. Reserved. Mask exceptions while stepping (does not affect NMI and hard fault); valid only if C_DEBUGEN is set. Single step control. Set this to 1 to carry out single step operation; valid only if C_DEBUGEN is set. Halt control. This bit is only valid when C_DEBUGEN is set. Debug enable. Set this bit to 1 to enable debug.
19
S_LOCKUP
RO
d
18 17 16
S_SLEEP S_HALT (during read) S_REGRDY_ST
RO RO RO
d d d
15:4 3
Reserved C_MASKINTS
d R/W
d 0
2
C_STEP
R/W
0
1
C_HALT
R/W
0
0
C_DEBUGEN
R/W
0
Debug Core Register Selector Register (0xE000EDF4) Bits
Field
Type
Reset Value
Descriptions
31:17 16
Reserved REGWnR
d WO
d d
15:5 4:0
Reserved REGSEL
d WO
d 0
Reserved Set to 1 to write value to register Set to 0 to read value from register Reserved Register select
Debug Core Register Data Register (0xE000EDF8) Bits
Field
Type
Reset Value
Descriptions
31:0
DBGTMP
RW
0
Data value for the core register transfer
Debug Exception and Monitor Control Register (0xE000EDFC) Bits 31:25 24 23:11
Field Reserved DWTENA Reserved
Type
Reset Value
Descriptions
d RW d
d 0 d
Reserved Data watchpoint unit enable Reserved (Continued)
464 Appendix E Bits
Field
Type
Reset Value
10
VC_HARDERR
RW
0
9:1 0
Reserved VC_CORERESET
d RW
d 0
Descriptions Debug trap at hard fault exception Reserved Halt processor after system reset and before the first instruction executed
Breakpoint Unit The breakpoint unit contains up to four comparators for instruction breakpoints. Each comparator can produce a breakpoint for up to two instructions (if the two instructions are located in the same word address). Additional breakpoints can be implemented by inserting breakpoint instructions in the program image if the program memory can be modified. The breakpoint unit design is configurable. Some microcontrollers might contain no breakpoint unit or a breakpoint unit with fewer than four comparators.
Address
Name
0xE0002000
BP_CTRL
0xE0002008 0xE000200C 0xE0002010 0xE0002014 0xE0002FD0 to 0xE0002FFC
BP_COMP0 BP_COMP1 BP_COMP2 BP_COMP3 PIDs, CIDs
Descriptions Breakpoint Control Registerdfor enabling the breakpoint unit and provide information about the breakpoint unit Breakpoint Comparator Register 0 Breakpoint Comparator Register 1 Breakpoint Comparator Register 2 Breakpoint Comparator Register 3 ID registers
Breakpoint Control Register (0xE0002000) Bits
Field
Type
Reset Value
Descriptions
31:17 7:4 3:2 1
Reserved NUM_CODE Reserved KEY
d RO d WO
d 0 to 4 d d
0
ENABLE
RW
0
Reserved Number of comparators Reserved Write Keydwhen there is a write operation to this register, this bit should be set to 1, otherwise the write operation is ignored Enable control
Debug Registers Quick Reference 465 Breakpoint Comparator Registers (0xE0002008e0xE0002014) Bits
Field
Type
Reset Value
Descriptions
31:30
BP_MATCH
RW
d
29 28:2 1 0
Reserved COMP Reserved ENABLE
d RW d RW
d d d 0
Breakpoint setting: 00: No breakpoint 01: Breakpoint at lower half word address 10: Breakpoint at upper half word address 11: Breakpoint at both lower and upper half word Reserved Compare instruction address Reserved Enable control for this comparator
Data Watchpoint Unit The data watchpoint unit has two main functions: • •
Setting data watchpoints Providing a PC sampling register for basic profiling
Before accessing the DWT, the TRCENA bit in Debug Exception and Monitor Control Register (DEMCR, address 0xE000EDFC) must be set to 1 to enable the DWT. Unlike the Data Watchpoint and Trace unit in the Cortex-M3/M4, the DWT in the Cortex-M0 does not support trace. But the programming models of its registers are mostly compatible to the DWT in ARMv7-M. The DWT design is configurable. Some microcontrollers might contain no DWT or a DWT with just 1 comparator. Address
Name
0xE0001000
DWT_CTRL
0xE000101C
DWT_PCSR
0xE0001020 0xE0001024 0xE0001028 0xE0001030 0xE0001034 0xE0001038 0xE0001FD0 to 0xE0001FFC
DWT_COMP0 DWT_MASK0 DWT_FUNCTION0 DWT_COMP1 DWT_MASK1 DWT_FUNCTION1 PIDs, CIDs
Descriptions DWT Control Registerdprovide information about the data watchpoint unit Program Counter Sample Registerdprovide current program address Comparator Register 0 Mask Register 0 Function Register 0 Comparator Register 1 Mask Register 1 Function Register 1 ID registers
DWT Control Register (0xE0001000) Bits 31:28 27:0
Field
Type
Reset Value
Descriptions
NUMCOMP Reserved
RO d
0 to 2 d
Number of comparator implemented Reserved
466 Appendix E Program Counter Sample Register (0xE000101C) Bits
Field
Type
Reset Value
Descriptions
31:0
EIASAMPLE
RO
d
Execution instruction address sample; read as 0xFFFFFFFF if core is halted or if DWTENA is 0
DWT COMP0 Register and DWT COMP1 Registers (0xE0001020, 0xE0001030) Bits
Field
Type
Reset Value
Descriptions
31:0
COMP
RW
d
Address value to compare to; the value must be aligned to the compare address range defined by the compare mask register
DWT MASK0 Register and DWT MASK1 Registers (0xE0001024, 0xE0001034) Bits
Field
Type
Reset Value
31:4 3:0
Reserved MASK
d RW
d d
Descriptions Reserved Mask pattern: 0000: compare mask 0001: compare mask . 1110: compare mask 1111: compare mask
¼ 0xFFFFFFFF ¼ 0xFFFFFFFE ¼ 0xFFFFC000 ¼ 0xFFFF8000
DWT FUNC0 Register and DWT FUNC1 Registers (0xE0001028, 0xE0001038) Bits
Field
Type
Reset Value
Descriptions
31:4 3:0
Reserved FUNC
d RW
d 0
Reserved Function: 0000: Disable 0100: Watchpoint on PC match 0101: Watchpoint on read address 0110: Watchpoint on write address 0111: Watchpoint on read or write address Other values: Reserved
ROM Table Registers The ROM table is used to allow a debugger to identify available components in the system. The lowest two bits of each entry are used to indicate if the debug component is present
Debug Registers Quick Reference 467 and if there is another valid entry following in the next address in the ROM table. The rest of the bits in the ROM table contain the address offset of the debug unit from the ROM table base address:
Address
Value
Name
0xE00FF000
0xFFF0F003
SCS
0xE00FF004 0xE00FF008 0xE00FF00C 0xE00FFFCC
0xFFF02003 0xFFF03003 0x00000000 0x00000001
DWT BPU end MEMTYPE
0xE00FFFD0 to 0xE00FFFFC
0x000000–
IDs
Descriptions Points to System Control Space base address 0xE000E000 Points to DW base address 0xE0001000 Points to BPU base address 0xE0002000 End of table marker Indicates that system memory is accessible on this memory map Peripheral ID and component ID values (values dependent on the design versions)
Using the ROM table, the debugger can identify the debug components available as shown in Figure E.1. The ROM table lookup can be divided into multiple stages if a system-on-chip design contains additional debug components and an extra ROM table. In such cases, the ROM table lookup can be cascaded so that the debugger can identify all the debug components available (Figure E.2).
Debugger connection (JTAG / Serial Wire)
Debug interface
Debugger goes through each entry in the ROM table
base address
ID registers
The debug components are identified by their ID values
ROM table SCS / NVIC
468 Appendix E
Debugger detects connection of debug interface and obtains the ROM table address
SCS / NVIC
Debugger can then determine available debug features by other registers in the debug components
DWT unit BP unit
ID registers
DWT Number of WatchPoints ID registers
FPB
ID registers
Figure E.1: The debugger can use the ROM table to detect available debug components automatically.
Number of BreakPoints
Debugger connection (JTAG / Serial Wire)
Debugger detects connection of debug interface and obtains the ROM table address
Debugger goes through each entry in the ROM table
Debug interface
Primary ROM table
base address
The debug components are identified by their ID values Debug unit X
Debugger can then determine available debug features by other registers in the debug compoents
Debug unit X ID registers Debug unit Y
ID registers
Cortex-M0 ROM table
Debug unit Y
ID registers Cortex-M0 ROM table
SCS / NVIC
SCS / NVIC DWT unit
ID registers
DWT Number of WatchPoints ID registers
FPB
ID registers
Figure E.2: Multistage ROM table lookup when additional debug components are present.
Number of BreakPoints
Debug Registers Quick Reference 469
BP unit
Debug Registers Quick Reference Overview The Cortex-M0 debug system contains a number of programmable registers. These registers can be accessed by an in-circuit debuggers only and cannot be accessed by the application software. This quick reference is intended for tools developers, or if you are using a debugger that supports debug scripts (e.g., RealView Debugger), you can use debug scripts to access to these registers to carry out testing operations automatically. The debug system in the Cortex-M0 is partitioned into the following segments: • • • •
Debug support in the processor core Breakpoint unit Data watchpoint unit ROM table.
System-on-chip developers can add debug support components if required. If additional debug components are added, another ROM table unit can also be added to the system so that a debugger can identify available debug components included in the system. The debug support is configurable; some Cortex-M0 based products might not have any debug support.
Core Debug Registers The processor core contains a number of registers for debug purpose.
Address
Name
0xE000ED24
SHCSR
0xE000ED30
DFSR
0xE000EDF0
DHCSR
0xE000EDF4
DCRSR
Descriptions System Handler Control and State Registerdindicate system exception status Debug Fault Status Registerdallow debugger to determine the cause of halting Debug Halting Control and Status Registerdcontrol processor debug activities like halting, single stepping, restart Debug Core Register Selector Registerdcontrol read and write of core registers during halt (Continued)
461
462 Appendix E Address
Name
0xE000EDF8
DCRDR
0xE000EDFC
DEMCR
0xE000EFD0 to 0xE000EFFC
PIDs, CIDs
Descriptions Debug Core Register Data Registerddata transfer register for reading or writing core registers during halt Debug Exception Monitor Control Registerdfor enabling of data watchpoint unit and vector catch feature; vector catch allows the debugger to halt the processor if the processor is reset or if a hard fault exception is triggered ID registers
System Handler Control and State Register (0xE000ED24) Bits
Field
Type
Reset Value
Descriptions
31:16 15
Reserved SVCALLPENDED
d RO
d 0
14:0
Reserved
d
d
Reserved 1 indicates SVC execution is pended; accessible from debugger only Reserved
Debug Fault Status Register (0xE000ED30) Bits
Field
Type
Reset Value
Descriptions
31:5 4 3 2 1 0
Reserved EXTERNAL VCATCH DWTTRAP BKPT HALTED
d RWc RWc RWc RWc RWc
d 0 0 0 0 0
Reserved EDBGRQ was asserted Vector catch occurred Data watchpoint occurred Breakpoint occurred Halted by debugger or single stepping
Debug Halting Control and Status Register (0xE000EDF0) Bits
Field
Type
Reset Value
Descriptions Debug Key. During write, the value of 0xA05F must be used on the top 16-bit. Otherwise the write is ignored. Reset status flag (sticky). Core has been reset or being reset; this bit is clear on read. Instruction is completed since last read; this bit is clear on reset.
31:16
DBGKEY (during write)
WO
d
25
S_RESET_ST (during read)
RO
d
24
S_RETIRE_ST (during read)
RO
d
(Continued)
Debug Registers Quick Reference 463 Bits
Field
Type
Reset Value
Descriptions When this bit is 1, the core is in lockup state. When this bit is 1, the core is sleeping. When this bit is 1, the core is halted. When this bit is 1, the core completed a register read or register write operation. Reserved. Mask exceptions while stepping (does not affect NMI and hard fault); valid only if C_DEBUGEN is set. Single step control. Set this to 1 to carry out single step operation; valid only if C_DEBUGEN is set. Halt control. This bit is only valid when C_DEBUGEN is set. Debug enable. Set this bit to 1 to enable debug.
19
S_LOCKUP
RO
d
18 17 16
S_SLEEP S_HALT (during read) S_REGRDY_ST
RO RO RO
d d d
15:4 3
Reserved C_MASKINTS
d R/W
d 0
2
C_STEP
R/W
0
1
C_HALT
R/W
0
0
C_DEBUGEN
R/W
0
Debug Core Register Selector Register (0xE000EDF4) Bits
Field
Type
Reset Value
Descriptions
31:17 16
Reserved REGWnR
d WO
d d
15:5 4:0
Reserved REGSEL
d WO
d 0
Reserved Set to 1 to write value to register Set to 0 to read value from register Reserved Register select
Debug Core Register Data Register (0xE000EDF8) Bits
Field
Type
Reset Value
Descriptions
31:0
DBGTMP
RW
0
Data value for the core register transfer
Debug Exception and Monitor Control Register (0xE000EDFC) Bits 31:25 24 23:11
Field Reserved DWTENA Reserved
Type
Reset Value
Descriptions
d RW d
d 0 d
Reserved Data watchpoint unit enable Reserved (Continued)
464 Appendix E Bits
Field
Type
Reset Value
10
VC_HARDERR
RW
0
9:1 0
Reserved VC_CORERESET
d RW
d 0
Descriptions Debug trap at hard fault exception Reserved Halt processor after system reset and before the first instruction executed
Breakpoint Unit The breakpoint unit contains up to four comparators for instruction breakpoints. Each comparator can produce a breakpoint for up to two instructions (if the two instructions are located in the same word address). Additional breakpoints can be implemented by inserting breakpoint instructions in the program image if the program memory can be modified. The breakpoint unit design is configurable. Some microcontrollers might contain no breakpoint unit or a breakpoint unit with fewer than four comparators.
Address
Name
0xE0002000
BP_CTRL
0xE0002008 0xE000200C 0xE0002010 0xE0002014 0xE0002FD0 to 0xE0002FFC
BP_COMP0 BP_COMP1 BP_COMP2 BP_COMP3 PIDs, CIDs
Descriptions Breakpoint Control Registerdfor enabling the breakpoint unit and provide information about the breakpoint unit Breakpoint Comparator Register 0 Breakpoint Comparator Register 1 Breakpoint Comparator Register 2 Breakpoint Comparator Register 3 ID registers
Breakpoint Control Register (0xE0002000) Bits
Field
Type
Reset Value
Descriptions
31:17 7:4 3:2 1
Reserved NUM_CODE Reserved KEY
d RO d WO
d 0 to 4 d d
0
ENABLE
RW
0
Reserved Number of comparators Reserved Write Keydwhen there is a write operation to this register, this bit should be set to 1, otherwise the write operation is ignored Enable control
Debug Registers Quick Reference 465 Breakpoint Comparator Registers (0xE0002008e0xE0002014) Bits
Field
Type
Reset Value
Descriptions
31:30
BP_MATCH
RW
d
29 28:2 1 0
Reserved COMP Reserved ENABLE
d RW d RW
d d d 0
Breakpoint setting: 00: No breakpoint 01: Breakpoint at lower half word address 10: Breakpoint at upper half word address 11: Breakpoint at both lower and upper half word Reserved Compare instruction address Reserved Enable control for this comparator
Data Watchpoint Unit The data watchpoint unit has two main functions: • •
Setting data watchpoints Providing a PC sampling register for basic profiling
Before accessing the DWT, the TRCENA bit in Debug Exception and Monitor Control Register (DEMCR, address 0xE000EDFC) must be set to 1 to enable the DWT. Unlike the Data Watchpoint and Trace unit in the Cortex-M3/M4, the DWT in the Cortex-M0 does not support trace. But the programming models of its registers are mostly compatible to the DWT in ARMv7-M. The DWT design is configurable. Some microcontrollers might contain no DWT or a DWT with just 1 comparator. Address
Name
0xE0001000
DWT_CTRL
0xE000101C
DWT_PCSR
0xE0001020 0xE0001024 0xE0001028 0xE0001030 0xE0001034 0xE0001038 0xE0001FD0 to 0xE0001FFC
DWT_COMP0 DWT_MASK0 DWT_FUNCTION0 DWT_COMP1 DWT_MASK1 DWT_FUNCTION1 PIDs, CIDs
Descriptions DWT Control Registerdprovide information about the data watchpoint unit Program Counter Sample Registerdprovide current program address Comparator Register 0 Mask Register 0 Function Register 0 Comparator Register 1 Mask Register 1 Function Register 1 ID registers
DWT Control Register (0xE0001000) Bits 31:28 27:0
Field
Type
Reset Value
Descriptions
NUMCOMP Reserved
RO d
0 to 2 d
Number of comparator implemented Reserved
466 Appendix E Program Counter Sample Register (0xE000101C) Bits
Field
Type
Reset Value
Descriptions
31:0
EIASAMPLE
RO
d
Execution instruction address sample; read as 0xFFFFFFFF if core is halted or if DWTENA is 0
DWT COMP0 Register and DWT COMP1 Registers (0xE0001020, 0xE0001030) Bits
Field
Type
Reset Value
Descriptions
31:0
COMP
RW
d
Address value to compare to; the value must be aligned to the compare address range defined by the compare mask register
DWT MASK0 Register and DWT MASK1 Registers (0xE0001024, 0xE0001034) Bits
Field
Type
Reset Value
31:4 3:0
Reserved MASK
d RW
d d
Descriptions Reserved Mask pattern: 0000: compare mask 0001: compare mask . 1110: compare mask 1111: compare mask
¼ 0xFFFFFFFF ¼ 0xFFFFFFFE ¼ 0xFFFFC000 ¼ 0xFFFF8000
DWT FUNC0 Register and DWT FUNC1 Registers (0xE0001028, 0xE0001038) Bits
Field
Type
Reset Value
Descriptions
31:4 3:0
Reserved FUNC
d RW
d 0
Reserved Function: 0000: Disable 0100: Watchpoint on PC match 0101: Watchpoint on read address 0110: Watchpoint on write address 0111: Watchpoint on read or write address Other values: Reserved
ROM Table Registers The ROM table is used to allow a debugger to identify available components in the system. The lowest two bits of each entry are used to indicate if the debug component is present
Debug Registers Quick Reference 467 and if there is another valid entry following in the next address in the ROM table. The rest of the bits in the ROM table contain the address offset of the debug unit from the ROM table base address:
Address
Value
Name
0xE00FF000
0xFFF0F003
SCS
0xE00FF004 0xE00FF008 0xE00FF00C 0xE00FFFCC
0xFFF02003 0xFFF03003 0x00000000 0x00000001
DWT BPU end MEMTYPE
0xE00FFFD0 to 0xE00FFFFC
0x000000–
IDs
Descriptions Points to System Control Space base address 0xE000E000 Points to DW base address 0xE0001000 Points to BPU base address 0xE0002000 End of table marker Indicates that system memory is accessible on this memory map Peripheral ID and component ID values (values dependent on the design versions)
Using the ROM table, the debugger can identify the debug components available as shown in Figure E.1. The ROM table lookup can be divided into multiple stages if a system-on-chip design contains additional debug components and an extra ROM table. In such cases, the ROM table lookup can be cascaded so that the debugger can identify all the debug components available (Figure E.2).
Debugger connection (JTAG / Serial Wire)
Debug interface
Debugger goes through each entry in the ROM table
base address
ID registers
The debug components are identified by their ID values
ROM table SCS / NVIC
468 Appendix E
Debugger detects connection of debug interface and obtains the ROM table address
SCS / NVIC
Debugger can then determine available debug features by other registers in the debug components
DWT unit BP unit
ID registers
DWT Number of WatchPoints ID registers
FPB
ID registers
Figure E.1: The debugger can use the ROM table to detect available debug components automatically.
Number of BreakPoints
Debugger connection (JTAG / Serial Wire)
Debugger detects connection of debug interface and obtains the ROM table address
Debugger goes through each entry in the ROM table
Debug interface
Primary ROM table
base address
The debug components are identified by their ID values Debug unit X
Debugger can then determine available debug features by other registers in the debug compoents
Debug unit X ID registers Debug unit Y
ID registers
Cortex-M0 ROM table
Debug unit Y
ID registers Cortex-M0 ROM table
SCS / NVIC
SCS / NVIC DWT unit
ID registers
DWT Number of WatchPoints ID registers
FPB
ID registers
Figure E.2: Multistage ROM table lookup when additional debug components are present.
Number of BreakPoints
Debug Registers Quick Reference 469
BP unit