Design and implementation of fast current releasing DC circuit breaker

Electric Power Systems Research 151 (2017) 218–232

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Design and implementation of fast current releasing DC circuit breaker Ataollah Mokhberdoran a,∗ , Adriano Carvalho a , Nuno Silva b , Helder Leite a , Antonio Carrapatoso a a b

Department of Electrical and Computer Engineering of University of Porto, Rua Doutor Roberto Frias, 4200-465 Porto, Portugal EFACEC Energia Mquinas e Equipamentos Elctricos, S.A, Un. Switchgear & Automation, Rua Frederico Ulrich, 3078, 4471-907 Maia, Portugal

a r t i c l e

i n f o

Article history: Received 22 September 2016 Received in revised form 21 April 2017 Accepted 25 May 2017 Keywords: DC circuit breaker Fault protection HVDC transmission Switching overvoltage Fault currents

a b s t r a c t Interruption of DC fault current in a DC system is more complex as compared to the AC one due to the high rate of rise of fault current and absence of natural zero crossing. Fast and hard switching action in DC current interruption causes excessive voltage across the circuit breaker. This paper investigates a new type of solid-state DC circuit breaker namely current releasing DC circuit breaker. The mechanism of current interruption in the current releasing DC circuit breaker is analyzed through an aggregated model. The design procedure is defined and simulation results are presented. In addition, a sensitivity analysis is carried out. Finally, the experimental results from a lab-scale prototype as a proof of concept are demonstrated. This study confirms that the current interruption time of the current releasing DC circuit breaker is remarkably less than the typical solid-state DC circuit breakers and it requires less number of semiconductors in its main breaking branch. Although the current releasing DC circuit breaker does not have any surge arrester in its structure, its switching surge voltage is significantly limited. © 2017 Elsevier B.V. All rights reserved.

1. Introduction High voltage direct current (HVDC) transmission technology has been identified as the most efficient choice for transmission of bulk amount of electrical energy over long distances. The increasing demand on development of large offshore wind farms located far from the coast and also the emerging multi-terminal HVDC (MTHVDC) grid concept make this technology more attractive than the past. Introduction of insulated gate bipolar transistor (IGBT) in 1990s led to development of high power voltage source converters (VSCs). Technical and economic studies prove the feasibility of MT-HVDC grids based on the VSCs [1,2]. Most of the VSCs are highly vulnerable against DC side short circuit faults. Therefore, to protect the power converters from high and sharp short circuit currents, different DC circuit breaker (DCCB) technologies have been developed [3,4]. The requirement for DCCBs can be reduced by DC fault tolerant VSC topologies but it cannot be eliminated [5]. In last decades, attempts include research on electromechanical, solid-state and hybrid DCCBs. The electromechanical DCCBs

∗ Corresponding author. E-mail address: [email protected] (A. Mokhberdoran). http://dx.doi.org/10.1016/j.epsr.2017.05.032 0378-7796/© 2017 Elsevier B.V. All rights reserved.

(MCB) has negligible power losses but they have a long operating time, in the order of 30–50 ms. Although recent developments have reduced the operating time significantly, with operating times in the range of 8–10 ms [6], it may not be still enough for protection of MT-HVDC grid. The hybrid DCCB (HCB) has low power losses and an operating time in the order of few milliseconds (2.5–3 ms) [7]. Although the solid-state DC circuit breakers (SSCBs) have higher power losses as compared to the MCB and HCB, they are technically attractive due to their ultra-fast current interruption performance [5,4,7,8]. The SSCBs can interrupt fault currents near instantaneously in the order of a few hundreds of micro second, and much faster than the MCBs [5,4]. Moreover, the improvements and the expectation for more advances in the field of high power semiconductor switches and also wide-band gap devices can be listed as the main motivations of research on the SSCBs. Furthermore, the HCBs utilize a solid-state breaker branch to interrupt the fault current and therefore the improvements in the SSCB technology may also improve the performance of HCBs [9]. A typical SSCB is composed of series and parallel connections of gate controlled semiconductor switches. In addition, a large surge arrester branch is required in parallel connection with the main current branch to limit the transient interruption voltage (TIV) and absorb the released energy [10]. The break-down voltage of SSCB must be chosen at least equal to 1.5 pu [10]. Prototypes of typical

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SSCB in lab scales have been implemented based on the mentioned requirements and presented in [11,12]. Conduction power losses and large clamping voltage and energy absorption ratings of surge arrester branch have been identified as drawbacks of typical SSCB [13,11,5,4]. Recent investigations are focused on reducing the conduction power losses and eliminating the surge arrester branches. The application of resonant type DC/DC converter in protection of DC grids has been proposed in [13]. Although the proposed solution does not require large surge arresters, its implementation cost and switching losses still might be high. A different topology of SSCB aiming to eliminate the surge arrester branch is proposed in [14]. Although the proposed SSCB does not require surge arrester branch, it employs two full rated coupled inductors, two full rated resistors and two full rated capacitors together with a full rated diode [14]. Two thyristor based SSCBs are introduced in [15,16] aiming to reduce the conduction power losses. However, the proposed topologies utilizes additional full rated components and their application in HVDC grids is not clear due to the simple study models. A research on separation the of energy absorption and overvoltage suppression branches has been conducted in [17]. A surge-less SSCB is proposed and discussed in [18] and the authors propose an overvoltage limiting and energy absorbing branch including diodes, resistors and none-linear surge arresters [18]. The proposed topology still employs surge arrester banks but in reduced voltage and energy ratings. The application of wide band gap devices in SSCB implementation have been investigated in [19–26]. The higher blocking voltage of single wide band gap semiconductor switches may lead to reduction in conduction power losses. However, the mentioned type switches are not commercially available in high voltage and high current levels. This paper focuses on a surge-less fast SSCB topology, which is called current releasing DC circuit breaker (CRCB). The CRCB has different operation principles as compared to the typical SSCBs and previously proposed SSCBs in the literature. The proposed topology aims to reduce the voltage rating of solid-state breaking branch and consequently on-state power losses by eliminating large TIV across the circuit breaker. Despite existing literature, the performance of proposed CRCB has been studied through detailed simulation models employing state of the art models of multi-terminal HVDC grids and frequency dependent model of HVDC cable. After the introduction, the switching overvoltage phenomena in SSCBs will be reviewed in Section 2. The operation principles of CRCB is explained in Section 3. Section 4 includes the analysis of the CRCB through an aggregated model. Design remarks are provided in Section 5 and the impacts of variation in different CRCB and system parameters are investigated through the sensitivity analysis in Section 6. The proposed CRCB is integrated into a four-terminal HVDC grid model, which is equipped by a state of art fast fault identification system and the simulation results are presented in Section 7. Finally, the paper is concluded in Section 9 after demonstrating the experimental results from an implemented lab-scale prototype in Section 8.

219

Fig. 1. Typical solid-state circuit breaker.

Fig. 2. Topology of current releasing DC circuit breaker (CRCB).

The voltage across the SSCB without surge arrester after current interruption instance can be given by: vcb (t) = Vdc − (Lcb + Ll )

dicb (t) − Rl icb (t); dt

t > tbr

(1)

where icb (t) represents the current flowing through the SSCB. Eq. (1) implies that vcb can reach higher values than Vdc , if (Lcb + Ll )dicb (t)/dt + Rl icb (t) < 0. In fact, icb (t)/dt always has negative values for t > tbr due to the continuous decrease in fault current after current interruption at t = tbr . Also, the absolute value of dicb (t)/dt can reach high values since the high fault current (several kilo amperes) falls to zero in a very short period of time (few tens of microseconds in case of SSCB). On the other hand, the multiplication of line resistance and the fault current (Rl icb (t)) is also negligible against dicb (t)/dt. Hence, the voltage across the switch can easily reach higher values than its rated voltage value. Typically, the surge voltage across the SSCB is limited by nonlinear surge arresters, which would be connected in parallel with the SSCB [5]. The surge arrester is shown in gray color in Fig. 1. 3. Current releasing DC circuit breaker

2. Solid-state DC circuit breakers

3.1. Improved topology

The power semiconductor switches are able to cut the current in less than few tens of microseconds. Interrupting the DC current is more complex as compared to the AC current due to the lack of natural zero crossing [27]. Furthermore, the inductive elements of system oppose the current interruption and in case of a hard switching action a high surge voltage appears across the switch, which may push it out of its safe operation area. Fig. 1 shows a typical SSCB feeding a load through an inductive transmission line. Assume that a short circuit fault occurs at t = tf and connects point F to the ground. Also, assume that the SSCB is opened at t = tbr .

The original CRCB topology has been proposed by authors of this paper in [28]. However, the proposed topology has been improved by adding few components in its structure. The improved topology of CRCB is depicted in Fig. 2. The CRCB is composed of main breaker (MB) unit, charging branch, discharging branch, capacitor and current limiting inductor. The MB unit of CRCB can be realized by series and parallel connection of the semiconductor switches. As can be seen in Fig. 2, the semiconductor switches in the MB unit are connected in one direction, which implies that the CRCB is able to interrupt the current only in its forward direction (line

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Fig. 3. CRCB integrated to different HVDC configurations: (a) asymmetric monopole, (b) symmetric monopole, (c) bipolar.

side). The current flow in the backward direction (converter side) of the CRCB cannot be interrupted by the CRCB. Hence, the proposed CRCB is a unidirectional type DCCB. Due to their lower implementation cost, the unidirectional DCCBs are attractive to be employed in protection of MT-HVDC grid using directional protection strategies [29]. The charging branch consists of a thyristor bank (Tch ), a resistor (Rch ) and a low voltage gate controlled semiconductor switch (Qch ). The discharging branch is also composed of a thyristor bank (TF ), a resistor (Rcb ) and a low voltage gate controlled semiconductor switch (QF ). Qch and QF are added into the original topology of CRCB in order to avoid the thyristor commutation failure during the charging and discharging stages. 3.2. Operation principles The CRCB can be integrated into the existing HVDC configurations including asymmetric and symmetric monopole and bipolar systems. Fig. 3 shows the CRCB integration into the different HVDC configurations. The metallic return path might be installed in the asymmetric monopole and the bipole systems. Therefore, the metallic return is depicted by dashed line in Fig. 3(a) and (c). The operation principles of CRCB are detailed for the asymmetric monopole system and pole-to-ground fault in this subsection. However, the operation procedure for a pole-to-pole fault in symmetric monopole system is similar to a pole-to-ground fault in asymmetric monopole system but two CRCBs at both positive and negative poles of VSC must trip. The pole-to-ground fault interruption process in the bipolar system is identical to the pole-to-ground fault in an asymmetric monopole system. 3.2.1. Normal conduction mode When the CRCB is in open mode, all the switches in the MB unit (Q1 − Qn ) are turned off. TF should not be triggered whereas Qch and QF must be close. The CRCB can be closed by turning on all the switches in the MB unit. The prerequisite of current interruption in the fault operation mode is the capacitor Ccb charging stage, which can be done upon energization of the DC bus side of the CRCB. The charging stage can start by triggering the gate of Tch . The charging current peak is limited by Rch . Although Tch would be naturally turned off after Ccb is charged up to the system voltage level, the commutation failures may happen. Therefore, Qch is included in the topology of CRCB and always stays in the close state and only will be turned off for a short period of time when the capacitor is charged up and its voltage is close to the system voltage level. Hence, Qch has a reduced voltage rating, which is equal to the difference between the system and the charged capacitor voltage. Ccb must be kept charged and if its voltage drops more than specific values the charging process must be repeated. Note that when the

CRCB is closed the current can flow in its forward and backward directions due to presence of antiparallel diodes of the switches in the MB unit. 3.2.2. Current interruption mode Upon detection of a fault on a transmission line both CRCBs attached to the faulty transmission line should trip. The time delay between the trip command and fault inception depends on the protection scheme features. To interrupt the fault current and isolate it from the VSC the MB unit must be opened and TF should be triggered. Triggering TF discharges Ccb to the faulted transmission line and feeds the fault point by the limited energy of capacitor. In fact, discharging the capacitor does not allow the voltage of point A (see Fig. 2) to become negative. Therefore, the switches in the MB unit turn off softly without high surge voltage. Stored energy in the inductance of cable and current limiting inductor is also discharged and dissipated in the Rcb , cable resistance and fault resistance. To avoid commutation failures in TF a low voltage gate controlled switch (QF ) is added to the CRCB topology. QF should be turned off for a short period of time after the capacitor is discharged in order to cut the residual current and commutate the TF . The current interruption time of CRCB is expected to be in the order of a few hundreds of micro-second. The line demagnetization process would be below 100 ms depending on the CRCB internal and system parameters. 4. Analysis 4.1. Asymmetric monopole system This section aims to clarify the surge-less operation of the proposed CRCB and define the maximum ratings of components to be used in design process through the equivalent circuit analysis. A pole-to-ground fault in an asymmetric monopole system divides the system in two independent sections. In order to analyze the CRCB behavior one section should be considered. Fig. 4 depicts a simple study system. After current interruption, the CRCB voltage depends upon the voltage at point 1 and 2. v1 depends on the

Fig. 4. Simplified study system.

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221

Fig. 5. (a) and (b) Equivalent circuit of a simple DC system in presence of the CRCB.

power converter behavior after current interruption. In the analysis of this section, v1 is assumed to be constant during and after fault interruption Therefore, the VSC is modeled as a constant DC voltage source. However, the impact of VSC behavior on the vcb will be discussed later in Section 7. v2 depends on the transmission line characteristics. The HVDC transmission line parameters have a frequency dependent behavior. The line inductance reduces significantly during the DC fault due to the high frequency components of DC fault [30]. Also the transmission line resistance increase due to the skin affect caused by the DC fault current [30]. The CRCB contains a relatively large capacitor as compared to the transmission line capacitance and hence dominates the circuit behavior after current interruption. Therefore, the transmission line is modeled by its high frequency inductance and resistance during the current interruption and its capacitance is neglected. The results from analysis will be compared to the simulation results from simulation of distributed frequency dependent model in Section 7. Fig. 5(a) depicts the equivalent circuit of study system when a pole-to-ground fault occurs. The other parameters of the circuit can be given as: • • • • • • • •

sw1 : Thyristor TF sw2 : Main breaker unit (Series connection of Q1 ,. . .,Qn ) Rcb : CRCB resistor Ccb : CRCB capacitor Lcb : Current limiting inductor RLHF : Transmission line high frequency resistance LLHF : Transmission line high frequency inductance Rf : Fault resistance

L=

R = Rf + RLHF

iL (tbr ) = imax

(4)

The damping factor of the RLC circuit can be given by (5). R + Rcb = 2

 Ccb L

(5)

When  > 1 the circuit has an over-damped response and for  < 1 the response is under-damped. For proper operation of CRCB it is necessary to avoid line current oscillation. Therefore, the internal parameters of CRCB should be designed to keep the circuit in overdamped regime. Hence, here the behavior of circuit for the overdamped condition is analyzed. Solving the second order differential equation, the line current can be given by (6). (6)

where −(R + Rcb ) + s1 = 2L −(R + Rcb ) − s2 = 2L k1 =

1 s1 − s2

k2 =

1 s2 − s1

 

(R + Rcb )2 1 − LCcb 4L2

(7)

(R + Rcb )2 1 − LCcb 4L2

(8)

 V − (R + R )i C0 cb max L

 V − (R + R )i C0 cb max L

− s2 imax

− s1 imax

 (9)

 (10)

(2)

Based on the CRCB operation principles, it is assumed that sw2 is opened and almost simultaneously sw1 is closed at time t = tbr . At the interruption instance the voltage of CRCB capacitor is equal to VC0 . Hence, the initial conditions of the circuit can be approximately given by: vC (tbr ) = VC0

d2 iL (t) (R + Rcb ) diL (t) 1 + iL (t) = 0 + · L LCcb dt dt 2

iL (t) = k1 es1 t + k2 es2 t

To analyze the circuit, semiconductor switches are replaced by ideal switches. The equivalent circuit of the system can be aggregated more by combining few elements of the circuit. Fig. 5(b) shows the aggregated equivalent circuit of the system. As it is illustrated in (2), L represents the sum of current limiting inductor and the line high frequency inductance and also R represents the sum of fault and transmission line high frequency resistances. Lcb + LLHF

where vC (tbr ) and iL (tbr ) are the initial voltage of CRCB capacitor and the initial current in its inductor, respectively. imax is the fault current magnitude at the interruption instance. After switching action is done at t = tbr , the depicted equivalent circuit in Fig. 5 represents a second order series RLC circuit. The well-known differential equation for this circuit is given by (4) [31].

Assuming vA (in Fig. 5) equal to Vdc after opening sw2 , vcb (t) can be derived as (11). vcb (t) = Vdc − k1 s1 Les1 t − k2 s2 Les2 t − RiL

The current peak in the transmission line after interruption instant can be given by: s1

(3)

(11)

I L, max = k1 (−

s2

k1 s1 s2 −s1 k1 s1 s2 −s1 ) + k2 (− ) k2 s2 k2 s2

(12)

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Fig. 6. Equivalent circuit of the bipole HVDC system: (a) pole-to-pole-to-ground, (b) pole-to-pole short circuit fault.

The maximum TIV across the main breaker unit can be given by (13)

 V cb,max = Vdc

−k1 (R + Ls1 ) −

 −k2 (R + Ls2 ) −

k1 s12

 s1

s2 − s1

k2 s22

 s2 2

k1 s1

(13)

s2 − s1

k2 s22

4.2. Bipolar system In bipolar HVDC configuration, three types of fault should be taken into account: pole-to-ground, pole-to-pole and pole-to-poleto-ground faults. Pole-to-ground fault in one pole of bipolar system is similar to the pole-to-ground fault in the asymmetric monopole system. Therefore, the analysis from Section 4.1 is valid for the mentioned type of fault in bipolar HVDC systems. Fig. 6(a) shows the simplified equivalent circuit in presence of a low impedance poleto-pole-to-ground short circuit fault in a bipolar configuration. It can be seen in Fig. 6(a) that the circuit can be analyzed as two independent circuits. Hence, the obtained equations in Section 4.1 are also valid for this case. Fig. 6(b) shows the simplified equivalent circuit of the bipolar system during a pole-to-pole fault. In this case after opening sw2 and sw4 and closing sw1 and sw3 the current of positive and the negative poles will be equal. The differential equation of the circuit can be given as: p

d2 iL (t) dt 2

p

+

(RT + 2Rcb ) diL (t) 1 p · i (t) = 0 + 2L dt 2L(Ccb /2) L

(14)

where RT represents the sum of high frequency resistance of faulted sections of two transmission lines and the fault resistance. Note that 2R » RT and hence RT can be replaced by 2RT . Thereafter the differential equation can be rearranged as follows: d2 iL (t) (RT + Rcb ) · + L dt 2

p diL (t)

dt

+

1 p i (t) = 0, L L

(15)

which is identical to (4). Therefore, the line current after interruption of a pole-to-pole short circuit fault in a bipolar configuration is similar to that of a monopole system. During interruption of a

pole-to-pole fault because of simultaneous operation of the CRCBs in both poles of the system, the overall capacitance is divided by half and the overall resistance and also the inductance are doubled and the equations from Section 4.1 are valid. 4.3. Symmetric monopole system The interruption of pole-to-ground fault in the symmetric monopole system is similar to that of the asymmetric monopole system. Therefore, the analysis from Section 4.1 is valid for this type of fault in the symmetric monopole system. Moreover, the interruption of pole-to-pole and pole-to-pole-ground faults in symmetric monopole system are similar to interruption mentioned types of fault in the bipolar system. Thus, the analysis from Section 4.2 is valid for the mentioned types of fault in the symmetric monopole systems. 4.4. Power losses The MB unit conducts the nominal current of system in the normal condition. In order to satisfy the voltage requirements of grid the MB unit contains several semiconductor switches in series. depending on the current breaking capability The MB unit might have few parallel branches. IGBTs and IGCTs with antiparallel diodes are typically employed in the realization of DCCBs. Depending on the power flow direction in the DC transmission line, the current can flow through the switches or their antiparallel diodes. The conduction power losses for both IGBTs and IGCTs can be approximated by modeling them as the series connection of a constant DC voltage source (uT0 ), which represents the on-state collector–emitter voltage at zero-current and a resistor (rC ) representing the on-state resistance of semiconductor switch. Hence the collector–emitter voltage can be given by Eq. (16) [32]. uCE (t) = uT 0 + rc ic (t)

(16)

Total conduction power losses caused by the MB unit can be given by:



pcT,sw (t) = Np Ns

iMB (t)(t) uT 0 + rc Np



iMB (t) Np

2 

(17)

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where Np , Ns and iMB are the number of parallel branches, the number of semiconductor switches in series connection and the current in MB unit in normal condition. To clarify the impact of series and parallel connection of semiconductor switches, (17) can be rearranged as follows: pcT,sw (t) = Ns uT 0 iMB (t) + Ns rc iMB (t)2 −Ns







Np − 1 rc iMB (t)2 Np

(18)

Pcs,sw

Eq. (18) implies that the total conduction power losses reduce by increasing the number of parallel branches for a given number of switches in series. The power losses of inverter side CRCB can be derived by calculating the power losses in the antiparallel diodes of its MB unit. The power losses approximation for the antiparallel diodes is similar to that of IGBT [32] and can be given by: pcT ,D (t) = Ns uD0 iMB (t) +

Ns rD iMB (t)2 Np

(19)

5. Design remarks The design of CRCB can be done by considering the system parameters based on two main requirements including maximum current interruption capability and maximum TIV across the CRCB. 5.1. MB unit First of all the semiconductor switch type must be chosen. As mentioned, IGBTs ad IGCTs are most common components to be applied in the DCCBs implementation. However, other types of fast gate controlled devices would be potential candidates to be employed in the implementation of CRCB. The number of power switches in series connection in each branch of MB unit can be defined based on the maximum TIV requirement and the voltage capability of the power semiconductor switch. VCE,dc represents the collector–emitter DC stability voltage and typically is given for 100 FIT (Failures in Time). Typically, the collector–emitter DC stability voltage lies in the range of 0.5–0.6 of collector–emitter break-down voltage. Therefore, the number of IGBTs in series connection can be obtained based on the following equation:

Ns =

TIV max · Vdc VCE,dc

 (20)

where,  represents the ceiling function. x is equal to the smallest integer greater than or equal to x. The number of parallel branches should be defined based on required maximum current interruption capability of the CRCB. The number of parallel branches can be given as follows:

Np =

I br,max Icn

 (21)

5.2. Current limiting inductor The largest rate of rise of current occurs when a fault happens very close to the circuit breaker. In this case the fault can exceed the maximum current breaking capability of the CRCB very quickly even before it is detected by either the protection relay or the CRCB internal protection unit. Therefore, Lcb is included in the topology of the CRCB as the current limiting inductor in order to limit the rate of rise of fault current. The size of current limiting inductor can be defined by considering the maximum zero distance fault identification time (Tid0,max ) and the voltage level. Assume that a short circuit fault happens in a location with 0 km distance to the

223

CRCB. The maximum rate of rise if current in the MB unit of the CRCB can be given by: dif,max dt

=

V dc Lcb

(22)

Eq. (22) gives the maximum current derivative since in practice the DC bus voltage drops during the short circuit fault conditions. In case of MMC based system, due to the absence of large capacitor at the DC side of converter and the presence of relatively large arm inductors, the system inductance will be larger than Lcb . The current limiting inductor should be sized in order to limit the value of fault current below the maximum current breaking capability of CRCB for the faults with 0 km distance. Therefore, we have: Lcb =

Vdc Tid0,max ; m1 Ibr,max − In

0.6 < m1 < 1

(23)

where m1 is introduced as a design constant. If m1 is selected to be equal to one the current limiting inductor will limit the value of fault current to the maximum current breaking capability of the CRCB during the maximum zero distance fault detection time. 5.3. Discharging branch 5.3.1. Resistor Rcb Rcb should be designed in order to provide the system with discharging current with a peak larger than the maximum current breaking capability of CRCB. Therefore the acceptable range for Rcb can be given as: Rcb =

V Ccb0 ; m2 Ibr,max

1 < m2 < 1.1

(24)

where m2 is introduced as a design constant and VCcb0 is the capacitor Ccb voltage level after it is charged. The upper margin of m2 governs the resistance value. The larger m2 , the smaller value of resistance. On the other hand, smaller value of resistance will cause larger discharge current and overrating of related components. 5.3.2. Capacitor Ccb After calculating the resistor value, the minimum value of CRCB capacitor can be obtained. The capacitor should be sized in order to keep the fault interruption circuit in the over-damped regime in any condition. As can be found out from (5), for a given value of Ccb the damping factor increases by increasing the circuit resistance and also it increases by reducing the value of system inductance. The smallest  for a given value of Ccb happens when the circuit resistance has its lowest value and the inductance has its largest value. This case happens when a short circuit fault with 0  occurs at the far end of the line. Therefore, the acceptable range for the value of Ccb to have  > 1 in all fault scenarios can be obtained as follows:



 > 1 ⇒ Ccb >

4 Lcb + TLL · LLHF 2 Rcb



(25)

where TLL represents the transmission line length in km and LLHF represents the line high frequency inductance in mH/km. 6. Sensitivity analysis 6.1. Case study A CRCB is designed based on the analysis and remarks from Sections 4 and 5 and then the impacts of variation in different parameters on behavior of the CRCB investigated. The sensitivity analysis is carried out using the obtained equations in Section 4. Table 1 illustrates the case study system parameters and CRCB design requirements.

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Table 1 Conceptual design example parameters and requirements. Parameter

Description

Value

Vdc In TLL LL RL LLHF RLHF Tid0,max TIVmax Ibr,max

System nominal voltage System nominal current Transmission line length Transmission line inductance per kilometer Transmission line resistance per kilometer Transmission line high frequency inductance per kilometer Transmission line high frequency resistance per kilometer Maximum zero distance fault identification time Maximum TIV across the MB unit of CRCB Maximum current breaking capability of the CRCB

320 kV 1 kA 100 km 2.9 mH/km 10 m/km 0.11 mH/km 23 m/km 1 ms 1.15 pu 10 kA

Fig. 7. Design area considering the circuit damping factor.

LL , RL , LLHF and LLHF are obtained using PSCAD line constant program [30] for an XLPE insulated HVDC cable. The cross-section and parameters of HVDC cable are illustrated in Fig. 21 and Table 2, respectively [33]. The value of current limiting inductor is obtained using (23) and set to 50 mH. FZ750R65KE3 as one of the commercial IGBTs with highest available blocking voltage is selected. Based on the TIV and maximum current requirements from Table. 1, the number of IGBTs in series and parallel branches are calculated as 97 and 14, respectively from (20) and (21). Based on (24) and assuming VC0 = 320 kV, RL should be smaller than 32 . By selecting 30  as the value of RL the marginal value of Ccb can be calculated from (25). The minimum value of Ccb is obtained as 238.28 ␮F. Fig. 7 depicts the damping factor of equivalent circuit for different values of resistor and capacitor around obtained values. The red dashed line represents the criteria by (22). Point A illustrates the coordination of Rcb = 30  and the obtained marginal value for Ccb . In order to satisfy the TIV requirement of this design case the value of Ccb can be selected as 400 ␮F, which is shown by point B in Fig. 7. As can be seen in the figure the TIV is expected to lie in the range of 1.08–1.12 pu. 6.2. Impact of CRCB resistor and capacitor The impact of change in the internal resistor and capacitor of the CRCB is depicted in Fig. 8(a) and (b). Fig. 8(a) shows the TIV versus values of Ccb and Rcb . The fault distance from CRCB is set to 100 km and the CRCB interrupts its maximum rated current (10 kA).

In addition, the value of current limiting inductor is set to 50 mH. The capacitor value changes from 200 to 1200 ␮F and the resistor takes the value in the range of 25–32 . Minimum excessive voltage across the CRCB happens when it is equipped with the largest resistor and capacitor. The change in the resistance below its marginal value (can be calculated from (24)) does not change the TIV value, remarkably. However, small values of Rcb can increase the maximum line current up to 15%. The value of Ccb has the largest impact on the CRCB TIV, whereas it has a negligible impact on the maximum line current when Rcb is selected close to its marginal value. Figs. 9(a) and 10(b) show the voltage across CRCB and the line current when the value of Rcb is set to 30  and the capacitor value varies from 200 to 1000 ␮F. The capacitances below Ccb marginal value causes larger TIV across the CRCB. Increase in the value of Ccb decreases the TIV whereas increases the line current discharge time. The CRCB voltage and the line current for different values of Rcb with fixed 400 ␮F capacitor are depicted in Fig. 9(b) and 10(b), respectively. Increasing the resistor value up to the marginal value decreases the excessive voltage on the device while increases the line current discharge time. However, it is recommended to choose the resistor value smaller than the marginal value. The capacitor and resistor value must be optimized together according to the requirements. When the resistor value is larger than its marginal value the voltage waveform changes significantly and reaches higher levels. 6.3. Impact of fault resistance Fault impedance has strong impact on the voltage waveform. As the worst case a short circuit fault at the end of DC line is investigated when the values of Ccb and Rcb are set to 400 ␮F and 30 , respectively and the fault resistance varies from 0 to 12 . As it can be seen in Fig. 9(c), the CRCB voltage takes its largest values during the interruption of low impedance faults. In fact, the higher impedance faults increase the damping factor of the equivalent circuit. Therefore, interrupting high impedance faults does not cause overvoltage on the CRCB. Fig. 10(c) illustrates that the fault resistance does not have a remarkable impact on the line current. 6.4. Impact of fault location Fig. 9(d) and 10(d) show the impact of fault distance from the CRCB on the voltage and current waveforms. As it is expected the amount of stored energy in the line inductance during the faults far from the CRCB is higher as compared to the closer faults. However, it can be seen in Fig. 9(d) when a fault occurs close to the CRCB, its interruption causes slightly larger TIV across the CRCB as compared to the faults with longer distances to the CRCB. As was previously mentioned, the line resistance depends on the frequency. Although the line resistance is typically small and negligible it can increase during the fault current interruption due to the high frequency

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Fig. 8. (a) TIV and (b) maximum line current variation by changing Ccb and Rcb .

Fig. 9. Sensitivity analysis of CRCB voltage during current interruption.

components of fault current and skin effect [30]. Moreover, the line inductance decreases remarkably as compared to its pre-fault value. The inductance and resistance of employed cable in this study for f = 0.001 Hz is equal to 2.9 mH/km and 10 m/km, respectively whereas for f = 1000 Hz the values change to 0.11 mH/km

Fig. 10. Sensitivity analysis of transmission line current during CRCB operation.

and 23 m/km. Therefore, when the CRCB interrupts a fault with 100 km distance from itself the high frequency line resistance increase the damping factor of equivalent circuit and reduces the overvoltage across the CRCB. When the fault occurs very close to the CRCB, the system inductance is equal to value of current lim-

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Fig. 11. Test multi-terminal HVDC grid.

Fig. 12. (a) and (b) MMC 1 and 4 and their associated buses and lines.

iting inductor while the line resistance between the CRCB and the fault location is equal to zero. Hence, larger TIV can be observed when the fault occurs very close to the CRCB. In addition, Fig. 10(d) illustrates that decreasing the fault distance reduces the resistance between the CRCB and the fault location and slightly increases the maximum line current.

Fig. 9(f), interruption of currents with larger value than the CRCB rated current interruption capability increases its TIV.

6.5. Impact of capacitor initial voltage

A four-terminal meshed HVDC grid model, which was proposed in [34] is employed in this study. The system configuration is shown in Fig. 11. The studied model represents a cable-based meshed HVDC grid. The investigated system has a symmetric monopole HVDC configuration and includes four half-bridge MMCs. The MMCs are modeled by a continuous modeling approach with antiparallel diodes representing the blocking capability of the MMCs [34]. The simulation study is carried out in an electromagnetic transients type program namely PSCAD. MMC 1 and 2 operate in active and reactive power control mode while MMC 3 and 4 operate in reactive power and voltage droop control mode. In the normal condition, MMCs 1 and 2 inject almost 700 MW into the grid and MMCs 3 and 4 absorb 600 and 800 MW, respectively. The blocking current threshold of MMCs is set to 2.8 kA in order to observe the MMC behavior without blocking during sever fault conditions. The parameters of four-terminal grid are illustrated in Table 3. HVDC transmission lines are modeled based on the XLPE insulated cable using frequency dependent modeling

Fig. 9(e) and 10(e) depict the impact of CRCB capacitor charged voltage on the CRCB voltage and the line current waveforms. When the capacitor is charged up to the system voltage, the CRCB satisfies the design requirements. When the capacitor is under-charged down to 280 kV, the CRCB still satisfies the TIV requirement. However, decreasing the voltage of capacitor below 260 kV increases the overvoltage across the CRCB. In addition when the capacitor is over-charged, the TIV across the CRCB reduces. 6.6. Impact of magnitude of interrupted current The impact of fault current value at the interruption instance (t = tbr ) on CRCB performance is depicted in Figs. 9(f) and 10(f). Since the CRCB is designed to interrupt the maximum fault current (in this case Imax = 10 kA), the interruption of lower currents can be done with lower TIV and lower maximum line current. It can be seen in

7. Simulation 7.1. Test system

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Fig. 13. The CRCB and its capacitor voltages following a pole-to-pole fault on line L14 .

approach. The cable cross-sections and properties of material are illustrated in Fig. 21 and Table 2, respectively [33]. In addition, a state of art non-unit protection scheme, which has recently been proposed in [35] is employed for transmission line protection. The utilized method uses the local current measurements for line fault detection. The directions and locations of relevant currents and voltages are illustrated in Fig. 12(a) and (b). LB represents the DC bus filter reactor and its value is included in Table 3. 7.2. Results A low-impedance (Rf = 1 m) pole-to-pole short circuit fault happens at t = 0 s at the middle of transmission line L14 (fault distance from CRCBs at buses 1 and 4 is equal to 100 km). The protection system identifies the fault and send the trip command to CRCBs that locate at both ends of line L14 . After all corresponding CRCBs trip and the fault currents are interrupted, transmission line L14 is isolated from the rest of multi-terminal HVDC grid. However, the power flow in the other lines changes and the MMCs track their pre-fault reference values without power flow discontinuity. Fig. 13(a)–(d) depicts the CRCB and its capacitor voltage p p for CB14 , CBn14 , CB41 and CBn41 , respectively. vCcb14p and vCcb14n reach 352.21 and -353.83 kV whereas vCcb41p and vCcb41p reach 346.20 and −346.23 kV, respectively. It can be seen that the maximum voltage for rectifier side (MMC 1) CRCBs is larger as compared to the maximum TIV of inverter side (MMC 4) CRCBs. The post-interruption voltage of the power converter can affect the TIV of CRCBs. The positive and negative DC bus voltages for MMC 1 and 4 are depicted in Fig. 14(a)–(d). After short circuit fault occurs, the DC bus voltage p decreases (for instance in case of vdc,MMC1 it falls to 264.5 kV) until the CRCB interrupts the fault current. Thereafter, few overshoots can be observed in the voltage since the MMC tries to regulate the DC bus voltage. The maximum overshoot depends on the MMC con-

227

Fig. 14. DC bus voltage following a pole-to-pole fault on line L14 .

trol system behavior. It can be seen in Fig. 14(a) that the positive DC bus voltage of MMC 1 after fault current interruption reaches 363 kV whereas Fig. 14(c) shows that the positive DC bus voltage of MMC 4 reaches 345 kV. Hence, the CRCBs associated with MMC 1 experience larger overvoltage (almost 6 kV) compared to the CRCBs associated with MMC 1. Fig. 15(a)–(d) depicts the MB unit and transmission line curp p rent for CB14 , CBn14 , CB41 and CBn41 , respectively. As can be seen in the figure, the fault current is interrupted promptly in MB units of corresponding CRCBs (green trace). The current interruption time for this simulation study is around 50 ␮s. The blue traces show the transmission line current, which discharges naturally. It can be seen that the demagnetization time is below 50 ms for this case study. The currents at MMC 1 side reach higher levels due to the positive pre-fault current (The pre-fault and fault currents are in the same direction.). The MMCs DC side current are depicted in Fig. 16(a)–(d). In fact, the main purpose of DCCB application in HVDC grids is to protect the converter station from high fault current. In this fault scenario MMC 1 and MMC 4 are attached to the faulty line. It can be seen in Fig. 16(a) and (d), the MMC DC side current is interrupted by the CRCB before reaching undesired values. In addition, as previously mentioned due to the fast operation of CRCB the MMC DC side current is interrupted in almost 50 ␮s. It can be seen in Figs. 16(a) and 15(a) the current in line L14 reaches 5.1 kA whereas the DC side current of MMC 1 reaches 4.2 kA. The difference between mentioned currents is due to the current contribution from other adjacent transmission lines at bus B1 . Figs. 16(c) and 15(d) show that the current in line L14 at MMC 4 side reaches 4.23 kA while the MMC 4 current reaches 2 kA. The larger difference between the line and converter currents at MMC 4 side compared to MMC 1 side is due to the higher current contribution from adjacent transmission lines at bus B4 . Fig. 16(b) and (c) shows that the current at DC sides of MMC 2 and 3 are disturbed but do not reach large values.

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Fig. 15. The MB unit and line currents following a pole-to-pole fault on line L14 .

Fig. 17. The CRCB voltage for different fault locations, resistance and capacitance values and capacitor charged voltage.

7.3. Sensitivity analysis verification In order to verify the findings from sensitivity analysis in Section 6, the most relevant cases are simulated using the four-terminal HVDC grid detailed model. Figs. 17(a) and 18 (a) depicts the CRCB voltage and the line current when the fault location changes. Initially, the closest fault to the CRCB causes larger TIV as compared to the fault with 200 km distance to the CRCB. Note that at t = 16 ms due to the increase in frequency dependent cable inductance and reduction in its resistance the CRCB voltage show different behavior. However, still the largest TIV happens at initial stage of voltage rise when the fault has 0 km distance to the CRCB, which was considered in design process. In addition, as was mentioned in Section 6, the line current reaches its larger value when the fault happens at 0 km distance from the CRCB. Figs. 17(b) and 18(b) depicts the impact of change in the CRCB capacitor on its voltage and the line current, which confirm the results from Section 6. Figs. 17(c) and 18(c) confirm that changing the value of Rcb below its marginal value does not have remarkable impact on the voltage across CRCB. However, lower values of resistance cause larger discharge current in the transmission line. Fig. 17(d) and 18(d) also confirm the findings in Section 6 about the impact of CRCB capacitor initial voltage on TIV and line current. 8. Experimental proof of concept

Fig. 16. The MMC DC side current following a pole-to-pole fault on line L14 .

A low voltage prototype has been built up to examine the practical functionality of the proposed CRCB. The employed components for implementation of the CRCB are illustrated in Table 4. Fig. 19(a) shows the experimental setup configuration. As can be seen in Fig. 19(a) the CRCB is connected to a DC link, which is fed by an autotransformer through a diode rectifier. The transmission line and the current limiting inductor is represented by an inductor and its

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experiment, the short circuit is detected by an overcurrent detector program, which is developed on a 16-bit digital signal controller. The threshold of overcurrent detector is set to 17.5 A. Note that the no-load DC link voltage is 135 V whereas it drops to 108 V when the resistive load is connected. The pre-fault current of system is almost 4 A. The gate signal of MB unit IGBT is changed to 15 V 2 ␮s after the thyristor gate pulse is generated. The thyristor gate pulse width is set to 1 ms. The experimental results have been observed and recorded using a DSOX2024A Agilent oscilloscope. The DC source and CRCB voltage waveforms are shown in Fig. 18(a). As can be seen in Fig. 18(c), the voltage increases sharply up to 108 V and thereafter rises up to the DC link no-load voltage value (135 V), smoothly. As can be seen in the area, which is marked by red arrow and A letter the DC source voltage increases to its no-load value after the fault current is interrupted. Therefore, the slight difference between the DC source voltage and the CRCB voltage right after fault interruption can be considered as the TIV across the CRCB, which is around 5 V (4.6% of VDC). Fig. 20(b) shows the line (iline ) and DC source (is ) current waveforms in blue and red colors, respectively. As can be seen in the figure, after fault inception the line current rises rapidly and when it reaches 17.5 A, the CRCB trips. The line current is diminished in less than 28 ms. Fig. 20(c) shows the capacitor voltage waveform together with the CRCB voltage. As can be seen in the figure, the capacitor voltage before discharging is equal to 98 V and decreases after interruption instance. Fig. 20(d) shows the magnified current waveforms. It can be seen in Fig. 20(d), the source current reaches zero in less than 10 s, which can be considered as the interruption time of the implemented CRCB for the aforementioned conditions. Fig. 18. The line current for different fault locations, resistance and capacitance values and capacitor charged voltage.

equivalent series resistance. A short circuit fault is placed using an AC mechanical circuit breaker. Fig. 19(b) shows the internal block diagram of implemented CRCB. The line current is measured using a hall effect-based linear current sensor. In order to carry out the

9. Conclusion Interrupting DC current is more challenging as compared to the AC one. In addition to the lack of natural zero crossing in DC current, the high transient interruption voltage (TIV) across the DC circuit

Fig. 19. (a) Experimental setup configuration. (b) Implemented CRCB block diagram.

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Fig. 20. Experimental results (a) CRCB [green] and DC link [orange] voltages, (b) Line [blue] and DC source [red] currents, (c) CRCB [green] and capacitor voltage [orange] waveforms, (d) Magnified line [blue] and DC source [red] currents. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of the article.)

breaker (DCCB) and handling the stored energy in the DC transmission line can be listed as the main issues. A different approach for DC fault current interruption and saving the power converter from destructive fault currents namely current releasing DC circuit breaker (CRCB) is investigated through the analysis, simulation and experiments in this paper. The CRCB is a solid-state type DC circuit breaker (SSCB). The results from this study show that by selecting suitable values for the internal parameters of CRCB the DC fault currents can be interrupted without generating surge voltage. In addition, by selecting the CRCB capacitor larger than the marginal value and also the CRCB resistor smaller than its marginal value the TIV across the CRCB can be effectively limited. Sensitivity analysis implies that the interruption of high impedance pole-to-ground or poleto-pole faults can be done even without excessive voltage. The highest TIV appears across the CRCB when the fault occurs very close to the CRCB and it has a very low resistance. The CRCB can be integrated into the different HVDC system configurations including the monopole and the bipolar configurations. Although this paper focuses on high voltage application of CRCB, it can be utilized in medium and low level DC systems. The CRCB has at least 60% less power losses as compared to the typical SSCBs due to the less number of semiconductor switches. The functionality of CRCB is examined and validated

through implementing a lab-scale prototype. The short circuit test of the prototype confirms the surge-less operation of the CRCB. Nevertheless, the high voltage implementation of CRCB might be challenging. However, the application of CRCB in point-to-point HVDC links due to the presence of inductance between the converter and the CRCB and also lack of alternative current paths is limited. In this case, when the CRCB operates (interrupts the current), the presence of inductance between the converter and CRCB can cause a transient overvoltage. This inductance does not cause overvoltage in a dc bus with adjacent transmission lines (e.g. in meshed HVDC grids) since its current will not change rapidly and can flow through the other adjacent lines. Future work will have a technical assessment on results of ongoing medium voltage scale prototyping of CRCB and will investigate its failure modes and drawbacks. In addition, a cost-benefit analysis is needed in order to confirm the economic feasibility of application of the proposed CRCB in future meshed HVDC grids. Acknowledgements The research leading to these results has received funding from the People Programme (Marie Curie Actions) of the European Unions Seventh Framework Programme (FP7/2007–2013) under REA grant agreement n◦ 317221.

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Appendix

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References

Fig. 21. Cross-section of 320 kV XLPE insulated HVDC cable.

Table 2 DC cable data [33]. Layer

Radius (mm)

Resistivity (m)

Rel. permeability

Rel. permittivity

(1) Core (2) Insulator (3) Sheath (4) Insulator (5) Armor (6) Insulator

25.2 40.2 43.0 48.0 53.0 57.0

1.72×10−8 – 2.20×10−7 – 1.80×10−7 –

1 1 1 1 10 1

1 2.3 1 2.3 1 2.1

Table 3 Four-terminal HVDC system parameters [34]. Parameter

Converter 1, 2, 3

Converter 4

Rated power AC grid voltage Converter AC voltage Transformer, uk Arm capacitance Carm Arm reactor Larm Arm, resistance Rarm DC Bus capacitor Ls Bus filter reactor Ls

900 MVA 400 kV 380 kV 0.15 pu 29.3 (␮)F 84.8 mH 0.885 () 10 (␮)F 10 mH

1200 MVA 400 kV 380 kV 0.15 pu 39 (␮)F 63.6 mH 0.67 () 10 (␮)F 10 mH

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Table 4 Employed components for prototyping. Component

Part number

Type

Description

TF , Tch MB, Qch , QF Rch Rcb Ccb Rload R L Cdc IGBT driver Voltage sensor Current sensor Controller

BT152-400R HGTG20N60B3 6.3  4.7  1000 ␮F 27  600 m 6.2 mH 6600 ␮F HCPL316J ACPL-C87 ACS712 dspic30F4011

Thyristor N-Channel IGBT Resistor Resistor Capacitor Resistor Resistor Inductor Capacitor IC IC IC IC

Thyristor 600 V, 40 A 5W 5W 200 V 150 W Equivalent series resistance of the line inductor – 300 V 2.5 A˚ gate drive optocoupler Precision optically isolated voltage sensor Hall effect-based linear current sensor IC 16-bit,120 MHz digital signal controller

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