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Development of a novel stack package to fabricate high density memory modules for high-end application
Microelectronics Reliability 50 (2010) 1116–1120
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Development of a novel stack package to fabricate high density memory modules for high-end application Chinguo Kuo a, Jen-Jun Chen a,b,* a b
National Taiwan Normal University, 162, He-ping East Road, Section 1, Taipei 10610, Taiwan, ROC Nanya Technology Corporation, 336, Section 1, Nankan Rd., Luchu, Taoyuan, Taiwan, ROC
a r t i c l e
i n f o
Article history: Received 1 December 2009 Received in revised form 27 January 2010 Available online 23 June 2010
a b s t r a c t A new thinking has been spreading rapidly throughout the microelectronics community in the development and application of 3D stack package. Based on the concept, the application of the 3D stack package to high density memory modules makes DRAM provides major opportunities in both miniaturization and integration for advanced and portable electronic products. In order to meet the increasing demands for smaller, higher functionality-integrated and low cost package, this paper presents a packaging method for multi-chip IC without the problem of warpage and pin leakages. Multiple chips are packaged into a single package by stacking up the chips vertically, in which the packaging method is based on the standard wire bond technology with the use of longer bonding wire, appropriate epoxy for delamination and special care in wafer thinning. The presented method promotes the yield of the packaged IC and also successfully reduces the package size. However, special circuit techniques are required to maintain the normal operation of the packaged IC, as well as to maintain the compatible operating speed and power consumption. The reliability of the IC packaged with the presented method has been examined and it verifies the high performance of the presented method. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction For large capacity DRAM, high data-rate (over 5300 MB/s) and low cost are two fundamental demands from the market. In the past years, a number of approaches have been proposed for achieving high data-rate [1,2], and low cost [3]. With the electronics market aggressively pushing towards memory and hand-held devices, the electronic packaging industry has been forced to come up with smaller and innovative solution to keep up with this demand. The trend towards miniaturization and increased functionality has pushed for packaging more than one die together, while maintaining chip scale [4]. Trend is to move from 2D configuration to 3D stacking and then to 3D ICs for: 1. Reduced footprint and increase Si efficiency (ratio of total Si footprint area to substrate area) 2. Increased electrical performances: shorter interconnects length (device speed) and better electrical insulation (to reduce electrical parasitances in RF applications) 3. Heterogeneous integration: integration of different functions (memory + logic + sensor + RF + imagers + different substrate materials ) * Corresponding author at: Nanya Technology Corporation, 336, Section 1, Nankan Rd., Luchu, Taoyuan, Taiwan, ROC. Tel.: +886 3 3528225. E-mail address: [email protected] (J.-J. Chen). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.04.025
Semiconductor chips face constant pressure for increased performances while still decreasing their size. At the same time, their packages must be able to accommodate new functionalities. The ever-expanding consumer electronics market is a particularly strong driver of packaging innovations such as 3D ICs [5]. 3D integration will use technologies originally developed for MEMS technology but for different markets. In our report, we have analyzed that portable applications are a strong market driver for 3D integration [6]. In the popular 3D stacked package form of 3D integration, the mostly digital subsystem components form a stack of multiple die. In such a construction, it is possible to fabricate transistors atop other transistors, resulting in multiple layers of active components. These transistors can then be wired to other transistors on the same device layer, to transistors on different device layers, or both, depending on the process technology. The several approaches to fabricate 3D package or 3D-compatible transistors vary in terms of the maximum number of device layers and the maximum density of interconnects between these layers. One leading approach what we use is wire bonding process, which glues discrete dies together using gold wires and substrate interconnect interface. This architecture uses a wire bond die that is electrically coupled to the substrate using wire bonding interconnect technology. Wire bonding interconnect technology is a very mature process and has flexibility in the change of die size can be accommodated without noticeable additional costs. This low cost, high yield and good
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reliability process let us implement 3D package for dies stack, overcoming the limitations of other proposed technologies. 2. Structure analysis Structural analysis of 1 Gb DDR2 stacked die was initiated on the structural design as presented in Fig. 1, in order to determine compatibility and parts related stresses, as well as the failure mechanism on the package, while it is being processed in assembly. The key dimensions of the various parts in the package are shown in Table 1 and are simulated in order to put them together in a package with 1.4 mm total height. 2.1. Concerns There are four important items that need to be considered on this development – namely: delamination, wire loop height, package warpage and wafer thinning technology.
(a)
C Mold Cap Thickness
Die 2 Die 1 A1
BLT1 SUB
(b) Top
Bottom wire
wire
BLT 2
BLT 1
D2 D1
Substra te
Fig. 1. (a) Schematic diagram of stack construction by 1 Gb DDR2 stacked die and (b) physical structure by cross-sectional view.
Table 1 Parts name of stacked die package.
Delamination is one of the major challenges on the package development. We conducted materials properties to properly select compatible materials. Additional, adhesion test between B-stage epoxy and die, selection of the epoxy adhesive between die to die, epoxy mold compound (EMC) were also conducted to select significant compatible materials as shown in Table 2. For the solution to delamination issue, the property target for the epoxy is higher Tg, higher modulus, lower CTE, good adhesion to die and good adhesion on EMC. Another leakage failure that was determined through the structural analysis was wire loop height. Loop height is caused by wire bonding control on the bottom die to the lead finger on the substrate. There is a different bonding method from conventional one proposed in the process. The reverse bonding was taken advantage of ensuring the constant loop height to prevent the short from wire and die as illustrated in Fig. 2. Package warpage was also determined as a challenge that may cause package failure. Package warpage was also initiated by different CTE during assembly processes to determined material warpage performance. Another problem we managed to get during the structural analysis was the wafer thinning technology. We selected three different processes to qualify in the wafer thinning process technology – namely: grinding, grinding + wet polishing and grinding + plasma polishing. By comparing the several methods, it was found the full grinding and wet polishing can obtain the good results on wafer thinning. Typically, stacking dies vertically in a single low-profile package present a lot of challenges to the final product; one of them is the wafer thinning process. We need to back grind the dies to less than or equal to 120 lm thickness to be able to put them together in one single package. This sensitive process, if not properly optimized, provides us a drastically low assembly yield. Yield loss is contributed by tow factors, first is wafer warpage, and second is weak strength of the wafer. Wafer warpage is prone to total wafer breakage and a weak wafer is prone to die chipping and micro crack. To overcome these difficulties we conducted an evaluation study on the wafer thinning process. Based on warpage performance the identified best process is grinding + wet polishing. 2.2. Thermal and electric simulation
Symbol
Description
Dimension (mm)
D2 BLT2 D1 BLT1 C SUB A1
Mold cap thickness Die thickness top (direct) Die to die attach – epoxy spacer Die thickness bottom (window) Die to substrate attach – paste Mold to die top surface clearance Substrate thickness Ball height (after reflow for 0.45 mm dia) Package max height
0.700 0.120 0.150 0.120 0.025 0.285 0.260 0.350 1.39
2.2.1. Thermal simulation In the semiconductor electronics industry, effective heat removal from the integrated circuits (IC) chip, through the electronic package to the environment is crucial to maintain an allowable junction temperature of the IC chip. Thermal performances of such electronic packages are characterized by package thermal resistance called hJA and are widely used in the electronic industry. Improving thermal performance is numerically predicted using computational fluid dynamics (CFD) technique. The electrical
Table 2 Comparison of material property. Property
Ionic impurity: chloride (CI ) Tg (DMA) Viscosity @25 °C Tensile modulus CTE Filler type/filler loading/filler size Moisture absorption Weight loss on cure
Units
@ 25C below Tg above Tg (85%/85 °C) @300C
ppm °C cps MPa ppm/C /%/lM % %
Type A
Type B
Type C
Type D
Epoxy paste
Epoxy paste
Epoxy paste
Epoxy paste
2
<20 31 9000 @5 rpm 300 93 174 Teflon/42/Max20, Mean 3 0.35 1.5
4
1.21
30 10,000
10,200
80 150
31 95
0.35
0.32
8 14.000 @5 rpm 11 149 216 Coated polymer/30 0.9 7.65
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DDR2 Stacked Die
(a)
Wire Bond
(b) Enclosure Frame
PCB
DDR2 Stacked Die
Fig. 2. SEM image focused at wire bond on the stacked die (a) wire bond loop from lead finger to bond pad, (b) wire bond on top die and bottom die and (c) reverse bond (second bond) at bond pad.
measurement method, as outlined in the JEDEC document JESD5 1–1 was used for making the thermal measurements of the package. Fig. 3 shows the computational model of 1 Gb 90 nm DDR2 stacked die package was mounted on a two-layer board. The whole assembly was placed horizontally in a plexiglas, still air enclosure with a volume of one cubical foot, as recommended by the JEDEC standard. The numerical thermal model was built using Flotherm, a CFD based numerical tool that is being widely used for thermal analysis of electronic components and systems. This tool uses a finite volume approach to solve for the mass, momentum and energy conservation equations to converge on the solution based on the ambient conditions. The conjugate heat and flow solution is performed using the Boussinesq approximation for buoyancy forces. It is capable of solving both steady-state as well as transient governing equations, while turbulence is modeled with a choice of zero or two equation models. The dissipated power initiates a thermal plume rising from the package of 1 Gb DDR2 stacked die. The maximum airflow vector was found to measure 0.12 m/s in natural convection. The weak flow is generated by the buoyancy effect. The thermal contours in the X–Z plane are shown in Fig. 4 for natural convection. Device
Fig. 3. (a) A three dimensional mathematical model of the package in an isometric view, (b) a perspective of a far field treatment at full domain.
junction temperatures as well as the thermal resistance of packages can be predicted with a good accuracy for different ranges of power levels in natural convection. The numerically estimated die junction temperatures have also been found to be accurate and reliable: the differences against measured data are less than 15 percent. 2.2.2. RLC extraction For electric performance, parametric studies are also performed to investigate the effects of bond wires with different diameter and horizontal distance, and variations in signal traces. Electrical simulation was executed to characterize a 71-ball stack package. The cross-sectional views of the package are shown in Fig. 1. Electrical performances were compared in terms of insertion loss, return loss, cross talk noise and propagation delay. To look at the performance heterogeneity as a result of manufacturing process, parametric studies are also performed to investigate the effects of bond wires with 25.4 lm diameter and horizontal distances, and variations in signal traces. These results provide useful insights on design and process selection for high-performance semiconductor packages. Both Optimal PakSi-E 5.0 and Ansoft Q3D were used to extract the RLCs of the longest and shortest nets as well as the target nets
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plane by two perfect conductors which represent local chip ground. Table 5 presents the RLC simulation results. By the simulation, the RLC measurement at stacked die package can pass the Intel qualification of electric performance.
3. Assembly technology and system test
PCB
DDR2 90nm Stacked Die
After the final BOM was set, we started to design the assembly process flow. The assembly process was designed with consideration of manufacturability and product structural design. It would include electrical continuity (Open/Short) test after die-attached process. More importantly, this electrical continuity screening, allows the tracking of the first pass die attach yield level and sortout the imperfect attachment to prevent wastage of wire bond Known Good Die (KGD). Assembly yield shows good results, and also indicate in the reliability MSL3, TC500, HTS and HAST as illustrated in Table 3. For a 5.3 GB/s high data-rate DRAM module of 1 Gb DDR2 stacked die package, it is high data transfer rate and large memory
Fig. 4. Temperature profile under natural convection and power level of 1 W. Table 3 Assembly results.
in the package of 1 Gb DDR2 stacked die as illustrated in Fig. 5. Simplified 4-point profile recommended by [7] is adopted for bond wire simulation. The package is simulated with a copper ground reference plane 0.152 mm away from the bottom of the solder ball [8]. All VSS and VDD class nets are assigned as GND and Powers nets, respectively for comprehensive signal return path. Between the package and the reference ground plane is BT epoxy. Also, to investigate the high frequency characteristics of the stack package, the target signal nets are simulated in the frequency range of 667 Hz and 800 GHz. The signal nets are set up as a four-port system. All the four-ports are lumped gap ports with an impedance value of 50 Ohm. At the ball side, the ports extend from the bottom of the solder ball directly to the PCB ground reference plane. At the wire/bump side, the ports are shorted to the PCB ground reference
Lot
A
B
C
Sample size Assembly yield (%) Reliability test (MSL 3) (%) HAST (144 h) 130 °C/85 °C/RH/Bias1.98 V (%) HTS (500 h) (%) TC 500 cycle 55 °C/125 °C (%)
231 99.9 100 100 100 100
231 99.8 100 100 100 100
231 99.9 99 100 100 100
Table 4 Characteristics of 1 Gb DDR2 stacked die DRAM. Process technology Chip size Internal clock frequency Organization Data-rate CAS access time RAS access time Supply voltage (Periphery) (Array) Refresh cycle/period Active current (Icc1) Package
90 nm 3Metal CMOS 8.01 16.13 (mm) 333 MHz 256 Mb 4 8 banks 5.3 GB/s 11 ns (3 Clock cycles + 2 ns) 37 ns 1.8 V 1.5 V 16 K/64 ms 70 mA (Tc = 30 ns) 71-ball stack package
Table 5 RLC results of selected nets for bottom die (D1) and top die (D2) at 800 MHz.
Fig. 5. 1 Gb 90 nm DDR2 stack package in Ansoft Q3D (a) 3D model and (b) side view.
Net
R (m Ohm)
Ls (nH)
Cs (pF)
ADD_0-D1 ADD_0-D2 ADD_10-D1 ADDJIC-D2 VIO_0-D1 VIO_0-D2 VI0_7-D1 VIO_7-D2 LDQS-D1 LDQS-D2 LDM_RDQS-D1 LDM_RDQS-D2 BCS0-D1 BCS1-D2 ODT0D1 0DT1-D2 CKE0-D1 CKE1-D2
898.70 944.40 89S.40 943.S0 893.10 93a.flO 83 fl.9O 934.30 90O.S0 945.40 87O0 923.90 1065.00 1091.00 1049.00 1113.00 1079.00 1113.00
8.43 9.34 8.36 9.06 8.66 9.10 9.42 9.81 8.93 9.36 9.22 9.55 8.25 9.32 8.00 9.42 8.71 9.73
1.95 1.95 1.84 1.84 1.92 1.92 1.94 1.94 1.77 1.77 1.65 1.65 1.99 2.03 2.09 1.93 2.17 2.22
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and the result shows the excellent eye width 2.5 ns as shown in Fig. 6a. For the spec of DQ at the same bounds, the range is located in tIS = 100 ps to tIH = 175 ps. The result shows the excellent eye width 1.1 ns as shown in Fig. 6b.
(a)
VIH=1.15V VIL=0.65V 2.58ns
2.58n
2.53n
2.60n
(b)
VIH=1.15
1.14ns
1.06ns
1.09ns
VIL=0.65
4. Conclusion A 5.3 GB/s high data-rate and high capacity 4 Gb RDIMM have been developed by stack package based on the 1 Gb 90 nm DDR2 die. Its high data transfer rate and large memory capacity are particularly well suited to the advanced memory system. For the application of the package technology by stacked die, there are some challenges were made as shown below. 1. Silicon integration: our new qualified package, stacked die by wire bond technology, is the best solution for high density and capacity modules from the two mainstream device process-application is for small, lightweight and cost effective consumer products. 2. Material selection: the best available spacer and epoxy mold compound materials have been identified which has a good compatibility for the staked die package through simulation. This is also qualified by reliability tests, including TC, HTS and HAST. 3. Wafer thinning process is one of the most difficult among the challenges in developing the stacked die package. For the manufacturability and yield control, the process has been optimized successfully.
Acknowledgments Fig. 6. Operating waveform (a) command pin at/CS and (b) I/O pin at DQ51.
capacity are targeted to the advanced unique memory system for serving high-end workstations, servers and laptops. The characteristics of the DDR2 DRAM are listed in Table 4. To reduce the power consumption, supply voltage for the cells has been set at 1.5 V while a 1.8-V is applied to other circuits. Also, a 0.27(V) Vbb is applied to the memory cell substrate in the sleep mode to extend the refresh period. To prevent the performance from deteriorating at 1.5 V, several techniques such as charge transferred well sensing and negative voltage word line are adopted. Fig. 6 shows the operating waveform of the stacked chip in the 4 GB RDIMM. The command pin of/CS access time at 1.8 V is 12 ns, and the latency is four external clock cycles. Since 64b are read in parallel every 3 ns, a high data-rate of 5.3 GB/s is successfully achieved. The spec is in the range of tIS = 200 ps to tIH = 275 ps at the upper bound VIH = 1.15 V to lower bound VLH = 0.65 V,
The author wishes to appreciate teammate YM Chen and Eric Chang for data preparations. Thanks system lab. colleagues, Allen, Chin-Fan and Bou-Chi for the inquiry of related information. Also, thanks Sam Lee’s and Leo Lee, Kevin Ho and Matt Yang for the encouragement on the technical data. Especially, thanks Cristina friendly support on the table fabrication. References [1] [2] [3] [4] [5] [6] [7] [8]
Horiguchi M et al. In: ISSCC technical digest; 1995. p. 252. Yoo J et al. In: ISSCC technical digest; 1996. p. 378. Sugibayashi T et al. In: ISSCC technical digest; 1995. p. 254. Pan SJ et al. In: IEEE/CPM/SEMI International Electronics Manufacturing Technology Symposium; 2003. p. 125. Spiesshoefer S et al. J Vac Sci Technol 2005;A23(4):824. John Reche. In: IEEE/CPMT meeting; 2000. p. 1. EIA/JEDEC. EIA/JESD59 bond wire modeling standard; June 1997. EIA/JEDEC. EIA/JEP126 guideline for developing and documenting package electrical models derived from computational analysis; May 1996.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Development of a novel stack package to fabricate high density memory modules for high-end application Chinguo Kuo a, Jen-Jun Chen a,b,* a b
National Taiwan Normal University, 162, He-ping East Road, Section 1, Taipei 10610, Taiwan, ROC Nanya Technology Corporation, 336, Section 1, Nankan Rd., Luchu, Taoyuan, Taiwan, ROC
a r t i c l e
i n f o
Article history: Received 1 December 2009 Received in revised form 27 January 2010 Available online 23 June 2010
a b s t r a c t A new thinking has been spreading rapidly throughout the microelectronics community in the development and application of 3D stack package. Based on the concept, the application of the 3D stack package to high density memory modules makes DRAM provides major opportunities in both miniaturization and integration for advanced and portable electronic products. In order to meet the increasing demands for smaller, higher functionality-integrated and low cost package, this paper presents a packaging method for multi-chip IC without the problem of warpage and pin leakages. Multiple chips are packaged into a single package by stacking up the chips vertically, in which the packaging method is based on the standard wire bond technology with the use of longer bonding wire, appropriate epoxy for delamination and special care in wafer thinning. The presented method promotes the yield of the packaged IC and also successfully reduces the package size. However, special circuit techniques are required to maintain the normal operation of the packaged IC, as well as to maintain the compatible operating speed and power consumption. The reliability of the IC packaged with the presented method has been examined and it verifies the high performance of the presented method. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction For large capacity DRAM, high data-rate (over 5300 MB/s) and low cost are two fundamental demands from the market. In the past years, a number of approaches have been proposed for achieving high data-rate [1,2], and low cost [3]. With the electronics market aggressively pushing towards memory and hand-held devices, the electronic packaging industry has been forced to come up with smaller and innovative solution to keep up with this demand. The trend towards miniaturization and increased functionality has pushed for packaging more than one die together, while maintaining chip scale [4]. Trend is to move from 2D configuration to 3D stacking and then to 3D ICs for: 1. Reduced footprint and increase Si efficiency (ratio of total Si footprint area to substrate area) 2. Increased electrical performances: shorter interconnects length (device speed) and better electrical insulation (to reduce electrical parasitances in RF applications) 3. Heterogeneous integration: integration of different functions (memory + logic + sensor + RF + imagers + different substrate materials ) * Corresponding author at: Nanya Technology Corporation, 336, Section 1, Nankan Rd., Luchu, Taoyuan, Taiwan, ROC. Tel.: +886 3 3528225. E-mail address: [email protected] (J.-J. Chen). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.04.025
Semiconductor chips face constant pressure for increased performances while still decreasing their size. At the same time, their packages must be able to accommodate new functionalities. The ever-expanding consumer electronics market is a particularly strong driver of packaging innovations such as 3D ICs [5]. 3D integration will use technologies originally developed for MEMS technology but for different markets. In our report, we have analyzed that portable applications are a strong market driver for 3D integration [6]. In the popular 3D stacked package form of 3D integration, the mostly digital subsystem components form a stack of multiple die. In such a construction, it is possible to fabricate transistors atop other transistors, resulting in multiple layers of active components. These transistors can then be wired to other transistors on the same device layer, to transistors on different device layers, or both, depending on the process technology. The several approaches to fabricate 3D package or 3D-compatible transistors vary in terms of the maximum number of device layers and the maximum density of interconnects between these layers. One leading approach what we use is wire bonding process, which glues discrete dies together using gold wires and substrate interconnect interface. This architecture uses a wire bond die that is electrically coupled to the substrate using wire bonding interconnect technology. Wire bonding interconnect technology is a very mature process and has flexibility in the change of die size can be accommodated without noticeable additional costs. This low cost, high yield and good
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reliability process let us implement 3D package for dies stack, overcoming the limitations of other proposed technologies. 2. Structure analysis Structural analysis of 1 Gb DDR2 stacked die was initiated on the structural design as presented in Fig. 1, in order to determine compatibility and parts related stresses, as well as the failure mechanism on the package, while it is being processed in assembly. The key dimensions of the various parts in the package are shown in Table 1 and are simulated in order to put them together in a package with 1.4 mm total height. 2.1. Concerns There are four important items that need to be considered on this development – namely: delamination, wire loop height, package warpage and wafer thinning technology.
(a)
C Mold Cap Thickness
Die 2 Die 1 A1
BLT1 SUB
(b) Top
Bottom wire
wire
BLT 2
BLT 1
D2 D1
Substra te
Fig. 1. (a) Schematic diagram of stack construction by 1 Gb DDR2 stacked die and (b) physical structure by cross-sectional view.
Table 1 Parts name of stacked die package.
Delamination is one of the major challenges on the package development. We conducted materials properties to properly select compatible materials. Additional, adhesion test between B-stage epoxy and die, selection of the epoxy adhesive between die to die, epoxy mold compound (EMC) were also conducted to select significant compatible materials as shown in Table 2. For the solution to delamination issue, the property target for the epoxy is higher Tg, higher modulus, lower CTE, good adhesion to die and good adhesion on EMC. Another leakage failure that was determined through the structural analysis was wire loop height. Loop height is caused by wire bonding control on the bottom die to the lead finger on the substrate. There is a different bonding method from conventional one proposed in the process. The reverse bonding was taken advantage of ensuring the constant loop height to prevent the short from wire and die as illustrated in Fig. 2. Package warpage was also determined as a challenge that may cause package failure. Package warpage was also initiated by different CTE during assembly processes to determined material warpage performance. Another problem we managed to get during the structural analysis was the wafer thinning technology. We selected three different processes to qualify in the wafer thinning process technology – namely: grinding, grinding + wet polishing and grinding + plasma polishing. By comparing the several methods, it was found the full grinding and wet polishing can obtain the good results on wafer thinning. Typically, stacking dies vertically in a single low-profile package present a lot of challenges to the final product; one of them is the wafer thinning process. We need to back grind the dies to less than or equal to 120 lm thickness to be able to put them together in one single package. This sensitive process, if not properly optimized, provides us a drastically low assembly yield. Yield loss is contributed by tow factors, first is wafer warpage, and second is weak strength of the wafer. Wafer warpage is prone to total wafer breakage and a weak wafer is prone to die chipping and micro crack. To overcome these difficulties we conducted an evaluation study on the wafer thinning process. Based on warpage performance the identified best process is grinding + wet polishing. 2.2. Thermal and electric simulation
Symbol
Description
Dimension (mm)
D2 BLT2 D1 BLT1 C SUB A1
Mold cap thickness Die thickness top (direct) Die to die attach – epoxy spacer Die thickness bottom (window) Die to substrate attach – paste Mold to die top surface clearance Substrate thickness Ball height (after reflow for 0.45 mm dia) Package max height
0.700 0.120 0.150 0.120 0.025 0.285 0.260 0.350 1.39
2.2.1. Thermal simulation In the semiconductor electronics industry, effective heat removal from the integrated circuits (IC) chip, through the electronic package to the environment is crucial to maintain an allowable junction temperature of the IC chip. Thermal performances of such electronic packages are characterized by package thermal resistance called hJA and are widely used in the electronic industry. Improving thermal performance is numerically predicted using computational fluid dynamics (CFD) technique. The electrical
Table 2 Comparison of material property. Property
Ionic impurity: chloride (CI ) Tg (DMA) Viscosity @25 °C Tensile modulus CTE Filler type/filler loading/filler size Moisture absorption Weight loss on cure
Units
@ 25C below Tg above Tg (85%/85 °C) @300C
ppm °C cps MPa ppm/C /%/lM % %
Type A
Type B
Type C
Type D
Epoxy paste
Epoxy paste
Epoxy paste
Epoxy paste
2
<20 31 9000 @5 rpm 300 93 174 Teflon/42/Max20, Mean 3 0.35 1.5
4
1.21
30 10,000
10,200
80 150
31 95
0.35
0.32
8 14.000 @5 rpm 11 149 216 Coated polymer/30 0.9 7.65
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DDR2 Stacked Die
(a)
Wire Bond
(b) Enclosure Frame
PCB
DDR2 Stacked Die
Fig. 2. SEM image focused at wire bond on the stacked die (a) wire bond loop from lead finger to bond pad, (b) wire bond on top die and bottom die and (c) reverse bond (second bond) at bond pad.
measurement method, as outlined in the JEDEC document JESD5 1–1 was used for making the thermal measurements of the package. Fig. 3 shows the computational model of 1 Gb 90 nm DDR2 stacked die package was mounted on a two-layer board. The whole assembly was placed horizontally in a plexiglas, still air enclosure with a volume of one cubical foot, as recommended by the JEDEC standard. The numerical thermal model was built using Flotherm, a CFD based numerical tool that is being widely used for thermal analysis of electronic components and systems. This tool uses a finite volume approach to solve for the mass, momentum and energy conservation equations to converge on the solution based on the ambient conditions. The conjugate heat and flow solution is performed using the Boussinesq approximation for buoyancy forces. It is capable of solving both steady-state as well as transient governing equations, while turbulence is modeled with a choice of zero or two equation models. The dissipated power initiates a thermal plume rising from the package of 1 Gb DDR2 stacked die. The maximum airflow vector was found to measure 0.12 m/s in natural convection. The weak flow is generated by the buoyancy effect. The thermal contours in the X–Z plane are shown in Fig. 4 for natural convection. Device
Fig. 3. (a) A three dimensional mathematical model of the package in an isometric view, (b) a perspective of a far field treatment at full domain.
junction temperatures as well as the thermal resistance of packages can be predicted with a good accuracy for different ranges of power levels in natural convection. The numerically estimated die junction temperatures have also been found to be accurate and reliable: the differences against measured data are less than 15 percent. 2.2.2. RLC extraction For electric performance, parametric studies are also performed to investigate the effects of bond wires with different diameter and horizontal distance, and variations in signal traces. Electrical simulation was executed to characterize a 71-ball stack package. The cross-sectional views of the package are shown in Fig. 1. Electrical performances were compared in terms of insertion loss, return loss, cross talk noise and propagation delay. To look at the performance heterogeneity as a result of manufacturing process, parametric studies are also performed to investigate the effects of bond wires with 25.4 lm diameter and horizontal distances, and variations in signal traces. These results provide useful insights on design and process selection for high-performance semiconductor packages. Both Optimal PakSi-E 5.0 and Ansoft Q3D were used to extract the RLCs of the longest and shortest nets as well as the target nets
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plane by two perfect conductors which represent local chip ground. Table 5 presents the RLC simulation results. By the simulation, the RLC measurement at stacked die package can pass the Intel qualification of electric performance.
3. Assembly technology and system test
PCB
DDR2 90nm Stacked Die
After the final BOM was set, we started to design the assembly process flow. The assembly process was designed with consideration of manufacturability and product structural design. It would include electrical continuity (Open/Short) test after die-attached process. More importantly, this electrical continuity screening, allows the tracking of the first pass die attach yield level and sortout the imperfect attachment to prevent wastage of wire bond Known Good Die (KGD). Assembly yield shows good results, and also indicate in the reliability MSL3, TC500, HTS and HAST as illustrated in Table 3. For a 5.3 GB/s high data-rate DRAM module of 1 Gb DDR2 stacked die package, it is high data transfer rate and large memory
Fig. 4. Temperature profile under natural convection and power level of 1 W. Table 3 Assembly results.
in the package of 1 Gb DDR2 stacked die as illustrated in Fig. 5. Simplified 4-point profile recommended by [7] is adopted for bond wire simulation. The package is simulated with a copper ground reference plane 0.152 mm away from the bottom of the solder ball [8]. All VSS and VDD class nets are assigned as GND and Powers nets, respectively for comprehensive signal return path. Between the package and the reference ground plane is BT epoxy. Also, to investigate the high frequency characteristics of the stack package, the target signal nets are simulated in the frequency range of 667 Hz and 800 GHz. The signal nets are set up as a four-port system. All the four-ports are lumped gap ports with an impedance value of 50 Ohm. At the ball side, the ports extend from the bottom of the solder ball directly to the PCB ground reference plane. At the wire/bump side, the ports are shorted to the PCB ground reference
Lot
A
B
C
Sample size Assembly yield (%) Reliability test (MSL 3) (%) HAST (144 h) 130 °C/85 °C/RH/Bias1.98 V (%) HTS (500 h) (%) TC 500 cycle 55 °C/125 °C (%)
231 99.9 100 100 100 100
231 99.8 100 100 100 100
231 99.9 99 100 100 100
Table 4 Characteristics of 1 Gb DDR2 stacked die DRAM. Process technology Chip size Internal clock frequency Organization Data-rate CAS access time RAS access time Supply voltage (Periphery) (Array) Refresh cycle/period Active current (Icc1) Package
90 nm 3Metal CMOS 8.01 16.13 (mm) 333 MHz 256 Mb 4 8 banks 5.3 GB/s 11 ns (3 Clock cycles + 2 ns) 37 ns 1.8 V 1.5 V 16 K/64 ms 70 mA (Tc = 30 ns) 71-ball stack package
Table 5 RLC results of selected nets for bottom die (D1) and top die (D2) at 800 MHz.
Fig. 5. 1 Gb 90 nm DDR2 stack package in Ansoft Q3D (a) 3D model and (b) side view.
Net
R (m Ohm)
Ls (nH)
Cs (pF)
ADD_0-D1 ADD_0-D2 ADD_10-D1 ADDJIC-D2 VIO_0-D1 VIO_0-D2 VI0_7-D1 VIO_7-D2 LDQS-D1 LDQS-D2 LDM_RDQS-D1 LDM_RDQS-D2 BCS0-D1 BCS1-D2 ODT0D1 0DT1-D2 CKE0-D1 CKE1-D2
898.70 944.40 89S.40 943.S0 893.10 93a.flO 83 fl.9O 934.30 90O.S0 945.40 87O0 923.90 1065.00 1091.00 1049.00 1113.00 1079.00 1113.00
8.43 9.34 8.36 9.06 8.66 9.10 9.42 9.81 8.93 9.36 9.22 9.55 8.25 9.32 8.00 9.42 8.71 9.73
1.95 1.95 1.84 1.84 1.92 1.92 1.94 1.94 1.77 1.77 1.65 1.65 1.99 2.03 2.09 1.93 2.17 2.22
1120
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and the result shows the excellent eye width 2.5 ns as shown in Fig. 6a. For the spec of DQ at the same bounds, the range is located in tIS = 100 ps to tIH = 175 ps. The result shows the excellent eye width 1.1 ns as shown in Fig. 6b.
(a)
VIH=1.15V VIL=0.65V 2.58ns
2.58n
2.53n
2.60n
(b)
VIH=1.15
1.14ns
1.06ns
1.09ns
VIL=0.65
4. Conclusion A 5.3 GB/s high data-rate and high capacity 4 Gb RDIMM have been developed by stack package based on the 1 Gb 90 nm DDR2 die. Its high data transfer rate and large memory capacity are particularly well suited to the advanced memory system. For the application of the package technology by stacked die, there are some challenges were made as shown below. 1. Silicon integration: our new qualified package, stacked die by wire bond technology, is the best solution for high density and capacity modules from the two mainstream device process-application is for small, lightweight and cost effective consumer products. 2. Material selection: the best available spacer and epoxy mold compound materials have been identified which has a good compatibility for the staked die package through simulation. This is also qualified by reliability tests, including TC, HTS and HAST. 3. Wafer thinning process is one of the most difficult among the challenges in developing the stacked die package. For the manufacturability and yield control, the process has been optimized successfully.
Acknowledgments Fig. 6. Operating waveform (a) command pin at/CS and (b) I/O pin at DQ51.
capacity are targeted to the advanced unique memory system for serving high-end workstations, servers and laptops. The characteristics of the DDR2 DRAM are listed in Table 4. To reduce the power consumption, supply voltage for the cells has been set at 1.5 V while a 1.8-V is applied to other circuits. Also, a 0.27(V) Vbb is applied to the memory cell substrate in the sleep mode to extend the refresh period. To prevent the performance from deteriorating at 1.5 V, several techniques such as charge transferred well sensing and negative voltage word line are adopted. Fig. 6 shows the operating waveform of the stacked chip in the 4 GB RDIMM. The command pin of/CS access time at 1.8 V is 12 ns, and the latency is four external clock cycles. Since 64b are read in parallel every 3 ns, a high data-rate of 5.3 GB/s is successfully achieved. The spec is in the range of tIS = 200 ps to tIH = 275 ps at the upper bound VIH = 1.15 V to lower bound VLH = 0.65 V,
The author wishes to appreciate teammate YM Chen and Eric Chang for data preparations. Thanks system lab. colleagues, Allen, Chin-Fan and Bou-Chi for the inquiry of related information. Also, thanks Sam Lee’s and Leo Lee, Kevin Ho and Matt Yang for the encouragement on the technical data. Especially, thanks Cristina friendly support on the table fabrication. References [1] [2] [3] [4] [5] [6] [7] [8]
Horiguchi M et al. In: ISSCC technical digest; 1995. p. 252. Yoo J et al. In: ISSCC technical digest; 1996. p. 378. Sugibayashi T et al. In: ISSCC technical digest; 1995. p. 254. Pan SJ et al. In: IEEE/CPM/SEMI International Electronics Manufacturing Technology Symposium; 2003. p. 125. Spiesshoefer S et al. J Vac Sci Technol 2005;A23(4):824. John Reche. In: IEEE/CPMT meeting; 2000. p. 1. EIA/JEDEC. EIA/JESD59 bond wire modeling standard; June 1997. EIA/JEDEC. EIA/JEP126 guideline for developing and documenting package electrical models derived from computational analysis; May 1996.