- Email: [email protected]
Development of front-end electronics for mini-strip RPC readout
ARTICLE IN PRESS Nuclear Instruments and Methods in Physics Research A 602 (2009) 754–756
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
Development of front-end electronics for mini-strip RPC readout Y. Shinde b,, G. De Robertis a, G. Iaselli b, F. Loddo a, G. Pugliese a, S. Tupputi b, G. Roselli b a b
INFN-Sezione Di Bari Via Orabona, 4, 70125 Bari, Italy Dipartimento Interateneo di Fisica and Sezione INFN, Via G. Amendola 173, 70126 Bari, Italy
a r t i c l e in f o
a b s t r a c t
Available online 3 January 2009
The design and test of a single-gap resistive plate chamber instrumented with mini-strip readout is discussed. Efficiency and charge distribution are studied by means of cosmic muons using a small vertical telescope. The feasibility of inferring the position of the impinging particle is studied from the peak charge strip position. On the basis of these results a dedicated front-end VLSI is designed and prototyped. & 2008 Elsevier B.V. All rights reserved.
Keywords: RPC Spatial resolutions Ministrips
1. Introduction Resistive plate chambers (RPC) have been widely and successfully used in the past as a timing detector [1]. Also experiments at LHC have developed and installed large RPC detectors for fasttriggering purpose [2]. In all these cases, a limited tracking capability, of the order of cm, is also provided using strip readout planes. It is of interest to investigate if RPC technology could also be exploited to achieve sub-millimeter spatial resolution together with the excellent time resolution. A set of experimental measurements on a small RPC prototype instrumented with a mini-strip readout plane are reported and discussed. Results of preliminary measurements are also important to set design parameters for a possible front-end electronic development which will be suitable to readout multiple mini-strips.
Due to the limited number of readout channels available, only 8 strips are readout in this phase. The RPC chamber is therefore placed such that those strips are covered by the trigger cone. Signals from strips are directly fed to the DAQ system without any intermediate electronics, for charge measurement. Data is acquired by means of Acqiris high-speed data acquisition system [3] with two digitizer cards (DC 271), each having 4 data channels. Each channel has 1 GHz bandwidth, with 8 bit ADC. This allowed us to read data from 8 strips of mini-strip readout plane. Trigger is obtained by feeding signals of all three scintillators to a logic coincidence unit and its output signal is used as an external trigger for DAQ unit. A data acquisition software is developed using the National Instruments Lab VIEW 8.2. On every external trigger, this software stores all the data from Acqiris for defined time window. The Trigger delay is managed in the software. This saved data is then compressed without loss of information.
2. Experimental setup 3. Data analysis and results Measurements are performed on a single-gas-gap RPC with 10 10 cm2 sensitive area and 2 mm gas-gap width. The detector is instrumented with a mini-strip readout plane, produced by the simple PCB technology, having ground plane on one side of PCB and mini-strips on the other side facing towards the RPC (Fig. 1). Mini-strips are 0.8 mm wide with 1 mm pitch. The test setup consists of a telescope of three scintillators triggering vertical muon tracks in a 301 cone (Fig. 2). The RPC detector was operated in avalanche mode with a gas mixture composed of 96.2% C2H2F4, 3.5% i-CH10, 0.3% SF6.
Corresponding author. Tel.: +390805442346; fax: +390805442370.
E-mail address: [email protected] (Y. Shinde). 0168-9002/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2008.12.130
Event by event, the data stored is analyzed to identify the channel that crosses a set threshold first and to find for each strip various signal parameters, like signal-arrival time and collected charge. The charge is computed by finding the area under signal for channels that cross a set threshold. Channel with maximum charge is found, while the ones below set threshold are assumed to have zero charge. Relative time at which every channel reach its maximum value and time at which every channel crosses the threshold are also computed. In Fig. 3 the chamber efficiency as a function of the high voltage is shown. The proper study of charge distribution requires the selection of events fully contained in 8 strips width (i.e. both side zeros of
ARTICLE IN PRESS Y. Shinde et al. / Nuclear Instruments and Methods in Physics Research A 602 (2009) 754–756
755
Integral-normalized charge profile Foam Foam
0.4
-HV
Readout PCB
Ground Ground layer layer Foam Foam
Fig. 1. RPC equipped with mini-strip readout plane.
Total charge fraction
Mini strips
Gas GasGap Gap
0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 -4
-2
Overlap 8 mm Scintillator 1 RPC Mini-strips
0 strip number
2
4
Fig. 5. Normalized strip charge profile.
Scintillator 2
Residuals distribution
Scintillator 3
Sigma 0.43+/-0.02
90 80 Entries/0.5strip
Fig. 2. Experimental setup.
100 90
60 50 40 30 20 10
80 Efficiency
70
0 -2
70
-1.5
-1
-0.5
0
0.5
1
1.5
2
Δstrip
60
Fig. 6. Residual distribution.
50 40 9.6
9.7
9.8
9.9
10
10.1
10.2
Top Pad
CSA
Bott. Pad
CSA
Thr
HV (kV)
Digital Section
CSA
S/H
CSA
S/H
CSA 0
1
2
3 4 Strip Number
5
6
7
Fig. 4. Events which are contained in 8 strips width.
charge profile, lie in 8 strips width). An example of two such events is shown in Fig. 4. These events may have charge peak at different positions. For studying charge distribution, we translate them to have charge peak position always at zero. Fired strips on left side of charge
Analog Analog Mux Mux
Thr
Charge
Fig. 3. Chamber efficiency vs. high voltage.
ADC 8 bit
S/H Fig. 7. Chip block diagram.
peak position are numbered with negative digits and those on right are numbered with positive ones. Fig. 5 shows the normalized average charge profile at HV=10.2 kV. About 40% of total induced charge is present in the strip having peak charge, while adjacent strips on both sides contain around 22% of total charge. This shows that peak is highly distinguished. The average value of the peak charge is about 140 fC.
ARTICLE IN PRESS 756
Y. Shinde et al. / Nuclear Instruments and Methods in Physics Research A 602 (2009) 754–756
INPUT from AnalogMux
I/O BUS
ADC ADC
S/H MUX[31:0] INT_TRG (from PADs) EXT_TRG
D[7:0]
Trigger
FSM FSM
control
Registers Registers
Internal_clock DATA_READY clock
RD, WR, CS
Clock BUS BUSControl Control
control
A[10:0] BASE[4:0]
Fig. 8. Digital-section block diagram.
Residuals between the charge peak position and center of charge are also calculated. Center of charge is defined as P Qx Center of charge ¼ Pi i i iQ i where Qi is the charge on strip number xi.In Fig. 6 the residual distribution is reported. RMS is about 0.43 mm.
4. New front-end chip On the basis of the previous results a prototype VLSI-mixed analog-digital circuit has been developed to readout an RPC equipped with mini-strips and select the strip with highest charge. It was developed in the AMS 0.35 mm technology; the die area is 8 mm2 and is fit in a CQFP80 package. The circuit consists of 16 identical channels, made of a chargesensitive amplifier (CSA) with a charge sensitivity set to 0.33 mV/ fC, a sample-and-hold and an analog multiplexer. Two more channels are dedicated to amplify and discriminate possible additional external signals for triggering purposes (Fig. 7). The digital section (Fig. 8) implements the following functions:
manages the two external signals to generate internal trigger
signal, with programmable OR/AND logic; controls the 8-bit ADC (40 fC resolution); suppress the signals below (digital) the threshold; finds the channel with highest charge; flags the presence of data to be read (DATA_READY); communicates with the Intel-like parallel bus; and sets the internal clock active only during conversion and readout.
fier. The first chip is also connected to the two external trigger signals. The board is controlled by a Spartan-3 FPGA (XC3S200), which handles commands for reading/writing registers in all front-end chips connected to it. It has command decoding FSM, which interprets commands received on the serial port from PC and controls parallel-bus connected to all the front-end chips accordingly. It also sends back data on serial port if necessary. For all the front-end chips FPGA acts as a parallel bus master controller. The board is in testing phase, software is developed using the Lab VIEW 8.2, which provides a GUI on PC to send commands to the FPGA and to read data sent by FPGA on serial port. This data is stored in a file for further offline analysis.
6. Conclusions The design and test of a resistive plate chamber single-gapinstrumented with mini-strip readout is discussed. The feasibility of inferring the position of the impinging particle from the peakcharge strip position is studied. Residuals between the charge peak position and center of charge are also calculated and found to about 0.43 mm. On the bases of these results a dedicated front-end VLSI has been designed and prototyped. The front-end board is now in the testing phase.
Acknowledgments We would like to thank Mr. N. Lacalamita and Mr. M. Papagni for their valuable assistance and help in setting up the experiment. References
5. The front-end board The board integrates both the mini-strip plane and the four front-end VLSI chips. It is equipped with 64 strips with 0.8 mm wide and 0.2 mm pitch, and directly AC-coupled to the preampli-
[1] A. Zallo, Nucl. Instr. and Meth. A 456 (2000) 117; A. Aloisio, et al., Nucl. Instr. and Meth. A 456 (2000) 113. [2] CMS Collaboration, The Muon Project, CERN/LHCC 97-32, 15 December 1997.; ATLAS collaboration, technical design report, CERN-99-001. [3] AQUIRIS web page: /http://www.acqiris.com/products/digitizers.htmluS.
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
Development of front-end electronics for mini-strip RPC readout Y. Shinde b,, G. De Robertis a, G. Iaselli b, F. Loddo a, G. Pugliese a, S. Tupputi b, G. Roselli b a b
INFN-Sezione Di Bari Via Orabona, 4, 70125 Bari, Italy Dipartimento Interateneo di Fisica and Sezione INFN, Via G. Amendola 173, 70126 Bari, Italy
a r t i c l e in f o
a b s t r a c t
Available online 3 January 2009
The design and test of a single-gap resistive plate chamber instrumented with mini-strip readout is discussed. Efficiency and charge distribution are studied by means of cosmic muons using a small vertical telescope. The feasibility of inferring the position of the impinging particle is studied from the peak charge strip position. On the basis of these results a dedicated front-end VLSI is designed and prototyped. & 2008 Elsevier B.V. All rights reserved.
Keywords: RPC Spatial resolutions Ministrips
1. Introduction Resistive plate chambers (RPC) have been widely and successfully used in the past as a timing detector [1]. Also experiments at LHC have developed and installed large RPC detectors for fasttriggering purpose [2]. In all these cases, a limited tracking capability, of the order of cm, is also provided using strip readout planes. It is of interest to investigate if RPC technology could also be exploited to achieve sub-millimeter spatial resolution together with the excellent time resolution. A set of experimental measurements on a small RPC prototype instrumented with a mini-strip readout plane are reported and discussed. Results of preliminary measurements are also important to set design parameters for a possible front-end electronic development which will be suitable to readout multiple mini-strips.
Due to the limited number of readout channels available, only 8 strips are readout in this phase. The RPC chamber is therefore placed such that those strips are covered by the trigger cone. Signals from strips are directly fed to the DAQ system without any intermediate electronics, for charge measurement. Data is acquired by means of Acqiris high-speed data acquisition system [3] with two digitizer cards (DC 271), each having 4 data channels. Each channel has 1 GHz bandwidth, with 8 bit ADC. This allowed us to read data from 8 strips of mini-strip readout plane. Trigger is obtained by feeding signals of all three scintillators to a logic coincidence unit and its output signal is used as an external trigger for DAQ unit. A data acquisition software is developed using the National Instruments Lab VIEW 8.2. On every external trigger, this software stores all the data from Acqiris for defined time window. The Trigger delay is managed in the software. This saved data is then compressed without loss of information.
2. Experimental setup 3. Data analysis and results Measurements are performed on a single-gas-gap RPC with 10 10 cm2 sensitive area and 2 mm gas-gap width. The detector is instrumented with a mini-strip readout plane, produced by the simple PCB technology, having ground plane on one side of PCB and mini-strips on the other side facing towards the RPC (Fig. 1). Mini-strips are 0.8 mm wide with 1 mm pitch. The test setup consists of a telescope of three scintillators triggering vertical muon tracks in a 301 cone (Fig. 2). The RPC detector was operated in avalanche mode with a gas mixture composed of 96.2% C2H2F4, 3.5% i-CH10, 0.3% SF6.
Corresponding author. Tel.: +390805442346; fax: +390805442370.
E-mail address: [email protected] (Y. Shinde). 0168-9002/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2008.12.130
Event by event, the data stored is analyzed to identify the channel that crosses a set threshold first and to find for each strip various signal parameters, like signal-arrival time and collected charge. The charge is computed by finding the area under signal for channels that cross a set threshold. Channel with maximum charge is found, while the ones below set threshold are assumed to have zero charge. Relative time at which every channel reach its maximum value and time at which every channel crosses the threshold are also computed. In Fig. 3 the chamber efficiency as a function of the high voltage is shown. The proper study of charge distribution requires the selection of events fully contained in 8 strips width (i.e. both side zeros of
ARTICLE IN PRESS Y. Shinde et al. / Nuclear Instruments and Methods in Physics Research A 602 (2009) 754–756
755
Integral-normalized charge profile Foam Foam
0.4
-HV
Readout PCB
Ground Ground layer layer Foam Foam
Fig. 1. RPC equipped with mini-strip readout plane.
Total charge fraction
Mini strips
Gas GasGap Gap
0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 -4
-2
Overlap 8 mm Scintillator 1 RPC Mini-strips
0 strip number
2
4
Fig. 5. Normalized strip charge profile.
Scintillator 2
Residuals distribution
Scintillator 3
Sigma 0.43+/-0.02
90 80 Entries/0.5strip
Fig. 2. Experimental setup.
100 90
60 50 40 30 20 10
80 Efficiency
70
0 -2
70
-1.5
-1
-0.5
0
0.5
1
1.5
2
Δstrip
60
Fig. 6. Residual distribution.
50 40 9.6
9.7
9.8
9.9
10
10.1
10.2
Top Pad
CSA
Bott. Pad
CSA
Thr
HV (kV)
Digital Section
CSA
S/H
CSA
S/H
CSA 0
1
2
3 4 Strip Number
5
6
7
Fig. 4. Events which are contained in 8 strips width.
charge profile, lie in 8 strips width). An example of two such events is shown in Fig. 4. These events may have charge peak at different positions. For studying charge distribution, we translate them to have charge peak position always at zero. Fired strips on left side of charge
Analog Analog Mux Mux
Thr
Charge
Fig. 3. Chamber efficiency vs. high voltage.
ADC 8 bit
S/H Fig. 7. Chip block diagram.
peak position are numbered with negative digits and those on right are numbered with positive ones. Fig. 5 shows the normalized average charge profile at HV=10.2 kV. About 40% of total induced charge is present in the strip having peak charge, while adjacent strips on both sides contain around 22% of total charge. This shows that peak is highly distinguished. The average value of the peak charge is about 140 fC.
ARTICLE IN PRESS 756
Y. Shinde et al. / Nuclear Instruments and Methods in Physics Research A 602 (2009) 754–756
INPUT from AnalogMux
I/O BUS
ADC ADC
S/H MUX[31:0] INT_TRG (from PADs) EXT_TRG
D[7:0]
Trigger
FSM FSM
control
Registers Registers
Internal_clock DATA_READY clock
RD, WR, CS
Clock BUS BUSControl Control
control
A[10:0] BASE[4:0]
Fig. 8. Digital-section block diagram.
Residuals between the charge peak position and center of charge are also calculated. Center of charge is defined as P Qx Center of charge ¼ Pi i i iQ i where Qi is the charge on strip number xi.In Fig. 6 the residual distribution is reported. RMS is about 0.43 mm.
4. New front-end chip On the basis of the previous results a prototype VLSI-mixed analog-digital circuit has been developed to readout an RPC equipped with mini-strips and select the strip with highest charge. It was developed in the AMS 0.35 mm technology; the die area is 8 mm2 and is fit in a CQFP80 package. The circuit consists of 16 identical channels, made of a chargesensitive amplifier (CSA) with a charge sensitivity set to 0.33 mV/ fC, a sample-and-hold and an analog multiplexer. Two more channels are dedicated to amplify and discriminate possible additional external signals for triggering purposes (Fig. 7). The digital section (Fig. 8) implements the following functions:
manages the two external signals to generate internal trigger
signal, with programmable OR/AND logic; controls the 8-bit ADC (40 fC resolution); suppress the signals below (digital) the threshold; finds the channel with highest charge; flags the presence of data to be read (DATA_READY); communicates with the Intel-like parallel bus; and sets the internal clock active only during conversion and readout.
fier. The first chip is also connected to the two external trigger signals. The board is controlled by a Spartan-3 FPGA (XC3S200), which handles commands for reading/writing registers in all front-end chips connected to it. It has command decoding FSM, which interprets commands received on the serial port from PC and controls parallel-bus connected to all the front-end chips accordingly. It also sends back data on serial port if necessary. For all the front-end chips FPGA acts as a parallel bus master controller. The board is in testing phase, software is developed using the Lab VIEW 8.2, which provides a GUI on PC to send commands to the FPGA and to read data sent by FPGA on serial port. This data is stored in a file for further offline analysis.
6. Conclusions The design and test of a resistive plate chamber single-gapinstrumented with mini-strip readout is discussed. The feasibility of inferring the position of the impinging particle from the peakcharge strip position is studied. Residuals between the charge peak position and center of charge are also calculated and found to about 0.43 mm. On the bases of these results a dedicated front-end VLSI has been designed and prototyped. The front-end board is now in the testing phase.
Acknowledgments We would like to thank Mr. N. Lacalamita and Mr. M. Papagni for their valuable assistance and help in setting up the experiment. References
5. The front-end board The board integrates both the mini-strip plane and the four front-end VLSI chips. It is equipped with 64 strips with 0.8 mm wide and 0.2 mm pitch, and directly AC-coupled to the preampli-
[1] A. Zallo, Nucl. Instr. and Meth. A 456 (2000) 117; A. Aloisio, et al., Nucl. Instr. and Meth. A 456 (2000) 113. [2] CMS Collaboration, The Muon Project, CERN/LHCC 97-32, 15 December 1997.; ATLAS collaboration, technical design report, CERN-99-001. [3] AQUIRIS web page: /http://www.acqiris.com/products/digitizers.htmluS.