- Email: [email protected]
Device modeling in the frame of Project ADEQUAT
ELSEVIER
Microelectronic Engineering 34 (1996) 67-84
Device modeling in the frame of Project ADEQUAT 1 a:g
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M. Rudan ' , M.C. Vecchl , A. v. Schwerin b, W. S c h o e n m a k e r , A. De K e e r s g l e t e r , K. McCarthy a, A. Mathewson d, D.B.M. Klaassen e, J.A.M. Otten t, S.K. Jones g, J.G. Metcalfe g aDipartimento di Elettronica, InJbrmatica e Sistemistica, Universith di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy bSiemens AG, Corp. R&D, ZFE BT ACM31, Otto-Hahn-Ring 6, D-81739 Miinchen 83, Germany ~IMEC, 75 Kapeldreef 3001 Leuven, Belgium JNational Microelectronics Research Centre, Cork, Ireland ~Philips Research Laboratories, Professor Holstlaan 4, 5656 AA Eindhoven, The Netherlands tFacul~.' of Electrical Engineering, Eindhoven University of Technology, Den Dolech 2, 5600 MB Eindhoven, The Netherlands gGEC-Marconi Materials Technology, Caswell, Towcester, Northants NN I2 8EQ, United Kingdom Abstract A number of activities recently carried out within Theme 4.2 - Device modeling - of Project ADEQUAT are selected and described here. Apart from illustrating the technical work in itself, the aim of the paper is also that of showing the cooperative effort and the positive interactions between the Institutions involved.
Keywords: Device modeling; 0.25 txm CMOS technology
1. Introduction The main concern of Phase 2 of Project ADEQUAT (February 1, 1994 - September 30, 1995) is the development of process modules for the next two submicron CMOS technologies. In particular, 0.35 p~m multilevel interconnect architectures and 0.25 ~m front-end architectures are addressed. For this, the application of advanced process- and device-simulation tools is mandatory. Workpackage 4 of the Project is devoted to modeling and is divided into Themes 4.1 ("Process modeling") and 4.2 ("Device modeling"). The latter is in turn subdivided into Tasks 4.2.1 ("Advanced energy-transport models") and 4.2.2 ("Support of device architecture and design").
This work was part of ADEQUAT (JESSI BT11) and was funded as ESPRIT Project 8002. S.K. Jones and J.G. Metcalfe acknowledge the support of GEC Plessey Semiconductors, who partly funded this work. * Corresponding author. 0167-9317/96/$15.00 Copyright © 1996 Elsevier Science B.V. All rights reserved Pll S0167-9317(96)00017-2
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M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
The ability of correctly describe hot-carrier effects plays an important role in the design of sub-micron devices. In the frame of the Task 4.2.1 of ADEQUAT, a strong effort has been devoted to hot-carrier modeling. Recent results are shown in Sections 2 and 3, where the activities of the University of Bologna and Siemens are briefly summarized. In the frame of this Task and in cooperation with IMEC, a number of benchmarks have been selected in order to test the models on realistic devices. In particular, the present status of the work on characterization and calibration based on the FOND devices is shown in Section 4. Statistical analysis and investigation on compact models are pursued in Task 4.2.2. Series-resistance measurement techniques have been investigated at TUE, using a method by which compact model parameters such as the gain factor /3 and the mobility reduction coefficients are obtained, independently from the series resistance (Section 5). At Philips, the spread in the threshold voltages and gain factors and their correlation coefficients has been analysed for both n- and p-well MOSFETs with large channel lengths from a CMOS production process. To this end a combination of process and device simulation tools has been used. Results are outlined in Section 6.1. Evaluation of public-domain and commercially-available compact MOS models for use in circuit simulation is also part of this Task. An evaluation of the BSIM3 MOSFET model from the University of Berkeley has been performed by the NMRC (Section 6.2). Finally, results from the validation of TCAD tools on a well-characterized GPS 0.5 txm conventional CMOS process, are reported. The applications considered at the NMOS transistor output and transfer characteristics together with bulk (substrate) current to assess hot-carrier impact-ionization effects (Section 7).
2. Full-band hydrodynamic model: Coefficient calculation The general scheme for the calculation of the hydrodynamic parameters carried out at the University of Bologna is based on the solution of the Boltzmann Transport Equation (BTE) by means of the Spherical-Harmonic Expansion (SHE) Method, and is made of the following steps: (1) fitting of the parameters within the SHE model, and (2) use of the distribution function obtained from the SHE model to calculate the macroscopic coefficients of the hydrodynamic equations, to be used in the in-house developed code HFIELDS-hydro. Step 2 will be described here. It is worth noting that, since the solution of the BTE by SHE is carried out accounting for the full band structure of the semiconductor, the form of the hydrodynamic equations must be consistent with such an approach. For the sake of conciseness, only the form of the full-band hydrodynamic model will be shown here, with reference to the electrons. The model is made of four equations; two of them, shown in Table 1, describe the flows of particle and energy in terms of the scalar unknowns n, Tn, s,, and of the electric field E. The normalized temperature r , = T n/T~, q is used in the table; in turn, s, is a known function of Table 1 Full-band hydrodynamic model: expression of the particle and energy negative flows LHS
RHS
h
Flow
Diff. term
Drift term
u
-no n -nP.,
Dpn grad(nr,) D q, grad(nsnr,, )
IzvnnE tZq, nsnE
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
69
Table 2 Full-band hydrodynamic model: expression o f the divergence o f the particle and energy flows LHS
RHS
h
Divergence o f flow
Drift term
1 e
div(nv,) div(nP,,)
-qnv,, "E
Time derivative
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Inter-b and coll.
Intra-b and coll.
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7",. The column indicated by h shows the function by which the moment of the BTE is calculated (u is the group velocity, e is the microscopic energy). The other two equations express the divergence of the flows and are shown in Table 2. The term w,, div(nvn) turns out to be a combination of the time-derivative and interband-transition terms, and is listed as such in Table 2. The symbols have the customary meaning of semiconductor theory. The coefficients of the hydrodynamic model are thus the mobilities and diffusivities of Table 1, the energy-relaxation time K,. of Table 2, and a further parameter embedded in the relation s,, = s,,(T,,). The definition of K,, is
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70
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
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energy-relaxation time is shown in Fig. 2. The calculation of the corresponding parameters for holes using the full valence band is one of the upcoming activities in Task 4.2.1. In the calculation of the coefficients by the SHE model, all the important scattering mechanisms are accounted for (e.g., acoustical and optical phonons, impurities, impact ionization). On the other hand, the numerical efficiency of SHE is superior to that of typical Monte Carlo codes. To conclude, the full-band hydrodynamic model supplemented with the SHE code is able to provide a realistic description of charge transport, including hot-carrier effects, suited for application in an industrial environment. This has already been demonstrated in the analysis of the soft-threshold effect of impact-ionization.
3. Hot-carrier degradation: Comparison of LATID and FOND One of the objectives within Task 4.2.1 of the ADEQUAT Project is the refinement of models for self-consistent simulation of MOSFET hot-carrier degradation. The purpose of these activities is to develop a simulation tool for MOSFET design optimization with respect to hot-carrier reliability. At Siemens, a prototype version of such a program based on the 2D-device simulator MINIMOS has been used to compare the characteristic behavior of two different drain design concepts which are under development in Workpackage 3 of ADEQUAT, namely the sol called LATID and FOND devices. The comparison is performed for devices with 8 nm oxide thickness and an effective channel length of 0.35 I,~m respectively. Due to the large gate/junction overlap in the case of the FOND device, the poly gate length in that case is 0.8 I,Lm, whereas the poly gate length for the LATID device was 0.5 Ixm. The doping profiles for the devices used in the simulation resulted from the processsimulation activities in Theme 4.1. The stress condition assumed in the hot-carrier simulation was 6 V
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
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at the drain and 6 V at the gate.2 Figs. 3 and 4 show a lateral cut through the doping profile near the drain sided gate edge together with the lateral electric field along the Si/SiO 2 interface at stress conditions for both devices. Apparently, the electric field in the case of the FOND device is significantly lower than in the LATID device. The electric field profile in the latter case exhibits a characteristic double-peak structure reflecting the junction doping. Fig. 5 shows as a result of the hot-carrier degradation simulation the integral of the stress-induced interface states, which is equivalent to the charge pumping current often used as a hot-carrier degradation monitor. Obviously, the FOND device exhibits significantly less hot-carrier degradation compared to the LATID device. This is consistent with the electric field data shown in Figs. 3 and 4. The superiority of the FOND concept with respect to hot-carrier reliability, however, is paid for
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2 This voltage conditions has been chosen because electron injection dominates device degradation behavior in this case. For lower stress gate voltage, hole injection plays an important role. The injection model for holes in the prototype version of the degradation simulator is still not very reliable. Therefore, this study was restricted to the electron injection bias regime. A refinement of the hole injection model is one of the upcoming activities in Task 4.2.1.
72
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
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with slightly inferior short-channel behavior and AC-performance: Fig. 6 shows a plot of saturation drain current as a function of short-channel roll-off. Minimum manufacturable channel length is limited by a certain short-channel roll-off. Thus, the maximum achievable saturation current in a well controlled process is significantly higher for LATID devices. As to the AC performance: gate/drain overlap capacitance in the case of FOND devices is about twice as high as in the LATID case, the total gate capacitance is (in agreement with the ratio of poly gate lengths) more than 50% larger for FOND. To conclude, for device optimization it is important to find the optimum trade-off between hot-carrier reliability and device performance. A simulation tool like the one developed in Task 4.2.1 0.0006
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Fig. 6. Simulated saturation drain current at Vd = 3.3 V, V = V,h + 2.5 V as a function o f short channel roll-off (defined by the difference between V,h at given gate length and long channel V,h). The parameter changed in simulation was the poly gate length. The solid line shows the result for LATID, dashed line is used for the F O N D results.
M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
73
of ADEQUAT which allows to calculate hot-carrier device degradation self-consistently can be of significant benefit for this purpose, in articular in the case of state-of-the-art device concepts where a large number of process parameters has to be optimized.
4. Hydrodynamic simulations of FOND structures Within the ADEQUAT Project, the emphasis is on development of CMOS technology which satisfies a series of specifications on reliability, speed, drive voltages and others and, moreover, this technology should be manufacturable with sufficient yield. This combined set of requirements puts strong demands on the transistor architecture. Therefore, within ADEQUAT a serious amount of resources is allocated to explore various transistor architectures and, from the modelling point of view, the emphasis is on a detailed understanding of the various device concepts and moreover to use this as a starting point for performing studies of yield optimization. Such a task setting naturally divides itself into three subtasks: first of all, a choice must be made of the tools which will be used for performing the simulations of the devices, in order to "look into" the devices; secondly, once the tools have been selected, a calibration task starts; finally, using the calibrated simulators, the optimization of the next generation of devices can be initiated. The choice of tools is strongly influenced by the capability of including the advanced structures into the simulators. Unfortunately, standard tools lack the sufficiently advanced physical models which are believed to be important for the device structures which have been suggested within the Project. Therefore, a necessary condition for the tools is to have access to the source codes of the tools in order to include the modifications needed for the simulation of new architectures. Within a Project of the size of ADEQUAT it is also important that data exchange between the various sites is done in a common format. These two conditions have led to work within ADEQUAT with the STORM software as a basis for process simulation, with HFIELDS (which has a smooth interface to STORM) for device simulation, as well as MINIMOS and NORMAL/DEBORA for the optimization based on response surfaces (RSM) constructed by a design of experiment (DOE) approach. The next step, being the calibration of the various tools, is a very tedious and difficult task. The reason is that we may not allow for a too-big discrepancy between the generation of technology that we want to use for calibration and the generation for which we want to optimize the process flow. Within ADEQUAT, we have followed the relations 0.50 i.Lm-calibration
~
0.35 p~m-optimization
0.35~m-calibration
---> 0.25 ~m-optimization
and next
The first step has been partly covered during the first phase of the Project. Most of the effort of IMEC within modeling has been allocated to the 0.35 i.Lm-device calibration. We will present here the present status of this work. In particular, we use the FOND devices which have been extensively characterized as the experimental basis for the calibration. The simulation of the FOND structures has confronted us with the problem of using process simulators which are not fully equipped for the task that is required. In particular, the implantation through the thick multilayer system, poly and SiO z needed considerable adaption of the implantation parameters. The change accounts for the grain size in the poly layer as well as the crystal orientation of the grains. Furthermore, the lateral straggling in silicon has also been changed.
74
M. Rudan et al.
Microelectronic Engineering 34 (1996) 67-84
,
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Fig. 7. The las-V~s characteristic of the 0.35 txm FOND structure at Vd~ = 0.1 V. The crosses ( × ) are the experimental results.
In Fig. 7, the/d,-Vgs characteristic is shown for Vds = 0.1 V. The crosses ( × ) are the experimental results from the 0.35 Ixm FOND devices processed at IMEC. The full line shows the simulation results using the default settings of the implantation parameters and the dashed line represents the simulation result after calibration, i.e., using adjusted implantation parameters. It should be emphasized that in present technologies, the constraint on the termal budget is severe, which implies that all ramping steps have to be included in a realistic way. The assumption that the anneal steps wipe out transient effects is not valid at all. Using the improved process simulation for the FOND devices we can now have a look inside the devices and find the hot spot(s). In Fig. 8 part of a device
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M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
75
in the drain region is shown for Vg.~= 1.1 V and Va~,= 2.5 V, which corresponds to the values for which a maximal substrate current is found. The figure shows the location of the hot spot removed from the spacer edge. Furthermore, the amount of hot-carrier generation is much less, than for conventional LDD structures with comparable dopant distributions.
5. Determination of the series resistance and effective channel length from one single or set of submicron MOSFETs The new method described here only needs one single MOSFET to measure (a) the series resistance as a function of the gate and drain bias, (b) the ratio of the intrinsic conductances, and (c) the mobility-degradation coefficients. In [1] already such a method was presented to measure Rserie~ as a function of gate bias. However, due to some inaccuracies inherent to the method incorrect results can easily be obtained [2], which are still valid despite recent improvements [3]. The new method of TUE measures the conductance and transconductance as a function of externally added resistance as a function of the terminal biases. Next, the derivatives of the series resistance with respect to bias are obtained from these measurements. Integration of the derivatives yields the series resistance. So our method "measures" the series resistance by distinguishing between the intrinsic and extrinsic behavior of the device and is therefore not limited to MOSFETs only. In addition using our method, compact model parameters such as the gain factor /3 and the mobility reduction coefficients are obtained, independently from the series resistance. In Fig. 11 the measured increase of the drain series resistance Rdr~o is plotted as a function of drain bias at various values of gate bias. In comparison with our earlier results [4], the new method is also able to measure the drain series resistance in saturation as shown in Fig. 9 where measurement results are compared with theoretical results (dotted line). In this case Ror~, is plotted as a function of the bias across the resistance. The same method is used to determine R s e ~ as a function of the gate bias at low drain bias. Since we can measure the ratio of the intrinsic conductance and transconductance (Fig. 12) we are able to determine the bias across the intrinsic MOSFET and thus also the value of R~e~(V~,). In Fig. 13 a measurement example is given where the results are compared with results of another method [5] where a set of MOSFETs is needed to determine R~e~ie~(Ve).
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M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
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We also have been able to model the series resistance in the full bias range using only five additional parameters. Since according to two-dimensional device simulations the main current path in the junction is near the interface, as illustrated in Fig. 14 where the dissipation in the MOSFET is plotted, the gate-bias-dependent part of Rseries (at low drain bias) can be modelled as a sum of two accumulation resistances in parallel with a sheet resistance. The increase in Rdr~in is mainly due to velocity saturation resulting in a linear increase of Rdrai n with the bias across this resistance, as shown in Fig. 10. Momentarily results show that by the inclusion of a compact bias-dependent series70O
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v o (v) Fig. 13. The measured MOSFET total resistance and series resistance as a function of the gate bias at Vd =0.10V ( W = 10 I~m, L,, = 0.80 ~m). The series resistance curve (A) is the determined series resistance using a set of identical MOSFETs, curve (B) is derived from the single transistor measurement technique.
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78
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
resistance model in a compact MOSFET model, better physically-based parameters are obtained together with a slight increase in accuracy.
6. Compact MOS models
6.1. The effect of process variations on compact model parameters From the statistical analysis of a large number of batches of the Philips CMOS production process it was found that the spread in threshold voltage was indeed larger for p-channel than for n-channel devices. However, for both n- and p-channel devices the simulated spreads are larger than the measured ones. Also the simulated spreads in gain factors of both n- and p-channel devices are larger than the experimental values obtained from the statistical analysis mentioned above. By fitting the spreads, simulated for threshold voltages and gain factors, to the values experimentally observed, new realistic spreads in the process variables have been obtained. The distributions for threshold voltages and gain factors have been calculated with these spreads. The distributions for the gain factors are shown in Fig. 15 for n channels and in Fig. 16 for p channels. It should be noted that with the new spreads in the process variables mentioned above, the spreads in the threshold voltages and gain factors of both n- and p-channel MOSFETs are predicted with good accuracy. Using these spreads, the correlation coefficients for the threshold voltages and gain factors of both n- and p-channel MOSFETs have been evaluated. The correlation coefficients between two sets x~ and yi is given by N
Z i : 1 x i Y i --
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M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
79
P-channel
la.,
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Fig. 16. Simulated statistical distribution for the gain factor of the p-channel transistor. and O-y are the spreads of the sets x i and Yi. By way of example, the correlations between gain factors are shown in Figs. 17 (experimental) and 18 (calculated). All plotted values have been centered around the mean value and normalized to the corresponding spread. 6.2. Evaluation o f commercially available M O S F E T models
BSIM3 is the latest in a series of models for submicron MOSFETs developed at the University of Berkeley and available in the popular IC simulation program SPICE. It is version 2 of the model [6] (referred to as BSIM3V2) which is discussed here. At NMRC, BSIM3V2 model sets have been extracted from an array of 14 NMOS devices of size ranging from 10 Izm/10 I~m to 1 Ixm/0.8 I~m. To investigate the scaling properties of the model both single-device and geometry-independent parameter sets were extracted. The single-device parameter sets were extracted from one device at a time whereas the geometry-independent parameter set was extracted to fit all 14 devices simul-
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80
M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
calculated
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taneously and is the model set which would be used for design purposes. The single-device models give good prediction in all cases but the geometry-independent models show a degraded performance in some regions. Figs. 19 and 20 show measurements and simulations (with the geometry-independent model) for the 10 Ixm/0.9 Ixm device. In general the current and output conductance prediction is good but the gas curve at low Vgs shows that a negative g,,,+ can sometimes be predicted by the model. Figs. 21 and 22 show the variation of threshold voltage and one of the substrate current parameters (PSCBE2) with length for both the single-device and geometry-independent parameter sets. It is seen
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Microelectronic Engineering 34 (1996) 67-84
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i,,,
i,,,
i,,,i,.,
2
.3
4
5
6
v,, (v) Fig. 20. BSIM 3V2 scaling: the square shows values for V., (left) and PSCBE 2 for individual transistors; the solid lines show the values used in a geometry independent model.
that the scaling rules in the model give good prediction of V,h vs. length but do not allow a variation of PSCBE2 with length as happens in practice. Overall, BSIM3V2 is an improvement over previously available public-domain models but suffers from some discontinuity problems (as illustrated in Fig. 20) and would benefit from some extra scaling parameters (as illustrated by the plot of PSCBE2). It is hoped that these issues will be addressed in the next version, BSIM3V3.
0.90
....
I ....
I '
'~'
1 ....
0.85 -o
0.80
0.75
0.70 0.0
....
i .... 0.5
I .... I .0
~ .... 1.5
2.0
1/L.. ( 1 / ~ ) Fig. 21. Variation of threshold voltage with length for both the single device and geometry independent parameter set.
82
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4 25
'
2O
"(3
'
'
'
1
. . . .
I
. . . .
[
. . . .
I~ ~5
fl
r~
5 o
.... o.o
1,1t,1
J . o. . .
, .... 0.5
r,,:
1 .o
2.0
1.5
l/L.,, (1/~,m)
Fig. 22. Variation of one of the substrate-current parameters (PSCBE2) with length for both the single-device and geometry-independent parameter set.
7. Validation of T C A D tools on a 0.5 lutm N M O S transistor
The NMOS device 3 under consideration at GMMT consisted of a B high-energy implanted and diffused p well in a p epitaxial layer on a p substrate; a POC13 doped polysilicon gate with as drawn 0.55 Ixm gate length; and Double Diffused Drain (DDD) A s / P source/drain (S/D) architecture. The final simulated device structure and doping are shown in Fig. 23. The process simulation was optimized to achieve target parameter values for the metallurgical Left; saturation current (at --
+
I
'
'
'
l
l
l
l
1
l
a
l
l
l
l
l
l
,
l
l
I
l
I
l
tmC,h ( u m ) Fig. 23. n-MOS device structure and doping.
3 The device was designed, processed and measured by GEC Plessey Semiconductors; data supplied by courtesy of B.S. Bold.
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
Model ......N o r t h .....C e n t r e
6-
83
..............
4-
2-
.
0
1
2
3
.
.
.
4
VDs (V)
Fig. 24. n-MOS output characteristics. V~ = V~ = 3 V); and VT. Acceptable agreement was obtained for these primary device parameters using the standard STORM models throughout, except for the S / D where it was necessary to use the advanced M M G level of coupled dopant point-defect diffusion. It was important to model all thermal ramps and low temperature anneals; these had a significant effect on the dopant profiles and activation. The only significant difference with the device layout and process flow was that the drawn gate length had to be increased by 0.05 Ixm, in order to obtain the correct Leef value. The error is thought to be due to overestimation in the implant model prediction of lateral straggle of the As and P at the polysilicon gate edge. The asymmetry between source and drain contours is caused by a 7 ° tilt in the As ion implantation assumed to be in the plane of the device (zero rotation). The substrate current in a short channel MOSFET is substantially overestimated by the standard impact-ionization model in a drift-diffusion model (such as in HFIELDS) because of fast variations in
-400,
--Model ......N o r t h .... C e n t r e -
:t ~-~ - 2 0 0 -
-100-
1
2
3
4
v o (v) Fig. 25. n - M O S
substrate current versus gate bias for fixed V#,.
84
M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
the electric field. The hydrodynamic model gives a better estimate of substrate current since it uses the carrier temperature to estimate the carder energy distribution which then determines the impactionization generation rate, as in the model of Quade and Rudan implemented in HFIELDS-hydro [7]. In the simulation care was taken to achieve a sufficiently fine mesh and bias-step increment to ensure a numerically accurate solution. Due to some convergence difficulties experienced with the first 4 release of HFIELDS-hydro much user intervention was necessary to tune this strategy. Measurements were taken at two sites (N, C) on the wafer, having nominally the same drawn poly gate length of 0.55 Ixm, to assess wafer variability. The agreement in Vr was better than 0.04 V. The saturation current at Vd = Vg = 3 V was simulated as 5.42 mA, compared to 5.38 mA averaged over the two sites measured. The complete (/d, Vas) characteristic for a 15 lxm wide device is shown in Fig. 24 for a full range of gate biases. It can be seen that the model fits well within the range of measurements obtained from different sites on the wafer. The substrate current for the same devices is shown in Fig. 25. The peak value is slightly larger and occurs at a higher gate bias in the model than in the measurements. The agreement is excellent when compared to the drift-diffusion model which over-estimates I~ub by two orders of magnitude in this case. In order to investigate the process sensitivity and also the discrepancy in the modelled voltage bias at which the peak substrate current occurs, several model variations were investigated. Reversing the direction of As tilt, and hence S / D of the device, gives a reduction in/sub by ×0.25, this is due to the shape of the 2D drain. The location and temperature of the hot carders strongly affects the impact-ionization generation. The S/D activation level depends upon the final anneal temperature. Although a high activation level is achieved for high temperature RTA, this can be reduced by low temperature post-processing in which a fraction of the As can become non-substitutional. However, the S/D activation had only a small effect (2%) on the drain current.
References [1] [2] [3] [4] [5] [6] [7]
L. Selmi, IEEE Trans. Electron Devices 36 (1989) 1094-1100. J.A.M. Otten and F.M. Klaassen, In Proc. ESSDERC, 1991. L. Selmi et al., IEDM 94 Technical Digest (1994) 471-474. J.A.M. Otten and F.M. Klaassen, Proc. ESSDERC, 1992. J.A.M. Otten and F.M. Klaassen, to be published. J.H. Huang et al., BSIM3 Manual (version 2). Technical Report, University of California, Berkeley, CA, 1994. W. Quade, M. Rudan, and E. Sch611, Hydrodynamicsimulation of impact-ionization effects in p-n junctions, IEEE Trans. on CAD of lCAS 10 (10) (1991) 1287-1294.
4 The robustness problem has been traced back to the organization of the internal loops used in connection with current generators, and is eliminated in the present release.
Microelectronic Engineering 34 (1996) 67-84
Device modeling in the frame of Project ADEQUAT 1 a:g
.a
c
•
c
M. Rudan ' , M.C. Vecchl , A. v. Schwerin b, W. S c h o e n m a k e r , A. De K e e r s g l e t e r , K. McCarthy a, A. Mathewson d, D.B.M. Klaassen e, J.A.M. Otten t, S.K. Jones g, J.G. Metcalfe g aDipartimento di Elettronica, InJbrmatica e Sistemistica, Universith di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy bSiemens AG, Corp. R&D, ZFE BT ACM31, Otto-Hahn-Ring 6, D-81739 Miinchen 83, Germany ~IMEC, 75 Kapeldreef 3001 Leuven, Belgium JNational Microelectronics Research Centre, Cork, Ireland ~Philips Research Laboratories, Professor Holstlaan 4, 5656 AA Eindhoven, The Netherlands tFacul~.' of Electrical Engineering, Eindhoven University of Technology, Den Dolech 2, 5600 MB Eindhoven, The Netherlands gGEC-Marconi Materials Technology, Caswell, Towcester, Northants NN I2 8EQ, United Kingdom Abstract A number of activities recently carried out within Theme 4.2 - Device modeling - of Project ADEQUAT are selected and described here. Apart from illustrating the technical work in itself, the aim of the paper is also that of showing the cooperative effort and the positive interactions between the Institutions involved.
Keywords: Device modeling; 0.25 txm CMOS technology
1. Introduction The main concern of Phase 2 of Project ADEQUAT (February 1, 1994 - September 30, 1995) is the development of process modules for the next two submicron CMOS technologies. In particular, 0.35 p~m multilevel interconnect architectures and 0.25 ~m front-end architectures are addressed. For this, the application of advanced process- and device-simulation tools is mandatory. Workpackage 4 of the Project is devoted to modeling and is divided into Themes 4.1 ("Process modeling") and 4.2 ("Device modeling"). The latter is in turn subdivided into Tasks 4.2.1 ("Advanced energy-transport models") and 4.2.2 ("Support of device architecture and design").
This work was part of ADEQUAT (JESSI BT11) and was funded as ESPRIT Project 8002. S.K. Jones and J.G. Metcalfe acknowledge the support of GEC Plessey Semiconductors, who partly funded this work. * Corresponding author. 0167-9317/96/$15.00 Copyright © 1996 Elsevier Science B.V. All rights reserved Pll S0167-9317(96)00017-2
68
M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
The ability of correctly describe hot-carrier effects plays an important role in the design of sub-micron devices. In the frame of the Task 4.2.1 of ADEQUAT, a strong effort has been devoted to hot-carrier modeling. Recent results are shown in Sections 2 and 3, where the activities of the University of Bologna and Siemens are briefly summarized. In the frame of this Task and in cooperation with IMEC, a number of benchmarks have been selected in order to test the models on realistic devices. In particular, the present status of the work on characterization and calibration based on the FOND devices is shown in Section 4. Statistical analysis and investigation on compact models are pursued in Task 4.2.2. Series-resistance measurement techniques have been investigated at TUE, using a method by which compact model parameters such as the gain factor /3 and the mobility reduction coefficients are obtained, independently from the series resistance (Section 5). At Philips, the spread in the threshold voltages and gain factors and their correlation coefficients has been analysed for both n- and p-well MOSFETs with large channel lengths from a CMOS production process. To this end a combination of process and device simulation tools has been used. Results are outlined in Section 6.1. Evaluation of public-domain and commercially-available compact MOS models for use in circuit simulation is also part of this Task. An evaluation of the BSIM3 MOSFET model from the University of Berkeley has been performed by the NMRC (Section 6.2). Finally, results from the validation of TCAD tools on a well-characterized GPS 0.5 txm conventional CMOS process, are reported. The applications considered at the NMOS transistor output and transfer characteristics together with bulk (substrate) current to assess hot-carrier impact-ionization effects (Section 7).
2. Full-band hydrodynamic model: Coefficient calculation The general scheme for the calculation of the hydrodynamic parameters carried out at the University of Bologna is based on the solution of the Boltzmann Transport Equation (BTE) by means of the Spherical-Harmonic Expansion (SHE) Method, and is made of the following steps: (1) fitting of the parameters within the SHE model, and (2) use of the distribution function obtained from the SHE model to calculate the macroscopic coefficients of the hydrodynamic equations, to be used in the in-house developed code HFIELDS-hydro. Step 2 will be described here. It is worth noting that, since the solution of the BTE by SHE is carried out accounting for the full band structure of the semiconductor, the form of the hydrodynamic equations must be consistent with such an approach. For the sake of conciseness, only the form of the full-band hydrodynamic model will be shown here, with reference to the electrons. The model is made of four equations; two of them, shown in Table 1, describe the flows of particle and energy in terms of the scalar unknowns n, Tn, s,, and of the electric field E. The normalized temperature r , = T n/T~, q is used in the table; in turn, s, is a known function of Table 1 Full-band hydrodynamic model: expression of the particle and energy negative flows LHS
RHS
h
Flow
Diff. term
Drift term
u
-no n -nP.,
Dpn grad(nr,) D q, grad(nsnr,, )
IzvnnE tZq, nsnE
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
69
Table 2 Full-band hydrodynamic model: expression o f the divergence o f the particle and energy flows LHS
RHS
h
Divergence o f flow
Drift term
1 e
div(nv,) div(nP,,)
-qnv,, "E
Time derivative
-ri
Inter-b and coll.
Intra-b and coll.
C,, w,, div(nv,,)
- n ( w , , - w~i'~)/7-,....
7",. The column indicated by h shows the function by which the moment of the BTE is calculated (u is the group velocity, e is the microscopic energy). The other two equations express the divergence of the flows and are shown in Table 2. The term w,, div(nvn) turns out to be a combination of the time-derivative and interband-transition terms, and is listed as such in Table 2. The symbols have the customary meaning of semiconductor theory. The coefficients of the hydrodynamic model are thus the mobilities and diffusivities of Table 1, the energy-relaxation time K,. of Table 2, and a further parameter embedded in the relation s,, = s,,(T,,). The definition of K,, is
fue(k)f ; f d3k
Twn
,
Yt(W n --Wn
eq) .
(l)
As for the mobilities and diffusivities, they can be expressed in terms of effective mass tensors and of two additional relaxation times, namely, the momentum-relaxation time ~,n and the heat-relaxation time rq. The latter, in turn, are the trace of the tensors +p,,, +q~ defined as
fB u(k)
f - f d3k 7"
~
~-l no., Tpn
f8 u(k)e(k) f - f d3k r
rl. ~ ' nP.
=
(2)
"
By way of example, the electron momentum- and heat-relaxation times are shown in Fig. 1, the
0.2 Taupn - Tauqn ......
0.18 0.16 "~
g
0.14 0.12
•2
0.1
~
o.os
"~
0.06 0.04 0.02 i
i
i
i
i
i
i
J
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Energy (eV)
1.8
Fig. 1. Electron m o m e n t u m relaxation time (%,) and heat-relaxation time (%,,) as a function o f the average energy w,, (eV). The relaxation times are expressed in psec.
70
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
0.55 0.5 0.45 "=
J
0.4 0.35 0.3 0.25 0.2
i
i
i
0.2
0.4
0.6
i
i
i
0.8 1 1.2 Energy (eV)
i
i
1.4
1.6
1.8
Fig. 2. Electron energy relaxation time L., (psec) as a function of the average energy w,, (eV).
energy-relaxation time is shown in Fig. 2. The calculation of the corresponding parameters for holes using the full valence band is one of the upcoming activities in Task 4.2.1. In the calculation of the coefficients by the SHE model, all the important scattering mechanisms are accounted for (e.g., acoustical and optical phonons, impurities, impact ionization). On the other hand, the numerical efficiency of SHE is superior to that of typical Monte Carlo codes. To conclude, the full-band hydrodynamic model supplemented with the SHE code is able to provide a realistic description of charge transport, including hot-carrier effects, suited for application in an industrial environment. This has already been demonstrated in the analysis of the soft-threshold effect of impact-ionization.
3. Hot-carrier degradation: Comparison of LATID and FOND One of the objectives within Task 4.2.1 of the ADEQUAT Project is the refinement of models for self-consistent simulation of MOSFET hot-carrier degradation. The purpose of these activities is to develop a simulation tool for MOSFET design optimization with respect to hot-carrier reliability. At Siemens, a prototype version of such a program based on the 2D-device simulator MINIMOS has been used to compare the characteristic behavior of two different drain design concepts which are under development in Workpackage 3 of ADEQUAT, namely the sol called LATID and FOND devices. The comparison is performed for devices with 8 nm oxide thickness and an effective channel length of 0.35 I,~m respectively. Due to the large gate/junction overlap in the case of the FOND device, the poly gate length in that case is 0.8 I,Lm, whereas the poly gate length for the LATID device was 0.5 Ixm. The doping profiles for the devices used in the simulation resulted from the processsimulation activities in Theme 4.1. The stress condition assumed in the hot-carrier simulation was 6 V
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
o3
10 21
3.0 ' ~
1 020
2.5 2.0 ~jj v1.5 10 1.o "~
1019
o
t.= e~ 0
D
71
1016 1017
0.5
1016
0.0
0.2
0.3
0.4
0.5
0.6
0.7
Lateral position [um] Fig. 3. Doping profile (dashed line) and lateral electric field (solid line) along the Si/SiO 2 interface at stress conditions. The figure shows results for the LATID device. Device and stress conditions are given in the text.
at the drain and 6 V at the gate.2 Figs. 3 and 4 show a lateral cut through the doping profile near the drain sided gate edge together with the lateral electric field along the Si/SiO 2 interface at stress conditions for both devices. Apparently, the electric field in the case of the FOND device is significantly lower than in the LATID device. The electric field profile in the latter case exhibits a characteristic double-peak structure reflecting the junction doping. Fig. 5 shows as a result of the hot-carrier degradation simulation the integral of the stress-induced interface states, which is equivalent to the charge pumping current often used as a hot-carrier degradation monitor. Obviously, the FOND device exhibits significantly less hot-carrier degradation compared to the LATID device. This is consistent with the electric field data shown in Figs. 3 and 4. The superiority of the FOND concept with respect to hot-carrier reliability, however, is paid for
1021
3.0 '~'
102o
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1019
2.0 ~ 1.5 :""
t-
1018
o E3
1017
1.0 ~ 0.5 ~
.m.
1016 0.4
, 0.5
,,
,
,
,
0.6
0.7
0.8
0.0 ~ 0.9
Lateral position [um] Fig. 4. Doping profile (dashed line) and lateral electric field (solid line) along the Si-SiO 2 interface at stress conditions. The figures shows results for the FOND device. Device and stress conditions as given in the text.
2 This voltage conditions has been chosen because electron injection dominates device degradation behavior in this case. For lower stress gate voltage, hole injection plays an important role. The injection model for holes in the prototype version of the degradation simulator is still not very reliable. Therefore, this study was restricted to the electron injection bias regime. A refinement of the hole injection model is one of the upcoming activities in Task 4.2.1.
72
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
10.8 •
,<
LATID
10.9 .= --I o ,,..~ 10-1o E
'-'s
~ tll t,--
10-11
10-12 100
101
102
103
104
105
106
107
Stress time [s] Fig. 5. Calculated charge pumping current as a function of simulated stress time. Results are shown for a FOND device (open circles) and for a LATID device (filled square). Device geometry and stress condition as given in the text.
with slightly inferior short-channel behavior and AC-performance: Fig. 6 shows a plot of saturation drain current as a function of short-channel roll-off. Minimum manufacturable channel length is limited by a certain short-channel roll-off. Thus, the maximum achievable saturation current in a well controlled process is significantly higher for LATID devices. As to the AC performance: gate/drain overlap capacitance in the case of FOND devices is about twice as high as in the LATID case, the total gate capacitance is (in agreement with the ratio of poly gate lengths) more than 50% larger for FOND. To conclude, for device optimization it is important to find the optimum trade-off between hot-carrier reliability and device performance. A simulation tool like the one developed in Task 4.2.1 0.0006
m
i
!
0.0005 E ~
//
/
f.--'"" .....................
0.0004
0 .-~ 0.0003
/
ffl
FOND .....
0.0002
0.0001
I
i
f
0.05 0.1 0.15 Short Channel Roll-off [V]
0.2
Fig. 6. Simulated saturation drain current at Vd = 3.3 V, V = V,h + 2.5 V as a function o f short channel roll-off (defined by the difference between V,h at given gate length and long channel V,h). The parameter changed in simulation was the poly gate length. The solid line shows the result for LATID, dashed line is used for the F O N D results.
M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
73
of ADEQUAT which allows to calculate hot-carrier device degradation self-consistently can be of significant benefit for this purpose, in articular in the case of state-of-the-art device concepts where a large number of process parameters has to be optimized.
4. Hydrodynamic simulations of FOND structures Within the ADEQUAT Project, the emphasis is on development of CMOS technology which satisfies a series of specifications on reliability, speed, drive voltages and others and, moreover, this technology should be manufacturable with sufficient yield. This combined set of requirements puts strong demands on the transistor architecture. Therefore, within ADEQUAT a serious amount of resources is allocated to explore various transistor architectures and, from the modelling point of view, the emphasis is on a detailed understanding of the various device concepts and moreover to use this as a starting point for performing studies of yield optimization. Such a task setting naturally divides itself into three subtasks: first of all, a choice must be made of the tools which will be used for performing the simulations of the devices, in order to "look into" the devices; secondly, once the tools have been selected, a calibration task starts; finally, using the calibrated simulators, the optimization of the next generation of devices can be initiated. The choice of tools is strongly influenced by the capability of including the advanced structures into the simulators. Unfortunately, standard tools lack the sufficiently advanced physical models which are believed to be important for the device structures which have been suggested within the Project. Therefore, a necessary condition for the tools is to have access to the source codes of the tools in order to include the modifications needed for the simulation of new architectures. Within a Project of the size of ADEQUAT it is also important that data exchange between the various sites is done in a common format. These two conditions have led to work within ADEQUAT with the STORM software as a basis for process simulation, with HFIELDS (which has a smooth interface to STORM) for device simulation, as well as MINIMOS and NORMAL/DEBORA for the optimization based on response surfaces (RSM) constructed by a design of experiment (DOE) approach. The next step, being the calibration of the various tools, is a very tedious and difficult task. The reason is that we may not allow for a too-big discrepancy between the generation of technology that we want to use for calibration and the generation for which we want to optimize the process flow. Within ADEQUAT, we have followed the relations 0.50 i.Lm-calibration
~
0.35 p~m-optimization
0.35~m-calibration
---> 0.25 ~m-optimization
and next
The first step has been partly covered during the first phase of the Project. Most of the effort of IMEC within modeling has been allocated to the 0.35 i.Lm-device calibration. We will present here the present status of this work. In particular, we use the FOND devices which have been extensively characterized as the experimental basis for the calibration. The simulation of the FOND structures has confronted us with the problem of using process simulators which are not fully equipped for the task that is required. In particular, the implantation through the thick multilayer system, poly and SiO z needed considerable adaption of the implantation parameters. The change accounts for the grain size in the poly layer as well as the crystal orientation of the grains. Furthermore, the lateral straggling in silicon has also been changed.
74
M. Rudan et al.
Microelectronic Engineering 34 (1996) 67-84
,
.
.
.
.
i
.
.
.
.
!. O.
I.
P-
3.
VG
Fig. 7. The las-V~s characteristic of the 0.35 txm FOND structure at Vd~ = 0.1 V. The crosses ( × ) are the experimental results.
In Fig. 7, the/d,-Vgs characteristic is shown for Vds = 0.1 V. The crosses ( × ) are the experimental results from the 0.35 Ixm FOND devices processed at IMEC. The full line shows the simulation results using the default settings of the implantation parameters and the dashed line represents the simulation result after calibration, i.e., using adjusted implantation parameters. It should be emphasized that in present technologies, the constraint on the termal budget is severe, which implies that all ramping steps have to be included in a realistic way. The assumption that the anneal steps wipe out transient effects is not valid at all. Using the improved process simulation for the FOND devices we can now have a look inside the devices and find the hot spot(s). In Fig. 8 part of a device
I
|
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.
.
.
.
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.
.
.
.
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.
.
.
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!
.
,
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.
,
,
Fig. 8. Location of the hot spot removed from the spacer edge.
M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
75
in the drain region is shown for Vg.~= 1.1 V and Va~,= 2.5 V, which corresponds to the values for which a maximal substrate current is found. The figure shows the location of the hot spot removed from the spacer edge. Furthermore, the amount of hot-carrier generation is much less, than for conventional LDD structures with comparable dopant distributions.
5. Determination of the series resistance and effective channel length from one single or set of submicron MOSFETs The new method described here only needs one single MOSFET to measure (a) the series resistance as a function of the gate and drain bias, (b) the ratio of the intrinsic conductances, and (c) the mobility-degradation coefficients. In [1] already such a method was presented to measure Rserie~ as a function of gate bias. However, due to some inaccuracies inherent to the method incorrect results can easily be obtained [2], which are still valid despite recent improvements [3]. The new method of TUE measures the conductance and transconductance as a function of externally added resistance as a function of the terminal biases. Next, the derivatives of the series resistance with respect to bias are obtained from these measurements. Integration of the derivatives yields the series resistance. So our method "measures" the series resistance by distinguishing between the intrinsic and extrinsic behavior of the device and is therefore not limited to MOSFETs only. In addition using our method, compact model parameters such as the gain factor /3 and the mobility reduction coefficients are obtained, independently from the series resistance. In Fig. 11 the measured increase of the drain series resistance Rdr~o is plotted as a function of drain bias at various values of gate bias. In comparison with our earlier results [4], the new method is also able to measure the drain series resistance in saturation as shown in Fig. 9 where measurement results are compared with theoretical results (dotted line). In this case Ror~, is plotted as a function of the bias across the resistance. The same method is used to determine R s e ~ as a function of the gate bias at low drain bias. Since we can measure the ratio of the intrinsic conductance and transconductance (Fig. 12) we are able to determine the bias across the intrinsic MOSFET and thus also the value of R~e~(V~,). In Fig. 13 a measurement example is given where the results are compared with results of another method [5] where a set of MOSFETs is needed to determine R~e~ie~(Ve).
2000
0.50
1000
\'v.i!! " °'
rr
|
0.40 0.30 0.20
n-
100
II re.
0.10
'
50
0.00 2
3
4
fi
6
vg (v) Fig. 9. Series resistance, c h a n n e l resistance and their ratio for an N - c h a n n e l L D D M O S F E T as a function o f the gate bias (Lt~ = 0.25 Ixm, W~, = 10 Ixm, V,~, = 100 mV).
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
76
b41D
W,
glD
!. Lm
I
(I)
4D-~ LU
|
Q m bin (V)
I" ILm
1JJ
t.N
LID
(b)
"
(c)
n
Vo (V)
I"
I1~
LM
v, (v)
I1~
(cO
~
1.18
ILm
v,
Fig. 10. (a) Drain current as a function of drain bias and (b, c, d) the derivative of the drain series resistance with respect to the drain bias and increase of R d as a function of the drain bias. The value of gate bias is 4, 5, and 6 V, respectively (W,, = 2 i.Lm, L,, = 0.70 Ixm).
We also have been able to model the series resistance in the full bias range using only five additional parameters. Since according to two-dimensional device simulations the main current path in the junction is near the interface, as illustrated in Fig. 14 where the dissipation in the MOSFET is plotted, the gate-bias-dependent part of Rseries (at low drain bias) can be modelled as a sum of two accumulation resistances in parallel with a sheet resistance. The increase in Rdr~in is mainly due to velocity saturation resulting in a linear increase of Rdrai n with the bias across this resistance, as shown in Fig. 10. Momentarily results show that by the inclusion of a compact bias-dependent series70O
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.M,
~
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,
0 0.00
r""
.~
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I
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0.40
V~l (V) Fig. l 1. Measured drain resistance at several gate biases as a function of the bias a c r o s s
Rdrai n ( W
= 2 txm, L,, = 0.70 ~m).
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4 o
o
,%
O.
*
77
~,
1.111
(II ~
1.1o ~
~
1.o6
+
1.00
4
0
V o (Volt)
Fig. 12. Ratio of the measured intrinsic conductances as a function of the gate bias at Va=0.10V (14/,, = 10txm, L,, = 0.80 ~m and to+ = 175 A). The solid line has been calculated according to our model. 8OO A
| n-
IE
m
(s)
100 i
50 2
6
4
8
v o (v) Fig. 13. The measured MOSFET total resistance and series resistance as a function of the gate bias at Vd =0.10V ( W = 10 I~m, L,, = 0.80 ~m). The series resistance curve (A) is the determined series resistance using a set of identical MOSFETs, curve (B) is derived from the single transistor measurement technique.
1.50e+1 2
'•
1.20e÷12
0.00e~11
'"'
/L.
'~ o.oo=.,.oo . o . 1 ~ o . 2 4"
o.ao'~
~,,#j....
°
~
o.1t
o . 7 o ~
o.u ,,i k.+~'~
Fig. 14. Local heat dissipation for n-channel device. The gate lies between x = 0 and x = 0.6 I.tm. As expected, the dissipated heat peaks near the interface.
78
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
resistance model in a compact MOSFET model, better physically-based parameters are obtained together with a slight increase in accuracy.
6. Compact MOS models
6.1. The effect of process variations on compact model parameters From the statistical analysis of a large number of batches of the Philips CMOS production process it was found that the spread in threshold voltage was indeed larger for p-channel than for n-channel devices. However, for both n- and p-channel devices the simulated spreads are larger than the measured ones. Also the simulated spreads in gain factors of both n- and p-channel devices are larger than the experimental values obtained from the statistical analysis mentioned above. By fitting the spreads, simulated for threshold voltages and gain factors, to the values experimentally observed, new realistic spreads in the process variables have been obtained. The distributions for threshold voltages and gain factors have been calculated with these spreads. The distributions for the gain factors are shown in Fig. 15 for n channels and in Fig. 16 for p channels. It should be noted that with the new spreads in the process variables mentioned above, the spreads in the threshold voltages and gain factors of both n- and p-channel MOSFETs are predicted with good accuracy. Using these spreads, the correlation coefficients for the threshold voltages and gain factors of both n- and p-channel MOSFETs have been evaluated. The correlation coefficients between two sets x~ and yi is given by N
Z i : 1 x i Y i --
Rxy --
N~37
(3)
Ntrxtry
where N is the number of values in sets x i and Yi, f, and 37 are the averages of the sets xi and Yi, and o-x
N-channel
.-r_
t-J
o ¢-L
0.130
0.145 0.160 (uA/V=~
beta
Fig. 15. Simulated statistical distribution for the gain factor of the n-channel transistor.
M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
79
P-channel
la.,
cl a~ o I.
0.034 beta
0.038 0.042 (/.LA/Y')
Fig. 16. Simulated statistical distribution for the gain factor of the p-channel transistor. and O-y are the spreads of the sets x i and Yi. By way of example, the correlations between gain factors are shown in Figs. 17 (experimental) and 18 (calculated). All plotted values have been centered around the mean value and normalized to the corresponding spread. 6.2. Evaluation o f commercially available M O S F E T models
BSIM3 is the latest in a series of models for submicron MOSFETs developed at the University of Berkeley and available in the popular IC simulation program SPICE. It is version 2 of the model [6] (referred to as BSIM3V2) which is discussed here. At NMRC, BSIM3V2 model sets have been extracted from an array of 14 NMOS devices of size ranging from 10 Izm/10 I~m to 1 Ixm/0.8 I~m. To investigate the scaling properties of the model both single-device and geometry-independent parameter sets were extracted. The single-device parameter sets were extracted from one device at a time whereas the geometry-independent parameter set was extracted to fit all 14 devices simul-
experimental •
,~ao
:
~:'.~'z'i~" "• •
f~o oO ° "A;''
•
• t~... ,~.. -3'
""
0
"
"
3
8o Fig. 17. Experimental correlation between the gain factors of the n- and p-channel transistors.
80
M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
calculated
~p
-3
0
3
#. Fig. 18. Calculated correlation between the gain factors of the n- and p-channel transistors.
taneously and is the model set which would be used for design purposes. The single-device models give good prediction in all cases but the geometry-independent models show a degraded performance in some regions. Figs. 19 and 20 show measurements and simulations (with the geometry-independent model) for the 10 Ixm/0.9 Ixm device. In general the current and output conductance prediction is good but the gas curve at low Vgs shows that a negative g,,,+ can sometimes be predicted by the model. Figs. 21 and 22 show the variation of threshold voltage and one of the substrate current parameters (PSCBE2) with length for both the single-device and geometry-independent parameter sets. It is seen
N10/0.9
0.0050~ ta v . b = 2 v 0.0040
__
v.
[-o v,,, = 5 v . . c ~ e ~ ~
5V
,._, 0 . 0 0 3 0 "
3.5
0.0020
0.0010 ~~AAAAA--A_=_~=_A_A_aAaA 2 V ~
A
v
=
~
o
o
o
0
0
o
o
o
o
o
o
o
o
'~gQv
_
0.0000
_ _
0.06
0
1
2
,.3
4
5
6
Vd, (V) Fig. 19. l0 Ixm/0.9 Ixm NMOS-BSIM 3V2 ids (left) and gas fit. Here the BSIM 3V2 model predicts a negative gd~ at low
v~. v+.
M. Rudan et al.
10
10
.-..
10
-2
-3
Microelectronic Engineering 34 (1996) 67-84
81
N10/0.9
I
' I ' ' ' I ' ' ' I ' '
' I ' ' ' I ' ' '
[] Vmb = 0 V
I~11~
A Vib = 2 V
0 V.b = 5 V
-4
5V
a
r~
10-5 O 10 -6
-
10 - 7
/'-'uooooooooooooooOOO° °0"86V ,i,, i,.,
0
1
i,,,
i,,,
i,,,i,.,
2
.3
4
5
6
v,, (v) Fig. 20. BSIM 3V2 scaling: the square shows values for V., (left) and PSCBE 2 for individual transistors; the solid lines show the values used in a geometry independent model.
that the scaling rules in the model give good prediction of V,h vs. length but do not allow a variation of PSCBE2 with length as happens in practice. Overall, BSIM3V2 is an improvement over previously available public-domain models but suffers from some discontinuity problems (as illustrated in Fig. 20) and would benefit from some extra scaling parameters (as illustrated by the plot of PSCBE2). It is hoped that these issues will be addressed in the next version, BSIM3V3.
0.90
....
I ....
I '
'~'
1 ....
0.85 -o
0.80
0.75
0.70 0.0
....
i .... 0.5
I .... I .0
~ .... 1.5
2.0
1/L.. ( 1 / ~ ) Fig. 21. Variation of threshold voltage with length for both the single device and geometry independent parameter set.
82
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4 25
'
2O
"(3
'
'
'
1
. . . .
I
. . . .
[
. . . .
I~ ~5
fl
r~
5 o
.... o.o
1,1t,1
J . o. . .
, .... 0.5
r,,:
1 .o
2.0
1.5
l/L.,, (1/~,m)
Fig. 22. Variation of one of the substrate-current parameters (PSCBE2) with length for both the single-device and geometry-independent parameter set.
7. Validation of T C A D tools on a 0.5 lutm N M O S transistor
The NMOS device 3 under consideration at GMMT consisted of a B high-energy implanted and diffused p well in a p epitaxial layer on a p substrate; a POC13 doped polysilicon gate with as drawn 0.55 Ixm gate length; and Double Diffused Drain (DDD) A s / P source/drain (S/D) architecture. The final simulated device structure and doping are shown in Fig. 23. The process simulation was optimized to achieve target parameter values for the metallurgical Left; saturation current (at --
+
I
'
'
'
l
l
l
l
1
l
a
l
l
l
l
l
l
,
l
l
I
l
I
l
tmC,h ( u m ) Fig. 23. n-MOS device structure and doping.
3 The device was designed, processed and measured by GEC Plessey Semiconductors; data supplied by courtesy of B.S. Bold.
M. Rudan et al. / Microelectronic Engineering 34 (1996) 6 7 - 8 4
Model ......N o r t h .....C e n t r e
6-
83
..............
4-
2-
.
0
1
2
3
.
.
.
4
VDs (V)
Fig. 24. n-MOS output characteristics. V~ = V~ = 3 V); and VT. Acceptable agreement was obtained for these primary device parameters using the standard STORM models throughout, except for the S / D where it was necessary to use the advanced M M G level of coupled dopant point-defect diffusion. It was important to model all thermal ramps and low temperature anneals; these had a significant effect on the dopant profiles and activation. The only significant difference with the device layout and process flow was that the drawn gate length had to be increased by 0.05 Ixm, in order to obtain the correct Leef value. The error is thought to be due to overestimation in the implant model prediction of lateral straggle of the As and P at the polysilicon gate edge. The asymmetry between source and drain contours is caused by a 7 ° tilt in the As ion implantation assumed to be in the plane of the device (zero rotation). The substrate current in a short channel MOSFET is substantially overestimated by the standard impact-ionization model in a drift-diffusion model (such as in HFIELDS) because of fast variations in
-400,
--Model ......N o r t h .... C e n t r e -
:t ~-~ - 2 0 0 -
-100-
1
2
3
4
v o (v) Fig. 25. n - M O S
substrate current versus gate bias for fixed V#,.
84
M. Rudan et al. / Microelectronic Engineering 34 (1996) 67-84
the electric field. The hydrodynamic model gives a better estimate of substrate current since it uses the carrier temperature to estimate the carder energy distribution which then determines the impactionization generation rate, as in the model of Quade and Rudan implemented in HFIELDS-hydro [7]. In the simulation care was taken to achieve a sufficiently fine mesh and bias-step increment to ensure a numerically accurate solution. Due to some convergence difficulties experienced with the first 4 release of HFIELDS-hydro much user intervention was necessary to tune this strategy. Measurements were taken at two sites (N, C) on the wafer, having nominally the same drawn poly gate length of 0.55 Ixm, to assess wafer variability. The agreement in Vr was better than 0.04 V. The saturation current at Vd = Vg = 3 V was simulated as 5.42 mA, compared to 5.38 mA averaged over the two sites measured. The complete (/d, Vas) characteristic for a 15 lxm wide device is shown in Fig. 24 for a full range of gate biases. It can be seen that the model fits well within the range of measurements obtained from different sites on the wafer. The substrate current for the same devices is shown in Fig. 25. The peak value is slightly larger and occurs at a higher gate bias in the model than in the measurements. The agreement is excellent when compared to the drift-diffusion model which over-estimates I~ub by two orders of magnitude in this case. In order to investigate the process sensitivity and also the discrepancy in the modelled voltage bias at which the peak substrate current occurs, several model variations were investigated. Reversing the direction of As tilt, and hence S / D of the device, gives a reduction in/sub by ×0.25, this is due to the shape of the 2D drain. The location and temperature of the hot carders strongly affects the impact-ionization generation. The S/D activation level depends upon the final anneal temperature. Although a high activation level is achieved for high temperature RTA, this can be reduced by low temperature post-processing in which a fraction of the As can become non-substitutional. However, the S/D activation had only a small effect (2%) on the drain current.
References [1] [2] [3] [4] [5] [6] [7]
L. Selmi, IEEE Trans. Electron Devices 36 (1989) 1094-1100. J.A.M. Otten and F.M. Klaassen, In Proc. ESSDERC, 1991. L. Selmi et al., IEDM 94 Technical Digest (1994) 471-474. J.A.M. Otten and F.M. Klaassen, Proc. ESSDERC, 1992. J.A.M. Otten and F.M. Klaassen, to be published. J.H. Huang et al., BSIM3 Manual (version 2). Technical Report, University of California, Berkeley, CA, 1994. W. Quade, M. Rudan, and E. Sch611, Hydrodynamicsimulation of impact-ionization effects in p-n junctions, IEEE Trans. on CAD of lCAS 10 (10) (1991) 1287-1294.
4 The robustness problem has been traced back to the organization of the internal loops used in connection with current generators, and is eliminated in the present release.