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Direct-coupled high speed adder by using Josephson junction
This paper presents the latest design work of high speed adder logic based on Josephson elements. The Josephson adder uses a novel exclusive-OR logic and performs high speed carry propagation technique. The idea of directionality is also undertaken to avoid the necessary distortion in carry signal. The principle o f operation with salient feature o f simulation of the adder are presented in full detail. Necessary checks for carry skip and other fabrication parameters are investigated using detailed model of the device based on its highly miniaturized size. The results of the simulation show that the nominal delay of the adder logic is 20 ps/stage and average power dissipation is 47 llW/stage. Authors have mainly stressed upon how to obtain ultra fast speed at the cost of very/owpower dissipation of the presented adder with its small size.
Direct-coupled high speed adder by using Josephson junction M. Morisue, H. Matsuo, K. K u r a m o c h i and Z. Hussain Shaikh Key words: superconducting devices, Josephson junction, adder
In the last decades, researchers have shown profound interest in the development of Josephson technology. Recently, Josephson circuits have been studied in depth and have shown tremendous capacilities of ultra high speed operation with remarkably low power dissipation) So far many Josephson logic adders have been proposed for various digital appfications by connecting into logic circuits. Therefore it is the circuit stages, wiring connections with other components make the entire circuit complex, which causes a great setback, to the operational speed of the logic circuit. ~ In this paper, a high speed Josephson adder using a novel exclusive-OR logic and high speed carry propagation technique, and the computer simulation of the adder using the Josephson Tunnelling Logic (JTL) gate are described. 3 The model for the simulation of the distributed parameter network is composed of lossless transmission lines and nonlinear active elements of JTLs. Some unique features of the present adder circuit are as follows: A high speed carry propagation technique is introduced to issue the carry signal, immediately when the condition to generate the signal is met at any stage. This reduces the total calculation time of the CPU to a half of the time required by ordinary ripple-carry technique.
As the speed of the logic element in the circuit is high, the circuit must be treated as transmission line networks. Detailed phenomena like reflection, distortion, absorption, rise and fall time of the signal would be neglected, when the line was treated as lumped circuits. Therefore we will obtain more accurate results by modelling the logic circuit as a transmission network. Interchip connections can be treated as transmission lines in the logic circuits of the computer, so as to avoid distortion in the signal and take into consideration propagation delay time along the line. The similar technique of modelling could be applied to the analysis of the Josephson logic systems. Principle o f operation
In order to investigate the operation of the adder, its nth stage is considered. Fig. 1 depicts the construction of the adder, where Xn and Yn are binary inputs of the nth stage, Jnl denotes Josephson Exclusive-OR, Jn2 threshold logic for the carry, Jn3 Josephson Exclusive-OR for the sum, Cn-i the carry from the preceeding stage, Cn the carry signal for the nth stage, E n is the bias pulse which produces a current below critical value of the Josephson junction. Cn - I
In circuits developed so far, the output current of the junction is not applied to the gate at the next stage directly, but in the present circuit it is so. This also lessens the total turn-on delay time for the element, because we can directly overdrive the junction and can bypass the delay time factor associated with the magnetic flux in the inserted inductance in order to have a directionality of the signal.
i ~ £-n3Sn Cn
Exclusive-OR function can be performed in one step by using only one element of the Josephson junction, therefore the size of the circuit is reduced and the operating speed is remarkably improved. The authors are at the Department of Electronic: Engineering, Saitama University, Urawa, Japan, KK is currently employed with Tokyo Sanyo Electric Co. and ZHS from Sind University, Institute
of Physics and Technology, Jamshoro, Pakistan, is presently researching in Saitama University. Paper received 4 January 1982. 0011-2275/82/009461-05 C R Y O G E N I C S . SEPTEMBER 1982
%
Xn
Yn
Fig. 1 Construction of a direct-coupled high speed adder using a Josephson tunelling Logic gate
$03.00 © 1982 Butterworth & Co (Publishers) Ltd. 461
,Ig
/
I
I
I
...... 0
-~A I
a ~ x : , , Y:o "N~v ~c,-,:'. c,.,=o
I
o'~-.--
X____.~~ I,Y=0 --_~ _l=O,Cn÷l=O zo
for the sum, Cn-1 the carry from the preceeding stage, Cn the carry signal for the nth stage, E n is the bias pulse which produces a current below critical value of the Josephson junction. When Xn and Yn are applied to the adder, the junction Jnl switches to non.zero voltage state, because the current through the control line of Jm by either of the inputs produces magnetic fluxes in the junction sufficient to reduce the critical current below the value of the gate current. The further operation of exclusive-OR can be understood from the threshold characteristics of the Josephson junction as shown in Fig. 2. Considering 0 as initial operating point on gate current axis moving between 0 and A or 0 and B for either of the inputs Xn and yn, either of the input develops the voltage across the junction and in turn produces output signal Z n. If both inputs are applied, Jnl will be held in the superconducting state (V = 0) because the magnetic fluxes produced by inputs will be cancelled out. Thus the operation of the exclusiveOR logic is achieved with single Josephson junction. Similiarly JTL gate Jn3 performs the operation of the exclusiveOR logic for the two signals Cn-1 and Z n (output). IfJns switches to the V 4= 0 state, Jn3 drives the superconducting transmission line to generate the output voltage across the load resistance RL3 corresponding to the sum signal Sn of the adder, as represented in the foUowing equation. Sn = Xn (9 Yn (9 Cn_l
o
z~
Fig.2 Threshold characteristics of a Josephson junction for exclusive-OR logic operation
Fig. 3 Threshold characteristics of a Josephson junction showing the operation of direct-coupled high speed carry propagation circuit
simultaneously. When X n 1 and Yn = 0, the current flows through the control line and produces the flux shifting the operating point 0 to B'. When the carry signal from the next stage Cn+l = 1 is applied, the flux will be produced but in the opposite direction so as to compensate the previous flux. This will shift the operating point B' to the original position 0 and then the gate current, by the carry signal, will increase as indicated by point C in Fig. 3. Now consider the 0 to D operation. The carry signal Cn + 1 = 1, when applied to the circuit, produces the flux and makes the operating point shift from 0 to D' and then this current also causes an increase in the gate current as shown from the point D' to D". When the carry signal Cn_ 1 = I, from the previous stage is applied, this causes a further increase in the gate current and the operating point shifts from D" to D, with this condition the Josephson junction will still stay in the superconducting state. =
Thus the directionality of the direct-coupled carry propagation circuit using Josephson junction can be obtained. This simple construction of the circuit helps in achieving a high speed adder.
(1)
To have faster operational speed of the adder, consider propagation delay time for the carry from the first to the final stage of the adder. The carry affects high speed response of the Josephson element at all stages. 3 Whenever the condition to generate a carry signal at any stage in the circuit is met, the carry is immediately issued without receiving the carry from the preceeding stage. This condition is explained by the circuit using the JTLJn2 in Fig. 1 with two control lines. Now consider Fig. 3 showing the threshold logic for generating the carry signal. When both inputs Xn = ]In = 1 are applied without any previous or next carry, the operating point 0 moves to A which is V=/=0 state. When Xn = 1, Yn = 0, Cn-l = 1 and Cn+l = 0, the operation 0 to B is performed, which causes a forward current in the circuit to produce the carry Cn. To know the directionality of this circuit and to avoid the backward effects, a control line into the transmission line is introduced. For 0 to C operation for which Xn = 1, Yn = 0, Cn-1 = 0 and Cn+l = 1, consider the circuit shown in Fig. 1 and the graph in Fig. 3
462
/
x=o,Y=O Cn_l = I C.÷,=l
D"t
-Tx
f~ CX=l,Y=O n _ I =0, C n . ~: [
k,2
Zk-,,I
Q
| /
)
Jk,t
k ~/ /
ek'ltl
~
Q fk
)
ek*l
Fig. 4 Basic model of the distributed parameter network for simulation of the Josephson high speed adder
CRYOGENICS.
SEPTEMBER
1982
Computer aided analysis in transmission lines
0<
i = V/R1
I V I < Ve
10
Fig. 4 shows the basic model of the network for the adder with an equivalent circuit of Josephson element. For this network consider a node K at which biasing voltage E k is applied through resistance R k. The length of transnfission lines hanging at K are represented by lk-l,1, lk,1 and/k,2 where K - 1 and K + 1 represent the node of the preceeding and next stage respectively. Here equations for the lossless transmission lines are shown as follows, in which ek, 1, and ik, are the line voltage and current, Lk, 1 and Ck,~ are the inductance and capacitance of the unit length of line respectively, x and t are the distance and time from the node.
aek, l(x, t) = --Lk, 1
i : V/R 2
From (1), we obtain
The node voltage can be calculated in E k, Rk, rk and Vk are known in the following equations.
(t) +Gk,1
Ik,1 gk, 1 , \
lx=O _=ik,l(t)= "
Fk,l(t)_Gkalt_lkj ) '\ Uk, l
1 Zk,1
(3) where Uk 1 = 1/(LK 1" Ck 1) ~ is the speed of wave less than that of light. Zk, 1 =' (Lk#/Ck, 1)'/~ the impedance of the transmission line, Fk, 1 and Gk,1 the forward and backward voltages from the node. Furthermore the relationship between voltage and current at the node can be shown by
eK,z(t)=FK,z(t)+GK, z (t
UK,p/K'2)
(4) \
FK,2(t)
eK_L1 (t) =FK_I,1(t (t)
-
1
ZK_IA
(1 1)
[IEk(t)--ek_l(t)l/Rk+ik_l,l(t)
ikj(t)
--ik,2(t)] " rk + Vk(t)
(12)
Algorithm
ek, l(x, t)Ix= 0 =ek, l(t) =Fk,
iK-I,1
Vc< IVl
From above analytical analysis ek, l(t) and ik, l ( 0 can be found at any time if Fk, 1(t) and Gk, 1(t) are known.
at
! iK,~ (t) = ZK,2
(10)
where R1 and R2 are the resistance for the region of lower voltage Ve and higher voltage Vc as shown in Fig. 7 respectively.
(1) Oik, 1 (X, t) __ _Ck, 1 Oek, 1 (X, t)
ek, l(X' t)
lie < [ g l < Vc
it=0
ek,l(t)=
Ot
OX
a,V ~
ek, x(t) : ek_ 1,1 (t) = ek, 2 (t)
Oik,1 (X, t)
OX
i = ~
- GK,2 l\t -
lK-1,1 UK_I,1
FK_I,1
)
UK,IK'2rl2
+ GK-I,1 (0
(5)
Basic flow chart for the computer simulation defines the step-wise algorithm. In this chart the data can be read from the card. Step 1 : the data R (resistor), L (inductance), C (capacitor), Z (impedance), T (end time of simulation) and so on are read from the card. Step 2 : voltage, current, forward and backward waves are calculated from the initial conditions in the first step. Step 3: Ig (gate current) and Vk (gate voltage) can be calculated with the help of equations as described before. Steps 4 and 5 : the calculations for F k and Gk, e k and ik are made with the help of set of equations as explained in computer-aided analysis in transmission lines based on fundamental theory. Finally we have to check whether simulation time has ended or not.
(6)
(7)
/
I
the current away from the node. For the Josephson junction, we have two fundamental differential equations
+ Vk(t)/R(Vk) + Jok sin 0 (t)
Initi°l c°nditi°ns
..J
where ek_l, 1(t) and ek, 2 (t) represent the voltage at node K, ik-l,1 (t) is the current towards the node, and ik,2(t) is
Step 3
The unknowns in lumped circuits ore determined
Step 4
Forword ond bockword woves ore obtoined
Step 5
Line voltages and line currents ore colculoted
(8) (9)
where Igk(t) is the gate current, Vk(t ) is the voltage across junction, Ck is the capacitance of the junction, Jok is the critical current and 0 is the phase difference between two superconductors of junction, R(Vk) is the non-linear resistance of the junction when it switches to the voltage state. The resistance is obtained from the V-I characteristics of the junction, where the tunnelling current and quasi-particle current flow. This V - I characteristic is represented in the following mathematical terms.
CRYOGENICS. SEPTEMBER 1982
I Step 2
UK-I,1
- aK_l,, (t) /
dO(t)/dt = 2e/h Vk(t)
I
I
\
Igk(t) = C k " d Vk(t)/dt
( Step ea 0a,o _
Fig. 5
Flow chart for the computer-aided
calculation
463
Table 1.
Truth table for the simulation
~-~ 3.6 V
Input Xn
Yn
Cn-I
Output Sn
Cn
a
1
1
1
1
1
b
1
0
1
0
1
c
1
1
0
0
1
=, 1.2V
1.2V
8
Computer simulation
[o+° I
Computer simulation is made to check the operation of the model representing an adder in distributed parameter network as shown in Fig. 6. The equivalent circuit and I - V characteristics curve of the Josephson junction are shown in Fig. 7. The basic equations describing the model are shown by the simultaneous partial differential equations with non-linear boundary condition of the junction, which cannot be solved analytically. Therefore these equations can be transformed into differential difference equations suitable for digital computation. These equations have already been discussed in computer aided analysis in transmission lines.
"0.5
0.5
Fig. 8 (a), (b) and (c) show current-time characteristics of the simulated operation of the adder, for which the truth table is also given in Table 1. It is very clear from Fig. 8 that the carry C n can be generated immediately without receiving the preceeding carry when X n = Y n = 1. The bias pulse is not supplied to the junction until the inputs X n and Y n are applied. Therefore both inputs need not to be absolutely coincident. Furthermore, if the bias voltage and inputs are applied at the same time, even then, the result will not be affected.
Fig. 6 Equivalent circuit of the high speed adder, consisting of JTLs and Iosslesstransmissionlinesfor computer simulation
-- - I ~ - - - - -
I
Ve
Y
The simulation results show that the delay time of the adder is 20 ps/stage and power consumption is 47 #W/stage which means the adder with 32 bits is able to operate with delay of less than 320 ps and 1.5 mW power. This simulation also shows an impressive result that even if some parameters in the network model are changed such
vc
b Fig. 7 a - Equivalent circuit of the Josephson junction for the simulation, b -- nonlinear current-voltage characteristics of a Josephson junction
0
I
0
f
E
I
I
I
S
0
E
Sn 0 co
E 0
a Fig. 8
#
k .........,50
~o
,oo ..... Ps
o
b
S
,L................ ,50
~o
,oo Ps
o C
;
;
5'o
Jo'
............
,,o
Ps
Results of the computer simulation for the circuit as shown in Fig. 6, showing how the operation of the adder is achieved for the Yn=landCn--1 =l;b--Xn=O, Yn=landCn--1 =l;c--Xn=l, Yn = l a n d c n 1=0
following three states of the s i g n a l s : a - - X n = l ,
464
C RYOG EN I CS. SEPTEM BE R 1982
Although the adder described here is constructed by using the Josephson Tunnelling Logic gates as an example, this system may also be implemented with interferometers or current injection logics. 4
2oI 0 041
f ~
Conclusion
0
ooi :
L_
0~
The design of a novel adder by using the Josephson junctions is proposed. The principle of operation, computer aided analysis in transmission line and simulation of the adder is made. The unique feature of directionality is discussed in detail. Further application of the technique is proposed for network transmission lines. Changing the value of a parameter in the model such as resistance will not cause any effect on reliable operation of the adder. Finally this paper suggests that the adder with 32 bits will be able to operate in a shorter time than 320 ps.
o,I O0
50
IOC)v%';';'--..... ISO Ps
Fig. 9 Resultsof the simulation in the caseof changing s o m e circuit parameters by about 17% in the circuit as shown in Fig. 6, which indicates that no peculiar effect is produced on the smooth operation of the adder
as resistances from 6 f2 and 8 ~2 to 5 f2 and 6.7 ~2 respectively, the operation of the adder in Fig. 9 does not show any unstable behaviour.
CRYOGENICS. SEPTEMBER 1982
The authors would like to express their appreciation for kind guidance of Professor Y. Komamiya, and thank Mrs Y. Kaminuma and Mr H. Tsuchida for their help to prepare this paper. The authors acknowledge supports from ministry of education of Japanese Government under the special research project on 'Superconducting Quantum Electronics' for this work. References 1 2 3 4
Matiso, J. IBMJR&D 24 (1980) 113 Herrell, D.J. 1EEE Trans Mag MAG-10 (1974) 864 Zappe, H.H. JApplPhys 44 (1973) 1371 Gheewala,R.IL IBMJR&D 24 (1980) 130
465
Direct-coupled high speed adder by using Josephson junction M. Morisue, H. Matsuo, K. K u r a m o c h i and Z. Hussain Shaikh Key words: superconducting devices, Josephson junction, adder
In the last decades, researchers have shown profound interest in the development of Josephson technology. Recently, Josephson circuits have been studied in depth and have shown tremendous capacilities of ultra high speed operation with remarkably low power dissipation) So far many Josephson logic adders have been proposed for various digital appfications by connecting into logic circuits. Therefore it is the circuit stages, wiring connections with other components make the entire circuit complex, which causes a great setback, to the operational speed of the logic circuit. ~ In this paper, a high speed Josephson adder using a novel exclusive-OR logic and high speed carry propagation technique, and the computer simulation of the adder using the Josephson Tunnelling Logic (JTL) gate are described. 3 The model for the simulation of the distributed parameter network is composed of lossless transmission lines and nonlinear active elements of JTLs. Some unique features of the present adder circuit are as follows: A high speed carry propagation technique is introduced to issue the carry signal, immediately when the condition to generate the signal is met at any stage. This reduces the total calculation time of the CPU to a half of the time required by ordinary ripple-carry technique.
As the speed of the logic element in the circuit is high, the circuit must be treated as transmission line networks. Detailed phenomena like reflection, distortion, absorption, rise and fall time of the signal would be neglected, when the line was treated as lumped circuits. Therefore we will obtain more accurate results by modelling the logic circuit as a transmission network. Interchip connections can be treated as transmission lines in the logic circuits of the computer, so as to avoid distortion in the signal and take into consideration propagation delay time along the line. The similar technique of modelling could be applied to the analysis of the Josephson logic systems. Principle o f operation
In order to investigate the operation of the adder, its nth stage is considered. Fig. 1 depicts the construction of the adder, where Xn and Yn are binary inputs of the nth stage, Jnl denotes Josephson Exclusive-OR, Jn2 threshold logic for the carry, Jn3 Josephson Exclusive-OR for the sum, Cn-i the carry from the preceeding stage, Cn the carry signal for the nth stage, E n is the bias pulse which produces a current below critical value of the Josephson junction. Cn - I
In circuits developed so far, the output current of the junction is not applied to the gate at the next stage directly, but in the present circuit it is so. This also lessens the total turn-on delay time for the element, because we can directly overdrive the junction and can bypass the delay time factor associated with the magnetic flux in the inserted inductance in order to have a directionality of the signal.
i ~ £-n3Sn Cn
Exclusive-OR function can be performed in one step by using only one element of the Josephson junction, therefore the size of the circuit is reduced and the operating speed is remarkably improved. The authors are at the Department of Electronic: Engineering, Saitama University, Urawa, Japan, KK is currently employed with Tokyo Sanyo Electric Co. and ZHS from Sind University, Institute
of Physics and Technology, Jamshoro, Pakistan, is presently researching in Saitama University. Paper received 4 January 1982. 0011-2275/82/009461-05 C R Y O G E N I C S . SEPTEMBER 1982
%
Xn
Yn
Fig. 1 Construction of a direct-coupled high speed adder using a Josephson tunelling Logic gate
$03.00 © 1982 Butterworth & Co (Publishers) Ltd. 461
,Ig
/
I
I
I
...... 0
-~A I
a ~ x : , , Y:o "N~v ~c,-,:'. c,.,=o
I
o'~-.--
X____.~~ I,Y=0 --_~ _l=O,Cn÷l=O zo
for the sum, Cn-1 the carry from the preceeding stage, Cn the carry signal for the nth stage, E n is the bias pulse which produces a current below critical value of the Josephson junction. When Xn and Yn are applied to the adder, the junction Jnl switches to non.zero voltage state, because the current through the control line of Jm by either of the inputs produces magnetic fluxes in the junction sufficient to reduce the critical current below the value of the gate current. The further operation of exclusive-OR can be understood from the threshold characteristics of the Josephson junction as shown in Fig. 2. Considering 0 as initial operating point on gate current axis moving between 0 and A or 0 and B for either of the inputs Xn and yn, either of the input develops the voltage across the junction and in turn produces output signal Z n. If both inputs are applied, Jnl will be held in the superconducting state (V = 0) because the magnetic fluxes produced by inputs will be cancelled out. Thus the operation of the exclusiveOR logic is achieved with single Josephson junction. Similiarly JTL gate Jn3 performs the operation of the exclusiveOR logic for the two signals Cn-1 and Z n (output). IfJns switches to the V 4= 0 state, Jn3 drives the superconducting transmission line to generate the output voltage across the load resistance RL3 corresponding to the sum signal Sn of the adder, as represented in the foUowing equation. Sn = Xn (9 Yn (9 Cn_l
o
z~
Fig.2 Threshold characteristics of a Josephson junction for exclusive-OR logic operation
Fig. 3 Threshold characteristics of a Josephson junction showing the operation of direct-coupled high speed carry propagation circuit
simultaneously. When X n 1 and Yn = 0, the current flows through the control line and produces the flux shifting the operating point 0 to B'. When the carry signal from the next stage Cn+l = 1 is applied, the flux will be produced but in the opposite direction so as to compensate the previous flux. This will shift the operating point B' to the original position 0 and then the gate current, by the carry signal, will increase as indicated by point C in Fig. 3. Now consider the 0 to D operation. The carry signal Cn + 1 = 1, when applied to the circuit, produces the flux and makes the operating point shift from 0 to D' and then this current also causes an increase in the gate current as shown from the point D' to D". When the carry signal Cn_ 1 = I, from the previous stage is applied, this causes a further increase in the gate current and the operating point shifts from D" to D, with this condition the Josephson junction will still stay in the superconducting state. =
Thus the directionality of the direct-coupled carry propagation circuit using Josephson junction can be obtained. This simple construction of the circuit helps in achieving a high speed adder.
(1)
To have faster operational speed of the adder, consider propagation delay time for the carry from the first to the final stage of the adder. The carry affects high speed response of the Josephson element at all stages. 3 Whenever the condition to generate a carry signal at any stage in the circuit is met, the carry is immediately issued without receiving the carry from the preceeding stage. This condition is explained by the circuit using the JTLJn2 in Fig. 1 with two control lines. Now consider Fig. 3 showing the threshold logic for generating the carry signal. When both inputs Xn = ]In = 1 are applied without any previous or next carry, the operating point 0 moves to A which is V=/=0 state. When Xn = 1, Yn = 0, Cn-l = 1 and Cn+l = 0, the operation 0 to B is performed, which causes a forward current in the circuit to produce the carry Cn. To know the directionality of this circuit and to avoid the backward effects, a control line into the transmission line is introduced. For 0 to C operation for which Xn = 1, Yn = 0, Cn-1 = 0 and Cn+l = 1, consider the circuit shown in Fig. 1 and the graph in Fig. 3
462
/
x=o,Y=O Cn_l = I C.÷,=l
D"t
-Tx
f~ CX=l,Y=O n _ I =0, C n . ~: [
k,2
Zk-,,I
Q
| /
)
Jk,t
k ~/ /
ek'ltl
~
Q fk
)
ek*l
Fig. 4 Basic model of the distributed parameter network for simulation of the Josephson high speed adder
CRYOGENICS.
SEPTEMBER
1982
Computer aided analysis in transmission lines
0<
i = V/R1
I V I < Ve
10
Fig. 4 shows the basic model of the network for the adder with an equivalent circuit of Josephson element. For this network consider a node K at which biasing voltage E k is applied through resistance R k. The length of transnfission lines hanging at K are represented by lk-l,1, lk,1 and/k,2 where K - 1 and K + 1 represent the node of the preceeding and next stage respectively. Here equations for the lossless transmission lines are shown as follows, in which ek, 1, and ik, are the line voltage and current, Lk, 1 and Ck,~ are the inductance and capacitance of the unit length of line respectively, x and t are the distance and time from the node.
aek, l(x, t) = --Lk, 1
i : V/R 2
From (1), we obtain
The node voltage can be calculated in E k, Rk, rk and Vk are known in the following equations.
(t) +Gk,1
Ik,1 gk, 1 , \
lx=O _=ik,l(t)= "
Fk,l(t)_Gkalt_lkj ) '\ Uk, l
1 Zk,1
(3) where Uk 1 = 1/(LK 1" Ck 1) ~ is the speed of wave less than that of light. Zk, 1 =' (Lk#/Ck, 1)'/~ the impedance of the transmission line, Fk, 1 and Gk,1 the forward and backward voltages from the node. Furthermore the relationship between voltage and current at the node can be shown by
eK,z(t)=FK,z(t)+GK, z (t
UK,p/K'2)
(4) \
FK,2(t)
eK_L1 (t) =FK_I,1(t (t)
-
1
ZK_IA
(1 1)
[IEk(t)--ek_l(t)l/Rk+ik_l,l(t)
ikj(t)
--ik,2(t)] " rk + Vk(t)
(12)
Algorithm
ek, l(x, t)Ix= 0 =ek, l(t) =Fk,
iK-I,1
Vc< IVl
From above analytical analysis ek, l(t) and ik, l ( 0 can be found at any time if Fk, 1(t) and Gk, 1(t) are known.
at
! iK,~ (t) = ZK,2
(10)
where R1 and R2 are the resistance for the region of lower voltage Ve and higher voltage Vc as shown in Fig. 7 respectively.
(1) Oik, 1 (X, t) __ _Ck, 1 Oek, 1 (X, t)
ek, l(X' t)
lie < [ g l < Vc
it=0
ek,l(t)=
Ot
OX
a,V ~
ek, x(t) : ek_ 1,1 (t) = ek, 2 (t)
Oik,1 (X, t)
OX
i = ~
- GK,2 l\t -
lK-1,1 UK_I,1
FK_I,1
)
UK,IK'2rl2
+ GK-I,1 (0
(5)
Basic flow chart for the computer simulation defines the step-wise algorithm. In this chart the data can be read from the card. Step 1 : the data R (resistor), L (inductance), C (capacitor), Z (impedance), T (end time of simulation) and so on are read from the card. Step 2 : voltage, current, forward and backward waves are calculated from the initial conditions in the first step. Step 3: Ig (gate current) and Vk (gate voltage) can be calculated with the help of equations as described before. Steps 4 and 5 : the calculations for F k and Gk, e k and ik are made with the help of set of equations as explained in computer-aided analysis in transmission lines based on fundamental theory. Finally we have to check whether simulation time has ended or not.
(6)
(7)
/
I
the current away from the node. For the Josephson junction, we have two fundamental differential equations
+ Vk(t)/R(Vk) + Jok sin 0 (t)
Initi°l c°nditi°ns
..J
where ek_l, 1(t) and ek, 2 (t) represent the voltage at node K, ik-l,1 (t) is the current towards the node, and ik,2(t) is
Step 3
The unknowns in lumped circuits ore determined
Step 4
Forword ond bockword woves ore obtoined
Step 5
Line voltages and line currents ore colculoted
(8) (9)
where Igk(t) is the gate current, Vk(t ) is the voltage across junction, Ck is the capacitance of the junction, Jok is the critical current and 0 is the phase difference between two superconductors of junction, R(Vk) is the non-linear resistance of the junction when it switches to the voltage state. The resistance is obtained from the V-I characteristics of the junction, where the tunnelling current and quasi-particle current flow. This V - I characteristic is represented in the following mathematical terms.
CRYOGENICS. SEPTEMBER 1982
I Step 2
UK-I,1
- aK_l,, (t) /
dO(t)/dt = 2e/h Vk(t)
I
I
\
Igk(t) = C k " d Vk(t)/dt
( Step ea 0a,o _
Fig. 5
Flow chart for the computer-aided
calculation
463
Table 1.
Truth table for the simulation
~-~ 3.6 V
Input Xn
Yn
Cn-I
Output Sn
Cn
a
1
1
1
1
1
b
1
0
1
0
1
c
1
1
0
0
1
=, 1.2V
1.2V
8
Computer simulation
[o+° I
Computer simulation is made to check the operation of the model representing an adder in distributed parameter network as shown in Fig. 6. The equivalent circuit and I - V characteristics curve of the Josephson junction are shown in Fig. 7. The basic equations describing the model are shown by the simultaneous partial differential equations with non-linear boundary condition of the junction, which cannot be solved analytically. Therefore these equations can be transformed into differential difference equations suitable for digital computation. These equations have already been discussed in computer aided analysis in transmission lines.
"0.5
0.5
Fig. 8 (a), (b) and (c) show current-time characteristics of the simulated operation of the adder, for which the truth table is also given in Table 1. It is very clear from Fig. 8 that the carry C n can be generated immediately without receiving the preceeding carry when X n = Y n = 1. The bias pulse is not supplied to the junction until the inputs X n and Y n are applied. Therefore both inputs need not to be absolutely coincident. Furthermore, if the bias voltage and inputs are applied at the same time, even then, the result will not be affected.
Fig. 6 Equivalent circuit of the high speed adder, consisting of JTLs and Iosslesstransmissionlinesfor computer simulation
-- - I ~ - - - - -
I
Ve
Y
The simulation results show that the delay time of the adder is 20 ps/stage and power consumption is 47 #W/stage which means the adder with 32 bits is able to operate with delay of less than 320 ps and 1.5 mW power. This simulation also shows an impressive result that even if some parameters in the network model are changed such
vc
b Fig. 7 a - Equivalent circuit of the Josephson junction for the simulation, b -- nonlinear current-voltage characteristics of a Josephson junction
0
I
0
f
E
I
I
I
S
0
E
Sn 0 co
E 0
a Fig. 8
#
k .........,50
~o
,oo ..... Ps
o
b
S
,L................ ,50
~o
,oo Ps
o C
;
;
5'o
Jo'
............
,,o
Ps
Results of the computer simulation for the circuit as shown in Fig. 6, showing how the operation of the adder is achieved for the Yn=landCn--1 =l;b--Xn=O, Yn=landCn--1 =l;c--Xn=l, Yn = l a n d c n 1=0
following three states of the s i g n a l s : a - - X n = l ,
464
C RYOG EN I CS. SEPTEM BE R 1982
Although the adder described here is constructed by using the Josephson Tunnelling Logic gates as an example, this system may also be implemented with interferometers or current injection logics. 4
2oI 0 041
f ~
Conclusion
0
ooi :
L_
0~
The design of a novel adder by using the Josephson junctions is proposed. The principle of operation, computer aided analysis in transmission line and simulation of the adder is made. The unique feature of directionality is discussed in detail. Further application of the technique is proposed for network transmission lines. Changing the value of a parameter in the model such as resistance will not cause any effect on reliable operation of the adder. Finally this paper suggests that the adder with 32 bits will be able to operate in a shorter time than 320 ps.
o,I O0
50
IOC)v%';';'--..... ISO Ps
Fig. 9 Resultsof the simulation in the caseof changing s o m e circuit parameters by about 17% in the circuit as shown in Fig. 6, which indicates that no peculiar effect is produced on the smooth operation of the adder
as resistances from 6 f2 and 8 ~2 to 5 f2 and 6.7 ~2 respectively, the operation of the adder in Fig. 9 does not show any unstable behaviour.
CRYOGENICS. SEPTEMBER 1982
The authors would like to express their appreciation for kind guidance of Professor Y. Komamiya, and thank Mrs Y. Kaminuma and Mr H. Tsuchida for their help to prepare this paper. The authors acknowledge supports from ministry of education of Japanese Government under the special research project on 'Superconducting Quantum Electronics' for this work. References 1 2 3 4
Matiso, J. IBMJR&D 24 (1980) 113 Herrell, D.J. 1EEE Trans Mag MAG-10 (1974) 864 Zappe, H.H. JApplPhys 44 (1973) 1371 Gheewala,R.IL IBMJR&D 24 (1980) 130
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