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Effect of graded InGaN drain region and ’In’ fraction in InGaN channel on performances of InGaN tunnel field-effect transistor
Superlattices and Microstructures 112 (2017) 671e679
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Effect of graded InGaN drain region and ’In’ fraction in InGaN channel on performances of InGaN tunnel field-effect transistor Xiaoling Duan, Jincheng Zhang*, Shulong Wang, Rudai Quan, Yue Hao Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory, School of Microelectronics, Xidian University, Xi’an, 710071, China
a r t i c l e i n f o
a b s t r a c t
Article history: Received 11 September 2017 Received in revised form 21 October 2017 Accepted 21 October 2017 Available online 27 October 2017
An InGaN-based graded drain region tunnel field-effect transistor (GD-TFET) is proposed to suppress the ambipolar behavior. The simulation results with the trade-off between onstate current (Ion) and ambipolar current (Iambipolar) show decreased Iambipolar (1.9 1014 A/mm) in comparison with that of conventional TFETs (2.0 108 A/mm). Furthermore, GD-TFET with high ’In’ fraction InxGa1-xN source-side channel (SC- GD-TFET) is explored and exhibits 5.3 times Ion improvement and 60% average subthreshold swing (SSavg) reduction in comparison with GD-TFET by adjusting ’In’ fraction in the InxGa1-xN source-side channel. The improvement is attributed to the confinement of BTBT in the source-side channel by the heterojunction. And then, the optimum value for source-side channel length (Lsc) is researched by DC performances results, which shows it falls into the range between Lsc ¼ 10 nm and 20 nm. © 2017 Elsevier Ltd. All rights reserved.
Keywords: TFET Band to band tunneling (BTBT) Graded InGaN Source-side channel
1. Introduction In recent years, as the integrated circuit technology coming into the nano-size, MOSFET suffers from problems of short channel effects (SCEs), such as degradation of sub-threshold swing (SS), high leakage current (Ioff), and loss of gate controllability over the channel [1e3]. Tunnel field-effect transistor (TFET), in which the carrier injection from source to channel is by tunneling, is not limited by the thermionic emission constraint, so the SS is lower than 60mV/decade. For this, TFET has been considered as an attractive alternative to the MOSFET in the ultralow supply voltage integrated circuits [4,5]. Although TFET has low SS and good immunity to SCEs due to the quantum band-to-band tunneling (BTBT) phenomena for current conduction, conventional TFETs still encounter small Ion [6,7], less-than-ideal SS, and ambipolar behavior [8] as reported in the literature. Regarding these issues, different techniques have been developed, such as narrow bandgap materials, double gate TFET [9], heterojunction engineering [10e12], drain doping profile investigation [13], gate-drain electrode gap control [14], etc. Recently, TFETs based on narrow bandgap semiconductors such as InGaAs, InAs and GaSb have been demonstrated theoretically and experimentally [15,16]. These based on narrow bandgap materials (e.g. InAs, GaSb) exhibit high Ion but severe ambipolar conduction. To suppress Iambipolar, wide band-gap materials like III-Nitride (GaN and AlN) can be used [17]. However, the large band gap makes it impractical to realize interband tunneling in homojunctions. To trade off the ambipolar
* Corresponding author. https://doi.org/10.1016/j.spmi.2017.10.026 0749-6036/© 2017 Elsevier Ltd. All rights reserved.
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behavior and on-state performance, an In0.75Ga0.25N TFET with moderately wide bandgap InGaN by control of ’In’ fraction in drain region may be useful to suppress the ambipolar behavior in devices. Furthermore, TFET with high ’In’ fraction InGaN in the source-side channel is expected to obtain a high Ion due to the narrow bandgap. Technically, InGaN material has been widely used in light-emitting diodes (LEDs) [18,19], the synthesis of which across the entire compositional range can be facilitated by the plasma-assisted molecular beam epitaxy (PAMBE) [20,21]. For the reasons above, the band-gap modulated InGaN layer materials may be suitable for low-power TFET devices application. In this paper, we propose a novel InGaN graded drain TFET (GD-TFET) and explored the effects of graded InGaN drain on DC performances of InGaN TFET. And then, the ambipolar behavior with different specific location of the graded InGaN is analyzed. Furthermore, the channel of GD-TFET is divided into source-side channel and drain-side channel. This proposed stacked InGaN-layers TFET will be termed as SC-GD-TFET which is explored to improve on-state performances of GD-TFET. ’In’ fraction (x) and the length (Lsc) of the source-side channel are controlled to optimize the DC performances of the TFET devices. The paper is organized as follows: section 2 incorporates the device design and simulation models. Section 3 dedicates for the comparative analysis of the conventional In0.75Ga0.25N TFET, InGaN GD-TFET, and InGaN source-side channel GD-TFET (SCGD-TFET), where Iambipolar, SS (point and average), Ion and BTBT rate are mainly investigated. Finally, section 4 gives the conclusions.
2. Device structure and simulation methods Fig. 1 shows the schematics of the cross-section of the InGaN TFET. Fig. 1 (a) is the conventional In0.75Ga0.25N TFET as a referential device. Fig. 1 (b) shows the InGaN GD-TFET where the drain region is replaced by a graded InGaN. The graded InGaN drain region consists of 5 nm In0.65Ga0.35N, 5 nm In0.55Ga0.45N and ~100 nm In0.45Ga0.55N. SC-GD-TFET with an InxGa1xN source-side channel is proposed in Fig. 1 (c). The channel is divided into two sections: a source-side channel and a drainside channel. Total channel length (Lch) is 50 nm and the source-side channel length is labeled as Lsc, the body thickness (t) ¼ 10 nm, and gate oxide thickness (tox) ¼ 3 nm. The doping concentrations of the pþ source, n channel, and nþ drain are
Fig. 1. Schematic of the (a) conventional In0.75Ga0.25N TFET, (b) GD-TFET with the graded InGaN drain region, and (c) SC-GD-TFET with InxGa1-xN source-side channel and graded drain region.
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Table 1 Material parameters used in the simulation [17]. Parameters
InxGa1-xN
Band gap Eg (eV) Hole effective mass (m0) Electron effective mass (m0) Static dielectric constant εr Electron mobility me (cm2/V$s) Hole mobility mh (cm2/V$s)
1.4x2-4.1xþ3.4 0.46e0.22x 0.2e0.13x 10.5 þ 3.0x 1050 20
9.9 1019, 1 1015, and 1.2 1019 cm3, respectively. Al2O3 is used as the gate dielectric. The material parameters are listed in Table 1. The device simulations are carried out by the Silvaco Atlas simulator [22]. For the TCAD simulations, the device electrostatics are simulated by solving Poisson’s equation self-consistently with the carrier current continuity equations, while the interband tunneling process is treated by the nonlocal BTBT model, which can reflect a more real tunneling process. In this concern, tunneling region is defined at drain/channel and source/channel junctions to enable the forward and reverse tunneling. The Shockley-Read-Hall (SRH) recombination model, concentration-dependent and field-dependent mobility models are also considered. Quantization effects are not included in the simulations. For the film thickness below 10 nm, quantum confinement model has to be enabled in the simulations [23]. All of the TFET devices are fabricated on the nonpolar plane, so the polarization characteristics are not considered in the simulations. 3. Results and discussions 3.1. GD-TFET to suppress ambipolar current Graded InGaN drain region in the InGaN TFET is explored to facilitate the low Iambipolar. L1 is the position of the gate electrode edge as illustrated in Fig. 1 (b). In the practical applications, it is difficult to achieve a perfect alignment of L1 with the
Fig. 2. Transfer characteristic of InGaN TFET with graded InGaN drain region. (a) Id-Vg curves and (b) Ion and Iambipolar with different In0.65Ga0.35N/In0.75Ga0.25N interface location at Vd ¼ 1 V.
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Fig. 3. Energy band diagrams below gate oxide with different In0.65Ga0.35N/In0.75Ga0.25N interface location at (a) the negative gate bias and (b) Vd ¼ 1 V, Vg ¼ 1 V.
In0.65Ga0.35N/In0.75Ga0.25N interface. Therefore, performance analysis for the misalignment is presented in Fig. 2. It is shown that the proposed modification in the device results in a significant reduction of Iambipolar. As the In0.75Ga0.25N/In0.65Ga0.35N interface is aligned with L1, Iambipolar ¼ 1.7 1011 A/mm which is 1.2 103 times reduction in comparison with that of conventional TFETs (2.0 108 A/mm) at Vd ¼ 1 V and Vg ¼ 1 V, but Ion has almost no degradation at Vg ¼ 1 V. As the In0.65Ga0.35N/In0.75Ga0.25N interface shifts to the channel-side direction, Iambipolar will decrease further. When the position of the In0.65Ga0.35N/In0.75Ga0.25N interface is located at L1þ10 nm, Iambipolar is reduced to 3.4 1016 A/mm; however, Ion starts to fall as shown in Fig. 2 (a) and (b). Besides, as the In0.65Ga0.35N/In0.75Ga0.25N interface shifts to the drain-side direction, Iambipolar is not significantly reduced and is almost the same with that of the conventional In0.75Ga0.25N TFET. The reason is that Iambipolar is determined by transfer characteristic at the negative gate bias, but Ion is extracted at Vg of 1 V. To gain a better insight into the variation of Iambipolar and Ion, energy band profiles for Vg of 1 V and 1 V are shown in Fig. 3 (a) and (b), respectively. Fig. 3 (a) displays that the band gap gradually increases from the channel region to drain region in the GD-TFET, which results in the wider tunneling distance and the lower BTBT tunneling rate at the drain/channel interface, hence the reduction in Iambipolar is achieved. As the In0.65Ga0.35N/In0.75Ga0.25N interface shifts to the channel-side, the lateral tunneling distance at drain/channel interface further increases; therefore, lower Iambipolar is obtained. Fig. 3 (b) shows the energy band profile at the on-state. As the In0.65Ga0.35N/In0.75Ga0.25N interface is located at the position of L1þ10 nm, an energy peak near the drain/channel interface is created, which will act as barrier for electrons from source to drain region for the positive bias [24]. Therefore, Ion of the device will degrade as shown in Fig. 2 (b). Considering the trade-off between Ion and Iambipolar, the position of In0.75Ga0.25N/In0.65Ga0.35N interface is designed as L1þ5 nm in the following discussions.
3.2. SC-GD-TFET to improve on-state performances 3.2.1. Effect of x fraction of InxGa1-xN source-side channel on device performances To improve on-state performances of InGaN GD-TFET, a source-side channel InxGa1-xN is adopted in the GD-TFET. The length of InxGa1-xN source-side channel (Lsc) is 10 nm. Fig. 4 (a) shows the simulated transfer characteristics of the proposed
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Fig. 4. Transfer characteristic of SC-GD-TFETs with varying ’In’ fraction of InxGa1-xN in the source-side channel. (a) Id-Vg curves, (b) point swing S versus Id, and (c) average SS and Ion at Vd ¼ 1 V.
TFET device with different ’In’ fraction in the InxGa1-xN source-side channel. The threshold voltage Vt is defined as the voltage at which the current is 1 107 A/mm. With 0.7, 0.75, 0.8 and 0.85 ’In’ fraction in the source-side channel, Vt of TFETs are 0.71, 0.55, 0.39, and 0.27 V, respectively. The negative shift of Vt with the increasing of ’In’ fraction originates from the narrower lateral tunneling distance. What’s more, as the ’In’ fraction x > 0.75, the proposed structure significantly improves the steepness of turn-on behavior while maintaining the low ambipolar current. At the Vg of 1 V, the ambipolar current is of the order of 1014 A/mm for all the devices. It indicates that Iambipolar of the SC-GD-TFET is not affected by the ’In’ fraction variation in the source-side channel. As Vg increases to 1 V, Ion enhancement is achieved in SC-GD-TFET with ’In’ fraction x > 0.75 over GD-TFET (x ¼ 0.75). SC-GD-TFET with x ¼ 0.85 shows Ion ¼ 1.1 104 A/mm which is 5.3 times higher than that of GD-TFET (x ¼ 0.75). Fig. 4 (b) depicts the point swing S versus Id plots extracted from Id-Vg curves in Fig. 4 (a). Point swing S refers to the reciprocal of the slope of the Id-Vg curve obtained at a specific Id. It is observed that point swing S for x ¼ 0.85 SC-GD-TFET is the smallest compared with that of the other InxGa1-xN SC-GD-TFETs at any Id. Fig. 4 (c) shows average swing S (SSavg) and Ion as a function of ’In’ fraction (x). At x ¼ 0.85, the highest Ion of 1.1 104 A/mm and the lowest SSavg of 18.2 mV/decade are
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Fig. 5. Energy band diagrams below gate oxide with different ’In’ fraction of InxGa1-xN in the source-side channel at (a) the off-state and (b) the on-state.
achieved due to the narrowing effective tunneling barrier width. Therefore, to obtain lower SSavg and higher Ion, a larger ’In’ fraction is desirable in SC-GD-TFET. Fig. 5 depicts the energy band diagrams of the device at off-state and on-state for different ’In’ fraction x in the source-side channel InxGa1-xN. As x of InxGa1-xN increases, Eg of InxGa1-xN becomes smaller. As a result, the effective tunneling barrier width between source and channel becomes narrower at the given operating condition, which increases the tunneling probability of source-to-channel BTBT. Therefore, higher on-state current is achieved. Besides, the steeper characteristic of energy bands at the source/channel interface induces the smaller SSavg. This is the reason why the larger ’In’ fraction x gets smaller SSavg as shown in Fig. 4 (c). To get a better insight into the modulation effect of the source-side channel, contour plots of the nonlocal e- BTBT rates at Vg ¼ 1 V and Vd ¼ 1 V in SC-GD-TFET with x ¼ 0.85 and GD-TFET are displayed in Fig. 6 (a) and (b), respectively. We can confirm that SC-GD-TFET achieves a higher peak e- BTBT rates than GD-TFET. The e- BTBT rate degrades with contour lines extending to the drain direction, indicating long tunneling paths have low tunneling probability. It should be noted that the magnitude
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Fig. 6. Contour plots of e- BTBT rates at Vg ¼ 1 V and Vd ¼ 1 V in (a) In0.85Ga0.15N SC-GD-TFET and (b) GD-TFET.
of e- BTBT rate for source-side channel TFET shows a sudden decrease as e- BTBT rate profile crosses the heterojunction in the channel as shown in Fig. 6 (a). The maximum e- BTBT rates centers are confined in the region of the source-side channel in In0.85Ga0.15N source-side channel TFET. It infers that the significant BTBT has to choose the short tunneling paths, which will
Fig. 7. Transfer characteristic of SC-GD-TFET with ’In’ fraction of 0.85 in the source-side channel at different Lsc. (a) Id-Vg curves. (b) Average SS and Ion as the function of Lsc.
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Fig. 8. Energy band diagrams below gate oxide near the source-channel interface with different Lsc at (a) thermal equilibrium state and (b) Vd ¼ 1 V, Vg ¼ 0.5 V.
contribute to high tunneling rate. So the confinement of BTBT in the source-side channel near the source-channel junction can elevate tunneling probability and improve the on-state current. 3.2.2. Effect of variation of source-side channel length Lsc on device performances The proposed TFET device shows optimized DC characteristics at ’In’ fraction of 0.85 with Lsc ¼ 10 nm. Fig. 7 (a) and (b) show the Id-Vg curves and DC performances for devices with different Lsc at x ¼ 0.85. As can be seen in Fig. 7 (a), SSavg is sensitive to Lsc and may have an optimum value. Besides, Ion is degraded for an extremely short Lsc (Lsc ¼ 5 nm). Both SSavg and Ion have been extracted and exhibited in Fig. 7 (b). It indicates that an optimum value of Lsc in physical designing will fall into the range between Lsc ¼ 10 nm and 20 nm. Fig. 8 shows the energy band diagrams near the source-channel interface of the SC-GD-TFET. It can be found that when Lsc becomes as thin as 5 nm, valence electrons tunneling from source to channel encounter a relatively higher barrier which hinders the BTBT. The BTBT is not yet confined in the source-side channel. Part of the electrons tunnel from the source to the drain-side channel region near the heterojunction interface. This process encounters larger tunneling distance than that occurs in the TFET Lsc 10 nm where the BTBT is confined in the source-side channel region, which consequently degrades Ion. 4. Conclusions Effect of graded InGaN drain region and ’In’ fraction in InGaN channel on performances of InGaN tunnel field-effect transistor has been researched by ATLAS simulations in this paper. Firstly, the GD-TFET is put forward to reduce Iambipolar. The graded InGaN drain increases the lateral tunnel barrier width at the channel-drain junction and reduces the BTBT tunneling rate. Iambipolar reduces from 2.0 108 A/mm in conventional TFET to 1.9 1014 A/mm in GD-TFET. Secondly, SC-GD-
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TFET with ’In’ fraction of 0.85 in source-side channel is proposed, which exhibits a higher Ion of 1.1 104 A/mm and lower SSavg of 18.2 mV/decade after adjusting ’In’ fraction in the source-side InGaN channel. The improved performances are attributed to the small band-gap of the source-side channel In0.85Ga0.15N, narrow lateral tunneling distance and steepness of the source-channel junction. The optimum value of Lsc falls into the range between Lsc ¼ 10 nm and 20 nm resulting from the DC results. The research here indicated that the proposed SC-GD-TFET embodies an appropriate candidate for low power circuit applications. Acknowledgment This work was supported by the National Natural Science Foundation of China (Grant No. 61334002 and No. 61604115). References [1] S. Borkar, Circuit techniques for subthreshold leakage avoidance, control, and tolerance, in: IEEE Int. Electron Devices (IEDM) Tech. Dig., 2004, pp. 421e424. [2] S. Bangsaruntip, G.M. Cohen, A. Majumdar, J.W. Sleight, Universality of short-channel effects in undoped-body silicon nanowire MOSFETs, IEEE Electron Device Lett. 31 (9) (2010) 903e905. [3] H. Masuda, M. Nakai, M. Kubo, Characteristics and limitation of scaled-down MOSFET’s due to two-dimensional field effect, IEEE Trans. Electron Devices 26 (6) (1979) 980e986. [4] A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches, Nature 479 (7373) (2011) 329e337. [5] S.O. Koswatta, M.S. Lundstrom, D.E. Nikonov, Performance comparison between p-i-n tunneling transistors and conventional MOSFETs, IEEE Trans. Electron Devices 56 (3) (2007) 456e465. [6] S. Saurabh, M.J. Kumar, Novel attributes of a dual material gate nanoscale tunnel field-effect transistor, IEEE Trans. Electron Devices 58 (2) (2011) 404e410. [7] E.-H. Toh, G.H. Wang, G.S. Samudra, Y.-C. Yeo, Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization, Appl. Phys. Lett. 90 (26) (2007), 263507-1-;263507e3. [8] A. Hraziia, Vladimirescu, A. Amara, C. Anghel, An analysis on the ambipolar current in Si double-gate tunnel FETs, Solid-State Electron. 67 (1) (2012) 67e72. [9] T. Krishnamohan, D. Kim, S. Raghunathan, K. Saraswat, Double gate strained Ge heterostructure tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope, in: IEDM Tech. Dig., Dec 2008, pp. 947e949. [10] Y. Peng, G. Han, H. Wang, C. Zhang, Y. Liu, Y. Wang, S. Zhao, J. Zhang, Y. Hao, InN/InGaN complementary heterojunction-enhanced tunneling field-effect transistor with enhanced subthreshold swing and tunneling current, Superlattices Microstruct. 93 (2016) 144e152. [11] H. Wang, Y. Liu, M. Liu, Q. Zhang, C. Zhang, X. Ma, J. Zhang, Y. Hao, G. Han, Performance improvement in novel germaniumetin/germanium heterojunction-enhanced p-channel tunneling field-effect transistor, Superlattices Microstruct. 83 (2015) 401e410. [12] Y. Wang, Y. Liu, G. Han, H. Wang, C. Zhang, J. Zhang, Y. Hao, Theoretical investigation of GaAsBi/GaAsN tunneling field-effect transistors with type-II staggered tunneling junction, Superlattices Microstruct. 106 (2017) 139e146. [13] V. Vijayvargiya, S.K. Vishvakarma, Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance, IEEE Trans. Nanotechnol. 13 (5) (2014) 974e981. [14] D.B. Abdi, M.J. Kumar, PNPN tunnel FET with controllable drain side tunnel barrier width: proposal and analysis, Superlattices Microstruct. 86 (2015) 121e125. [15] D. K. Mohata, R. Bijesh, S. Mujumdar, C. Eaton, R. Engel-Herbert, T. Mayer, V. Narayanan, J. M. Fastenau, D. Loubychev, A. K. Liu, S. Datta, Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered hetero - junctions for 300mV logic applications, In: 2011 IEEE Int. Electron Devices Meeting (IEDM), pp. 33.5.1-33.5.4. [16] G. Zhou, R. Li, T. Vasen, M. Qi, S. Chae, Y. Lu, Q. Zhang, H. Zhu, J.-M. Kuo, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, Huili (Grace) Xing, Novel gate- recessed vertical InAs/GaSb TFETs with record high ION of 180 mA/mm at VDS ¼ 0.5 V, in: 2012 IEEE Int. Electron Devices Meeting (IEDM), 2011, 32.6.1-32.6.4. [17] W. Li, S. Sharmin, H. Ilatikhameneh, R. Rahman, Y. Lu, J. Wang, X. Yan, A. Seabaugh, G. Klimeck, D. Jena, P. Fay, Polarization engineering III-Nitride heterojunction tunnel field-effect transistors, IEEE J. Explor. Solid-State Comput. Devices Circuits 1 (2015) 28e34. [18] F. Akyol, D.N. Nath, S. Krishnamoorthy, P.S. Park, S. Rajan, Suppression of electron overflow and efficiency droop in N-polar GaN green light emitting diodes, Appl. Phys. Lett. 100 (11) (2012) 111118. [19] T. Tanikawa, K. Shojiki, S. Kuboya, R. Katayama, T. Matsuoka, Large Stokes-like shift in N-polar InGaN/GaN multiple-quantum-well light-emitting diodes, Jpn. J. Appl. Phys. 55 (5) (2016) 05FJ03. mez, N.U.H. Alvi, J.M. Ma nuel, F.M. Morales, J.J. Jime nez, R. García, A. Senichev, C. Lienau, E. Calleja, R. No € tzel, Near [20] P. Aseev, P.E.D. Soto Rodriguez, V.J. Go infrared emitting In-rich InGaN layers grown directly on Si: towards the whole composition range, Appl. Phys. Lett. 106 (2015) 072102. [21] C.A.M. Fabien, B.P. Gunning, W.A. Doolittle, A.M. Fischer, Y.O. Wei, H. Xie, F.A. Ponce, Low temperature growth of InGaN films over the entire composition range by MBE, J. Cryst. Growth 425 (1) (2015) 115e118. [22] Silvaco International, ATLAS User’s Manual, 2013. [23] Y. Omura, S. Horiguchi, M. Tabe, K. Kishi, Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs, IEEE Trans. Electron Devices 14 (12) (1993) 569e571. [24] B.R. Raad, D. Sharma, P. Kondekar, K. Nigam, D.S. Yadav, Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and RF performance improvement: a proposal, design, and investigation, IEEE Trans. Electron Devices 63 (10) (2016) 3950e3957.
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Effect of graded InGaN drain region and ’In’ fraction in InGaN channel on performances of InGaN tunnel field-effect transistor Xiaoling Duan, Jincheng Zhang*, Shulong Wang, Rudai Quan, Yue Hao Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory, School of Microelectronics, Xidian University, Xi’an, 710071, China
a r t i c l e i n f o
a b s t r a c t
Article history: Received 11 September 2017 Received in revised form 21 October 2017 Accepted 21 October 2017 Available online 27 October 2017
An InGaN-based graded drain region tunnel field-effect transistor (GD-TFET) is proposed to suppress the ambipolar behavior. The simulation results with the trade-off between onstate current (Ion) and ambipolar current (Iambipolar) show decreased Iambipolar (1.9 1014 A/mm) in comparison with that of conventional TFETs (2.0 108 A/mm). Furthermore, GD-TFET with high ’In’ fraction InxGa1-xN source-side channel (SC- GD-TFET) is explored and exhibits 5.3 times Ion improvement and 60% average subthreshold swing (SSavg) reduction in comparison with GD-TFET by adjusting ’In’ fraction in the InxGa1-xN source-side channel. The improvement is attributed to the confinement of BTBT in the source-side channel by the heterojunction. And then, the optimum value for source-side channel length (Lsc) is researched by DC performances results, which shows it falls into the range between Lsc ¼ 10 nm and 20 nm. © 2017 Elsevier Ltd. All rights reserved.
Keywords: TFET Band to band tunneling (BTBT) Graded InGaN Source-side channel
1. Introduction In recent years, as the integrated circuit technology coming into the nano-size, MOSFET suffers from problems of short channel effects (SCEs), such as degradation of sub-threshold swing (SS), high leakage current (Ioff), and loss of gate controllability over the channel [1e3]. Tunnel field-effect transistor (TFET), in which the carrier injection from source to channel is by tunneling, is not limited by the thermionic emission constraint, so the SS is lower than 60mV/decade. For this, TFET has been considered as an attractive alternative to the MOSFET in the ultralow supply voltage integrated circuits [4,5]. Although TFET has low SS and good immunity to SCEs due to the quantum band-to-band tunneling (BTBT) phenomena for current conduction, conventional TFETs still encounter small Ion [6,7], less-than-ideal SS, and ambipolar behavior [8] as reported in the literature. Regarding these issues, different techniques have been developed, such as narrow bandgap materials, double gate TFET [9], heterojunction engineering [10e12], drain doping profile investigation [13], gate-drain electrode gap control [14], etc. Recently, TFETs based on narrow bandgap semiconductors such as InGaAs, InAs and GaSb have been demonstrated theoretically and experimentally [15,16]. These based on narrow bandgap materials (e.g. InAs, GaSb) exhibit high Ion but severe ambipolar conduction. To suppress Iambipolar, wide band-gap materials like III-Nitride (GaN and AlN) can be used [17]. However, the large band gap makes it impractical to realize interband tunneling in homojunctions. To trade off the ambipolar
* Corresponding author. https://doi.org/10.1016/j.spmi.2017.10.026 0749-6036/© 2017 Elsevier Ltd. All rights reserved.
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behavior and on-state performance, an In0.75Ga0.25N TFET with moderately wide bandgap InGaN by control of ’In’ fraction in drain region may be useful to suppress the ambipolar behavior in devices. Furthermore, TFET with high ’In’ fraction InGaN in the source-side channel is expected to obtain a high Ion due to the narrow bandgap. Technically, InGaN material has been widely used in light-emitting diodes (LEDs) [18,19], the synthesis of which across the entire compositional range can be facilitated by the plasma-assisted molecular beam epitaxy (PAMBE) [20,21]. For the reasons above, the band-gap modulated InGaN layer materials may be suitable for low-power TFET devices application. In this paper, we propose a novel InGaN graded drain TFET (GD-TFET) and explored the effects of graded InGaN drain on DC performances of InGaN TFET. And then, the ambipolar behavior with different specific location of the graded InGaN is analyzed. Furthermore, the channel of GD-TFET is divided into source-side channel and drain-side channel. This proposed stacked InGaN-layers TFET will be termed as SC-GD-TFET which is explored to improve on-state performances of GD-TFET. ’In’ fraction (x) and the length (Lsc) of the source-side channel are controlled to optimize the DC performances of the TFET devices. The paper is organized as follows: section 2 incorporates the device design and simulation models. Section 3 dedicates for the comparative analysis of the conventional In0.75Ga0.25N TFET, InGaN GD-TFET, and InGaN source-side channel GD-TFET (SCGD-TFET), where Iambipolar, SS (point and average), Ion and BTBT rate are mainly investigated. Finally, section 4 gives the conclusions.
2. Device structure and simulation methods Fig. 1 shows the schematics of the cross-section of the InGaN TFET. Fig. 1 (a) is the conventional In0.75Ga0.25N TFET as a referential device. Fig. 1 (b) shows the InGaN GD-TFET where the drain region is replaced by a graded InGaN. The graded InGaN drain region consists of 5 nm In0.65Ga0.35N, 5 nm In0.55Ga0.45N and ~100 nm In0.45Ga0.55N. SC-GD-TFET with an InxGa1xN source-side channel is proposed in Fig. 1 (c). The channel is divided into two sections: a source-side channel and a drainside channel. Total channel length (Lch) is 50 nm and the source-side channel length is labeled as Lsc, the body thickness (t) ¼ 10 nm, and gate oxide thickness (tox) ¼ 3 nm. The doping concentrations of the pþ source, n channel, and nþ drain are
Fig. 1. Schematic of the (a) conventional In0.75Ga0.25N TFET, (b) GD-TFET with the graded InGaN drain region, and (c) SC-GD-TFET with InxGa1-xN source-side channel and graded drain region.
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Table 1 Material parameters used in the simulation [17]. Parameters
InxGa1-xN
Band gap Eg (eV) Hole effective mass (m0) Electron effective mass (m0) Static dielectric constant εr Electron mobility me (cm2/V$s) Hole mobility mh (cm2/V$s)
1.4x2-4.1xþ3.4 0.46e0.22x 0.2e0.13x 10.5 þ 3.0x 1050 20
9.9 1019, 1 1015, and 1.2 1019 cm3, respectively. Al2O3 is used as the gate dielectric. The material parameters are listed in Table 1. The device simulations are carried out by the Silvaco Atlas simulator [22]. For the TCAD simulations, the device electrostatics are simulated by solving Poisson’s equation self-consistently with the carrier current continuity equations, while the interband tunneling process is treated by the nonlocal BTBT model, which can reflect a more real tunneling process. In this concern, tunneling region is defined at drain/channel and source/channel junctions to enable the forward and reverse tunneling. The Shockley-Read-Hall (SRH) recombination model, concentration-dependent and field-dependent mobility models are also considered. Quantization effects are not included in the simulations. For the film thickness below 10 nm, quantum confinement model has to be enabled in the simulations [23]. All of the TFET devices are fabricated on the nonpolar plane, so the polarization characteristics are not considered in the simulations. 3. Results and discussions 3.1. GD-TFET to suppress ambipolar current Graded InGaN drain region in the InGaN TFET is explored to facilitate the low Iambipolar. L1 is the position of the gate electrode edge as illustrated in Fig. 1 (b). In the practical applications, it is difficult to achieve a perfect alignment of L1 with the
Fig. 2. Transfer characteristic of InGaN TFET with graded InGaN drain region. (a) Id-Vg curves and (b) Ion and Iambipolar with different In0.65Ga0.35N/In0.75Ga0.25N interface location at Vd ¼ 1 V.
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Fig. 3. Energy band diagrams below gate oxide with different In0.65Ga0.35N/In0.75Ga0.25N interface location at (a) the negative gate bias and (b) Vd ¼ 1 V, Vg ¼ 1 V.
In0.65Ga0.35N/In0.75Ga0.25N interface. Therefore, performance analysis for the misalignment is presented in Fig. 2. It is shown that the proposed modification in the device results in a significant reduction of Iambipolar. As the In0.75Ga0.25N/In0.65Ga0.35N interface is aligned with L1, Iambipolar ¼ 1.7 1011 A/mm which is 1.2 103 times reduction in comparison with that of conventional TFETs (2.0 108 A/mm) at Vd ¼ 1 V and Vg ¼ 1 V, but Ion has almost no degradation at Vg ¼ 1 V. As the In0.65Ga0.35N/In0.75Ga0.25N interface shifts to the channel-side direction, Iambipolar will decrease further. When the position of the In0.65Ga0.35N/In0.75Ga0.25N interface is located at L1þ10 nm, Iambipolar is reduced to 3.4 1016 A/mm; however, Ion starts to fall as shown in Fig. 2 (a) and (b). Besides, as the In0.65Ga0.35N/In0.75Ga0.25N interface shifts to the drain-side direction, Iambipolar is not significantly reduced and is almost the same with that of the conventional In0.75Ga0.25N TFET. The reason is that Iambipolar is determined by transfer characteristic at the negative gate bias, but Ion is extracted at Vg of 1 V. To gain a better insight into the variation of Iambipolar and Ion, energy band profiles for Vg of 1 V and 1 V are shown in Fig. 3 (a) and (b), respectively. Fig. 3 (a) displays that the band gap gradually increases from the channel region to drain region in the GD-TFET, which results in the wider tunneling distance and the lower BTBT tunneling rate at the drain/channel interface, hence the reduction in Iambipolar is achieved. As the In0.65Ga0.35N/In0.75Ga0.25N interface shifts to the channel-side, the lateral tunneling distance at drain/channel interface further increases; therefore, lower Iambipolar is obtained. Fig. 3 (b) shows the energy band profile at the on-state. As the In0.65Ga0.35N/In0.75Ga0.25N interface is located at the position of L1þ10 nm, an energy peak near the drain/channel interface is created, which will act as barrier for electrons from source to drain region for the positive bias [24]. Therefore, Ion of the device will degrade as shown in Fig. 2 (b). Considering the trade-off between Ion and Iambipolar, the position of In0.75Ga0.25N/In0.65Ga0.35N interface is designed as L1þ5 nm in the following discussions.
3.2. SC-GD-TFET to improve on-state performances 3.2.1. Effect of x fraction of InxGa1-xN source-side channel on device performances To improve on-state performances of InGaN GD-TFET, a source-side channel InxGa1-xN is adopted in the GD-TFET. The length of InxGa1-xN source-side channel (Lsc) is 10 nm. Fig. 4 (a) shows the simulated transfer characteristics of the proposed
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Fig. 4. Transfer characteristic of SC-GD-TFETs with varying ’In’ fraction of InxGa1-xN in the source-side channel. (a) Id-Vg curves, (b) point swing S versus Id, and (c) average SS and Ion at Vd ¼ 1 V.
TFET device with different ’In’ fraction in the InxGa1-xN source-side channel. The threshold voltage Vt is defined as the voltage at which the current is 1 107 A/mm. With 0.7, 0.75, 0.8 and 0.85 ’In’ fraction in the source-side channel, Vt of TFETs are 0.71, 0.55, 0.39, and 0.27 V, respectively. The negative shift of Vt with the increasing of ’In’ fraction originates from the narrower lateral tunneling distance. What’s more, as the ’In’ fraction x > 0.75, the proposed structure significantly improves the steepness of turn-on behavior while maintaining the low ambipolar current. At the Vg of 1 V, the ambipolar current is of the order of 1014 A/mm for all the devices. It indicates that Iambipolar of the SC-GD-TFET is not affected by the ’In’ fraction variation in the source-side channel. As Vg increases to 1 V, Ion enhancement is achieved in SC-GD-TFET with ’In’ fraction x > 0.75 over GD-TFET (x ¼ 0.75). SC-GD-TFET with x ¼ 0.85 shows Ion ¼ 1.1 104 A/mm which is 5.3 times higher than that of GD-TFET (x ¼ 0.75). Fig. 4 (b) depicts the point swing S versus Id plots extracted from Id-Vg curves in Fig. 4 (a). Point swing S refers to the reciprocal of the slope of the Id-Vg curve obtained at a specific Id. It is observed that point swing S for x ¼ 0.85 SC-GD-TFET is the smallest compared with that of the other InxGa1-xN SC-GD-TFETs at any Id. Fig. 4 (c) shows average swing S (SSavg) and Ion as a function of ’In’ fraction (x). At x ¼ 0.85, the highest Ion of 1.1 104 A/mm and the lowest SSavg of 18.2 mV/decade are
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Fig. 5. Energy band diagrams below gate oxide with different ’In’ fraction of InxGa1-xN in the source-side channel at (a) the off-state and (b) the on-state.
achieved due to the narrowing effective tunneling barrier width. Therefore, to obtain lower SSavg and higher Ion, a larger ’In’ fraction is desirable in SC-GD-TFET. Fig. 5 depicts the energy band diagrams of the device at off-state and on-state for different ’In’ fraction x in the source-side channel InxGa1-xN. As x of InxGa1-xN increases, Eg of InxGa1-xN becomes smaller. As a result, the effective tunneling barrier width between source and channel becomes narrower at the given operating condition, which increases the tunneling probability of source-to-channel BTBT. Therefore, higher on-state current is achieved. Besides, the steeper characteristic of energy bands at the source/channel interface induces the smaller SSavg. This is the reason why the larger ’In’ fraction x gets smaller SSavg as shown in Fig. 4 (c). To get a better insight into the modulation effect of the source-side channel, contour plots of the nonlocal e- BTBT rates at Vg ¼ 1 V and Vd ¼ 1 V in SC-GD-TFET with x ¼ 0.85 and GD-TFET are displayed in Fig. 6 (a) and (b), respectively. We can confirm that SC-GD-TFET achieves a higher peak e- BTBT rates than GD-TFET. The e- BTBT rate degrades with contour lines extending to the drain direction, indicating long tunneling paths have low tunneling probability. It should be noted that the magnitude
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Fig. 6. Contour plots of e- BTBT rates at Vg ¼ 1 V and Vd ¼ 1 V in (a) In0.85Ga0.15N SC-GD-TFET and (b) GD-TFET.
of e- BTBT rate for source-side channel TFET shows a sudden decrease as e- BTBT rate profile crosses the heterojunction in the channel as shown in Fig. 6 (a). The maximum e- BTBT rates centers are confined in the region of the source-side channel in In0.85Ga0.15N source-side channel TFET. It infers that the significant BTBT has to choose the short tunneling paths, which will
Fig. 7. Transfer characteristic of SC-GD-TFET with ’In’ fraction of 0.85 in the source-side channel at different Lsc. (a) Id-Vg curves. (b) Average SS and Ion as the function of Lsc.
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Fig. 8. Energy band diagrams below gate oxide near the source-channel interface with different Lsc at (a) thermal equilibrium state and (b) Vd ¼ 1 V, Vg ¼ 0.5 V.
contribute to high tunneling rate. So the confinement of BTBT in the source-side channel near the source-channel junction can elevate tunneling probability and improve the on-state current. 3.2.2. Effect of variation of source-side channel length Lsc on device performances The proposed TFET device shows optimized DC characteristics at ’In’ fraction of 0.85 with Lsc ¼ 10 nm. Fig. 7 (a) and (b) show the Id-Vg curves and DC performances for devices with different Lsc at x ¼ 0.85. As can be seen in Fig. 7 (a), SSavg is sensitive to Lsc and may have an optimum value. Besides, Ion is degraded for an extremely short Lsc (Lsc ¼ 5 nm). Both SSavg and Ion have been extracted and exhibited in Fig. 7 (b). It indicates that an optimum value of Lsc in physical designing will fall into the range between Lsc ¼ 10 nm and 20 nm. Fig. 8 shows the energy band diagrams near the source-channel interface of the SC-GD-TFET. It can be found that when Lsc becomes as thin as 5 nm, valence electrons tunneling from source to channel encounter a relatively higher barrier which hinders the BTBT. The BTBT is not yet confined in the source-side channel. Part of the electrons tunnel from the source to the drain-side channel region near the heterojunction interface. This process encounters larger tunneling distance than that occurs in the TFET Lsc 10 nm where the BTBT is confined in the source-side channel region, which consequently degrades Ion. 4. Conclusions Effect of graded InGaN drain region and ’In’ fraction in InGaN channel on performances of InGaN tunnel field-effect transistor has been researched by ATLAS simulations in this paper. Firstly, the GD-TFET is put forward to reduce Iambipolar. The graded InGaN drain increases the lateral tunnel barrier width at the channel-drain junction and reduces the BTBT tunneling rate. Iambipolar reduces from 2.0 108 A/mm in conventional TFET to 1.9 1014 A/mm in GD-TFET. Secondly, SC-GD-
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TFET with ’In’ fraction of 0.85 in source-side channel is proposed, which exhibits a higher Ion of 1.1 104 A/mm and lower SSavg of 18.2 mV/decade after adjusting ’In’ fraction in the source-side InGaN channel. The improved performances are attributed to the small band-gap of the source-side channel In0.85Ga0.15N, narrow lateral tunneling distance and steepness of the source-channel junction. The optimum value of Lsc falls into the range between Lsc ¼ 10 nm and 20 nm resulting from the DC results. The research here indicated that the proposed SC-GD-TFET embodies an appropriate candidate for low power circuit applications. Acknowledgment This work was supported by the National Natural Science Foundation of China (Grant No. 61334002 and No. 61604115). References [1] S. Borkar, Circuit techniques for subthreshold leakage avoidance, control, and tolerance, in: IEEE Int. Electron Devices (IEDM) Tech. Dig., 2004, pp. 421e424. [2] S. Bangsaruntip, G.M. Cohen, A. Majumdar, J.W. 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