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Effect of multiple scans and granular defects on excimer laser annealed polysilicon TFTs
PERGAMON
Solid-State Electronics 43 (1999) 305±313
Eect of multiple scans and granular defects on excimer laser annealed polysilicon TFTs Aaron M. Marmorstein a, Apostolos T. Voutsas b, Raj Solanki a, * a
Oregon Graduate Institute, Department of Electrical and Computer Engineering, P.O. Box 91000, Portland, OR 97291-1000, USA b Sharp Microelectronics Technology Inc., 5700 NW Paci®c Rim Boulevard, Camas, WA 98607, USA Received 13 March 1998; received in revised form 22 June 1998
Abstract A thorough investigation of excimer laser annealed polycrystalline silicon thin ®lm transistors fabricated from single and multiple laser scan processes has been completed. Our results show that even though multiple scans can enhance the grain size in the polycrystalline silicon ®lm, the production of intragrain defects and interface trapping states have adverse eects on the performance of the corresponding devices and in particular, on the leakage current, threshold voltage and subthreshold swing. Further investigation revealed substantial changes in the sourcedrain current activation energy, as a function of the number of scans. Using our experimental data, coupled with theoretical analysis, we were able to examine to what degree intragrain and grain boundary mobilities determine the overall ®eld eect mobility of the device. A transition region, based on the grain boundary barrier height, was identi®ed separating annealing conditions for which the carrier scattering in the grains or the carrier scattering at the grain boundaries dominated the conduction process. # 1998 Elsevier Science Ltd. All rights reserved.
1. Introduction Polycrystalline silicon (p-Si) thin ®lm transistors (TFTs) have been extensively investigated, especially for their use in active-matrix liquid crystal displays [1]. Of the dierent techniques available to prepare p-Si, excimer laser annealing (ELA) of amorphous silicon has proven to be the most capable of producing high quality TFTs [2]. Because the mobilities of devices made with ELA crystallized p-Si are much higher than devices made using either solid phase crystallization (SPC) or deposited p-Si, the creation of displays with faster switching speeds and driver circuitry integrated directly on the display substrate is possible. The goal of many researchers optimizing a p-Si laser annealing process, is to maximize the grain size of the ®lm because, in most cases, larger grains lead to better device characteristics [3]. Two methods to create large
* Corresponding author. Tel.: +1-503-690-1168; Fax: +1503-690-1406; E-mail: [email protected]
grains by ELA are application of a single scan (single pass) with a laser energy density which maximizes the average grain size or application of multiple scans (multiple passes) using a lower energy density. For single scans, the creation of very large grains requires a near complete melting of the irradiated area, down to the substrate. However, even with a 96% beam overlap, the resultant p-Si layer typically has a wide distribution of grain sizes, due to the inherent pulse-topulse variations associated with excimer lasers [4]. If the energy density of a particular pulse is high enough to melt the ®lm entirely, the reduction in the number of nucleation sites can lead to the creation of small crystallites through homogenous nucleation of the molten layer after it has become signi®cantly supercooled [5]. Multiple scans avoid this problem by increasing the grain size gradually. In so doing, large grains are formed as grains from previous scans conglomerate. What is unclear though, is how the corresponding TFT performance will compare for a single scan and multiple scan process.
0038-1101/98/$ - see front matter # 1998 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 9 8 ) 0 0 2 4 9 - 4
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A.M. Marmorstein et al. / Solid-State Electronics 43 (1999) 305±313
In this investigation, we have examined the characteristics of n-channel p-Si TFTs, annealed by a single and multiscan ELA process. Though the use of multiple scans to produce large grains in p-Si material has been previously studied [4, 6], the eect on device performance is not fully understood. TFTs were fabricated using laser-crystallized p-Si at conditions identi®ed and optimized in our previous work [4]. Devices were characterized extensively and it was found that the grain size itself was not the only attribute determining device performance, especially for multiscan ELA. Our materials analysis suggests that the quality of the grains is a sensitive function of the annealing conditions and that, under certain circumstances, advantages derived from larger grains can be eectively overtaken by increasing intragrain defects and interface trapping states, resulting in poorer transistor performance. New results showing the eects of multiple scans on activation energy, threshold voltage and subthreshold swing are also presented.
electron microscopy (TEM). N-channel TFTs, having a top-metal-gate structure, were fabricated using a four mask process. The TFTs were characterized using a Hewlett Packard 4156A semiconductor analyzer. Seventy-®ve 5 5 mm devices were measured for each laser annealing condition, to ensure accurate statistics for the device characteristics. The majority of the measurements consisted of ID±VG data taken at room temperature with VDS = 0.1 V, where the gate voltage was varied from +20 to ÿ20 V. For selected devices, measurements were made at elevated temperatures from 20 to 1008C. By using a linear ®t of a ln(ID) vs. 1/kT plot, where T is the absolute temperature and k is the Boltzmann constant, the source-drain current activation energy was determined. Device characterization was performed both before and after a postfabrication hydrogenation step. Unless otherwise stated, results are for prehydrogenation. 3. Results
2. Experimental Polysilicon TFTs were fabricated on quartz substrates with a 200 nm thick SiO2 barrier layer. The barrier layer serves both to increase the grain size in the p-Si ®lm and to prevent impurity segregation from the substrate [4]. 50 nm of amorphous silicon was deposited on the barrier layer, using plasma enhanced chemical vapor deposition (PECVD), at a deposition rate of 60 nm/min and a temperature of 3908C. To remove excess hydrogen, which could lead to ablation upon crystallization, samples were preheated to 4508C for 3 h in a diusion furnace, under nitrogen ¯ow. The laser annealing took place in an evacuated chamber, at a pressure of 1 mTorr and a temperature of 4008C. Pulses from a XeCl excimer laser (308 nm) operating at 35 Hz were used to crystallize the amorphous silicon. The beam was passed through a homogenizer and focused down to a spot size of 5 6 mm. Samples were scanned with the laser from 1 to 8 times, using a 96% overlap from pulse to pulse. The grain size in the resulting p-Si ®lm was determined by transmission
Table 1 displays the important device parameters, along with the average grain sizes, for samples scanned one time at dierent energy densities. For these samples, there was a steady improvement in all the pertinent characteristics as the average grain size increased with the laser energy density, within the speci®ed range. Characteristics for devices formed with a multiscan process are also shown in Table 1. In contrast to the previous case, the on±o-current ratio, subthreshold swing and leakage current degraded markedly, despite the increase in average grain size. Moreover, the threshold voltage became decidedly negative. Comparing the average mobility of samples annealed at 305 (eight passes) and 335 mJ/cm2 (one pass), despite the larger grain size in the former case, the device performance was poorer. The reasons for these eects were not immediately clear. Through extensive materials analysis, we were able to determine that, even though the grain size in the pSi ®lm was increasing with each scan, artifacts from previous scans remained in the interior of the newly
Table 1. Average device parameters and grain sizes (GS) for p-Si TFTs Number of scans
Energy density (mJ/cm2)
GS (nm)
Mobility (cm2/Vs)
Vth (V)
Leakage current (A)
Log (IOn/IO)
Sub. Swing (V/dec)
1 1 1 2 4 8
275 305 335 305 305 305
90 330 530 390 500 600
95 151 217 179 194 212
2.36 1.16 0.53 0.90 ÿ0.04 ÿ0.8
1.21 10 ÿ 12 8.00 10 ÿ 13 1.90 10 ÿ 13 8.25 10 ÿ 13 3.02 10 ÿ 12 2.46 10 ÿ 11
6.67 7.14 7.96 7.08 6.61 5.72
0.90 0.73 0.65 0.79 1.05 1.68
A.M. Marmorstein et al. / Solid-State Electronics 43 (1999) 305±313
formed grains. In a multiscan process, large grains develop as grains from previous scans conglomerate, often without complete elimination of the original grain boundaries. The original grain boundaries can act as intragrain defects and thus hinder device performance. Residual intragrain subboundaries from a sample scanned eight times can be seen by atomic force microscopy (AFM), as shown in Fig. 1. Similar defects can be seen in the TEM image of Fig. 2. A thorough explanation for this phenomenon is presented elsewhere [4].
307
Previous studies of p-Si TFTs fabricated with SPC suggest the dominance of intragrain defects over grain boundary defects with respect to their eect on carrier transport in the channel [7, 8]. A recent work, however, points out that for suciently low intragrain defect density, the carrier mobility can become grain boundary trap limited [9]. Typically, this is the case for ELA p-Si material, where the intragrain defect density tends to be very low, resulting in fast carrier transport within the grains.
Fig. 1. AFM image of ELA p-Si showing large grains conglomerated from smaller grains in a sample scanned eight times at 305 mJ/cm2. Subboundaries and point-like defects are visible throughout the grains. Arrow (a) indicates a primary grain boundary. Arrow (b) points to a point-like defect. Arrow (c) is showing subboundaries formed from partially conglomerated grains. The measured area was 10 10 mm.
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Fig. 2. TEM image of ELA p-Si showing large grains of a sample scanned eight times at 305 mJ/cm2. Defects resulting from grains conglomerated from previous scans are evident throughout the image, as both subboundaries and point-like defects. The point-like defects often form in a regular array, as in the ®gure. Two such defects are indicated by the arrows.
To investigate the mobility variations as a function of the annealing conditions, we used the method proposed by Levinson et al. to evaluate the trap density at the grain boundaries [10]. Based on this formulation, the potential barrier height at the grain boundary is given by Eq. (1) q3 N 2t dch EB , 8 COX VG eSi
1
where EB is the potential barrier height, q is the electronic charge, Nt is the grain boundary trap density, dch is the induced channel thickness (assumed to be 10 nm), eSi is the dielectric constant of Si, COX is the capacitance of the gate insulator, and VG is the applied gate voltage. Levinson et al. assumed a grain boundary mobility of the form shown in Eq. (2) mGB m0 exp ÿEB =kT ,
2
where k is the Boltzmann constant, T is the absolute
temperature and m0 is a pre-factor. Thus the total mobility in the channel, being a function of scattering occurring within the grains and at the grain boundaries, can be expressed as 1=mCH 1=mG 1=mGB ,
3
where mCH is the total mobility, mG is the intragrain mobility and mGB is the mobility at the grain boundary. Based on Levinson's model, the grain boundary trap density (Nt) was calculated from the slope of ln(ID/VG) vs. (1/VG). Furthermore, the intercept of this line was used to calculate the parameter m0 in Eq. (2). A plot of the ®eld eect mobility versus trap density at the grain boundary is shown in Fig. 3. It is evident from the ®gure, that as a general trend, the mobility and trap density were inversely related. Notice, however, the distinction between single-pass and multipass ELA. For the same trap density, ®lms annealed by multipass ELA, with more than four passes, demonstrated a
A.M. Marmorstein et al. / Solid-State Electronics 43 (1999) 305±313
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Fig. 3. Field eect mobility as a function of grain boundary (GB) trap density for devices made from single and multiscan ELA processes. The devices made from single scans were annealed at, from right to left, 275, 305 and 335 mJ/cm2, respectively. The devices made from multiple scans were annealed using 305 mJ/cm2, from right to left, 2, 4 and 8 scans respectively.
lower mobility than ®lms annealed by single pass ELA at a higher energy density. For example, the average mobility of the devices annealed at 335 mJ/cm2 (one pass) was higher than the average mobility of the ®lm annealed at 305 mJ/cm2 (eight passes). This is a very interesting result, in light of the fact that the latter ®lm had a lower grain boundary defect density and a larger average grain size. As we have suggested above, a multipass ELA process increases the defect density within the grains. Since a higher number of defects decreases
the mobility along the length of the grain, and because the grains were becoming larger, it is likely that the transport of carriers became intragrain limited as the ®lm was subjected to more passes. To assess the validity of this hypothesis, we evaluated the magnitude of the grain boundary potential barrier height at the value of the gate voltage, corresponding to the peak in the transconductance for VDS = 0.1 V. These results are shown in Fig. 4, where the TFT mobility is plotted as a function of the barrier
Fig. 4. TFT channel mobility as a function of the potential barrier height at the grain boundary (GB) for devices made from single and multiscan ELA processes. Samples in the intragrain limited regime (black circles) were scanned, from right to left, 2 times, 4 times and 8 times, respectively at 305 mJ/cm2. The samples in the grain boundary limited regime (white circles) were scanned one time at, from right to left, 275 mJ/cm2, 305 mJ/cm2 and 335 mJ/cm2 respectively. Also shown is the transition band separating the regimes where mobility is limited by intragrain or grain boundary defects.
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A.M. Marmorstein et al. / Solid-State Electronics 43 (1999) 305±313
height. It is evident that even though the grain boundary barrier height was signi®cantly decreased for the case of the multipass process, the TFT mobility was not correspondingly increased. Since lower grain boundary barriers strengthen the in¯uence of the intragrain defects, the conduction was intragrain limited in this case, while for high barrier heights, it was grain boundary limited. Based on our data, a transition band, separating these two regimes was identi®ed in the range of 0.0097±0.0107 eV. This range is close to the value for the potential barrier height reported by other authors, for a similar transition [11]. This previous study concluded, that grain boundaries dominated the carrier transport in the channel when the grain boundary potential barrier height was larger than 0.0124 eV. Using the experimentally measured TFT mobility and the calculated grain boundary mobility from Eq. (2), we performed an order of magnitude calculation of the ratio mG/mGB, using Eq. (3). Fig. 5 plots this ratio as a function of the potential barrier height at the grain boundary. As expected, in the intragrain limited regime, the ratio decreased with decreasing barrier height, con®rming the increasing importance of intragrain defects in the conduction process. An extreme in this regime would be a TFT dominated by intragrain defects, as from SPC p-Si. At the other extreme, it is anticipated that the barrier height will saturate as the size of the associated depletion regions approach the size of the grains. At this point, the carrier density will be greatly reduced and the ®eld eect mobility will be correspondingly low.
Referring back to Table 1, notice that the average value of the subthreshold swing (S) increased by more than a factor of 2 for the samples scanned eight times as compared to the samples scanned once. This behavior was unexpected, because in most cases, S improves as the grain size increases. In general, S is de®ned as in Eq. (4) S ln 10
dVG : d ln ID
Eq. (4) can be rewritten as Eq. (5) [12] kT CD Cit ln 10 1 S , q COX
4
5
where Cit = qDit, Dit is the interface trap density, and CD is the depletion layer capacitance. From this relation, it can be inferred that an increase in Dit for the samples scanned multiple times, may have served to increase S, and as we will show, other evidence supports this claim. Often times, approximate values for Dit are derived directly from the subthreshold slope [12±14]. One such method involves looking at DS. In so doing, it is assumed that the depletion layer capacitance is approximately the same for two samples, one of which has a low interface trap density. If this is true, Dit can be solved for as in (6) Dit
COX q DS: ln 10 kT q
6
Fig. 5. Ratio of intragrain mobility (mG) to the grain boundary mobility (mGB) as a function of the potential barrier height at the grain boundary (GB). White circles represent samples scanned one time at, from right to left, 275, 305 and 335 mJ/cm2, respectively. Black circles represent samples scanned, from right to left, two times, four times and eight times respectively at 305 mJ/cm2. Also shown is the transition band separating the regimes where mobility is limited by intragrain or grain boundary defects.
A.M. Marmorstein et al. / Solid-State Electronics 43 (1999) 305±313
311
Fig. 6. Relationship between grain boundary (GB) trap density and threshold voltage for ELA p-Si TFTs made from a single and multiscan process. Black circles represent samples scanned, from right to left, two times, four times and eight times, respectively at 305 mJ/cm2. White circles represent samples scanned one time at, from right to left, 275, 305 and 335 mJ/cm2 respectively.
To apply this equation, we used the average S (S = 0.567 V/dec.) for the wafer scanned one time at 305 mJ/cm2, after hydrogen passivation was performed, as our reference sample with a low level of interface traps. From this, we determined that Dit gradually increased from 5.86 1011/cm2 eV after one scan to 4.00 1012/cm2 eV after eight scans. The relationship between the grain boundary trap density and threshold voltage (Vth) is shown in Fig. 6. As a general trend, and in agreement with previous studies, the threshold voltage decreased as the trap density decreased [15]. Notice, however, that the threshold voltage for multiscans became increasingly negative at a higher rate in relation to the grain boundary trap density than for single scans. In addition, the samples scanned eight times had an average Vth well below 0 V. These eects can be explained if it is assumed that a majority of the interface traps, as described above, are donorlike in nature (positive when unoccupied and neutral when ®lled with an electron), resulting in a net positive layer of interfacial charge, the magnitude of which is a function of the gate voltage. It is also important to note that Vth increased following hydrogenation of the wafer scanned eight times, for devices with negative threshold values. After measuring 15 TFTs where the average Vth was equal to ÿ2.16 V before hydrogenation, it rose to ÿ1.52 V after. In most cases, because hydrogen reduces the number of dangling bonds, the threshold voltage decreases for n-type devices following hydrogenation [16]. However, in the case of donorlike interfacial traps, a reduction in their number would increase Vth.
By making ID±VG measurements at various temperatures, the source-drain current activation energy of each annealing condition, as a function of gate voltage was also determined, and is shown in Fig. 7. The steady decrease in the activation energy with each scan suggests that the Fermi level is moving progressively closer to the conduction band edge. This can be accounted for by either a growing layer of positive interfacial charge or accumulation of n-type dopant in the channel. The dopant could only come from the source and drain regions, but series resistance measurements have con®rmed that this is not the case. It is also possible that incorporated oxygen is acting as a thermal donor, and as the oxygen level increases with each scan, the eect is magni®ed. However, this same drop in activation energy is not witnessed for TFTs laser annealed in air, thus disarming this theory. This leaves interfacial charge due to the presence of traps as the likely culprit. The charge would have the eect of drawing electrons to the surface of the channel, shifting the Fermi level in the bandgap towards the conduction band, and thus lowering the activation energy. Interfacial traps may also be responsible for the increase in leakage current, which occurred for samples scanned multiple times, as shown in Table 1. It is widely believed trap assisted thermionic ®eld emission in the high electric ®eld region near the drain contact is responsible for the anomalously high o-current in p-Si TFTs, for low drain-source voltages [17]. Interface traps introduce allowable energy levels in the bandgap at the p-Si/SiO2 interface, which serve to increase leakage current.
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Fig. 7. Source-drain current activation energy as a function of gate voltage for ELA p-Si TFTs scanned one, two, four and eight times at 305 mJ/cm2.
4. Conclusion Through this investigation, we were able to determine the eects of multiple scans on laser annealed pSi TFTs. Comparison to devices made from single scans revealed that the subthreshold slope and leakage current were aected adversely by multiple scans. In addition, the increase in mobility in relation to grain size was not as profound as for single scans. The changes which occurred within the devices could be explained by an increase in the intragrain defect density and an increase in the magnitude of the p-Si/SiO2 interfacial trap density. This investigation also revealed the subtle interplay between the eect of grain boundary and intragrain defects on mobility. Under certain conditions, maximizing the grain size may not lead to enhanced device performance, if its accompanied by an increase in intragranular defects. Even for ELA, where the intragrain defect density is typically low, carrier mobility may still be signi®cantly aected by scattering within the grain itself. A regime exists, determined by the grain boundary barrier height, separating under what conditions intragrain or grain boundary defects dominate the conduction process. If the grain boundary barrier height is low, intragrain mobility, as controlled by intragrain defects, will play an enhanced role. If the barrier height is high, the grain boundaries will dominate the transport of carriers.
References [1] Peter Brody T. The thin ®lm transistor: a late ¯owering bloom. IEEE Trans Elec Dev 1984;ED-31(11):1614. [2] Plais F, Legagneus P, Reita C, Huet O, Petinot F, Oribat D, Godard B, Stehle M, Fogarassy E. Low temperature polysilicon TFTs: a comparison of solid phase and laser crystallization. Microelectr Eng 1995;28:443. [3] Mei P, Boyce JB, Hack M, Lujan R, Ready SE, Fork DK, Johnson RI, Anderson GB. Grain growth in laser dehydrogenated and crystallized polycrystalline silicon for thin ®lm transistors. J Appl Phys 1994;76(5):3194. [4] Marmorstein A, Voutsas AT, Solanki R. A systematic study and optimization of parameters aecting grain size and surface roughness in excimer laser annealed polysilicon thin ®lms. J Appl Phys 1997;82:4303. [5] Im JS, Kim HJ, Thompson MO. Phase transformation mechanisms involved in excimer laser crystallization of amorphous silicon ®lms. Appl Phys Lett 1993;63(14):1969. [6] Kuriyama H, Kiyama S, Noguchi S, Kuwahara T, Ishida S, Nohda T, Sano K, Iwata H, Kawata H, Osumi M, Tsuda S, Nakano S, Kuwana Y. Enlargement of poly-si ®lm grain size by excimer laser annealing and its application to high-performance poly-si thin ®lm transistor. Jpn J Appl Phys 1991;30:3700. [7] Wu I-W, Huang T-Y, Jackson WB, Lewis AG, Chiang A. Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation. IEEE Elec Dev Lett 1991;12(4):181. [8] Kim YS, Choi KY, Han MK. Dierent hydrogen passivation mechanisms between low-temperature and high-
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[9]
[10]
[11]
[12] [13]
temperature poly-Si TFTs. Part 1. Jpn J Appl Phys 1995;34(2B):719. Morimoto Y, Jinno Y, Hirai K, Ogata H, Yamada T, Yoneda K. In¯uence of the grain boundaries and intragrain defects on the performance of poly-Si thin ®lm transistors. J Electrochem Soc 1997;144(7):2495. Levinson J, Shepherd FR, Scanlon PJ, Westwood WD, Este G, Rider M. Conductivity behavior in polycrystalline semiconductor thin ®lm transistors. J Appl Phys 1982;53(2):1193. Seki S, Kogure O, Tsujiyama B. A semi-empirical model for the ®eld-eect mobility of hydrogenated polycrystalline-silicon MOSFET's. IEEE Trans Elec Dev 1988;35(5):669. Sah, C.-T. Fundamentals of Solid-State Electronics. World Scienti®c Publishing, Singapore, 1991, p. 661. Noguchi T, Hayashi H, Oshima T. Low temperature polysilicon super-thin-®lm transistor (LSFT). Jpn J Appl Phys 1986;25(2):L121.
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[14] Dimitriadis C, Coxon P, Dozsa L, Papadimitriou L, Economou N. Performance of thin-®lm transistors on polysilicon ®lms grown by low-pressure chemical vapor deposition at various pressures. IEEE Trans Elec Dev 1992;39(3):598. [15] Kong H-S, Lee C. Two-dimensional simulation study of ®eld-eect operation in undoped poly-Si thin-®lm transistors. J Appl Phys 1995;78(10):6122. [16] Wu I-W, Huang T-Y, Jackson WB, Lewis AG, Chiang A. Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation. IEEE Elec Dev Lett 1991;12(4):181. [17] Migliorato P, Reita C, Tallarida G, Quinn M, Fortunato G. Anomalous o-current mechanisms in n-channel polySi thin ®lm transistors. Solid-State Electron 1995;38(12):2075.
Solid-State Electronics 43 (1999) 305±313
Eect of multiple scans and granular defects on excimer laser annealed polysilicon TFTs Aaron M. Marmorstein a, Apostolos T. Voutsas b, Raj Solanki a, * a
Oregon Graduate Institute, Department of Electrical and Computer Engineering, P.O. Box 91000, Portland, OR 97291-1000, USA b Sharp Microelectronics Technology Inc., 5700 NW Paci®c Rim Boulevard, Camas, WA 98607, USA Received 13 March 1998; received in revised form 22 June 1998
Abstract A thorough investigation of excimer laser annealed polycrystalline silicon thin ®lm transistors fabricated from single and multiple laser scan processes has been completed. Our results show that even though multiple scans can enhance the grain size in the polycrystalline silicon ®lm, the production of intragrain defects and interface trapping states have adverse eects on the performance of the corresponding devices and in particular, on the leakage current, threshold voltage and subthreshold swing. Further investigation revealed substantial changes in the sourcedrain current activation energy, as a function of the number of scans. Using our experimental data, coupled with theoretical analysis, we were able to examine to what degree intragrain and grain boundary mobilities determine the overall ®eld eect mobility of the device. A transition region, based on the grain boundary barrier height, was identi®ed separating annealing conditions for which the carrier scattering in the grains or the carrier scattering at the grain boundaries dominated the conduction process. # 1998 Elsevier Science Ltd. All rights reserved.
1. Introduction Polycrystalline silicon (p-Si) thin ®lm transistors (TFTs) have been extensively investigated, especially for their use in active-matrix liquid crystal displays [1]. Of the dierent techniques available to prepare p-Si, excimer laser annealing (ELA) of amorphous silicon has proven to be the most capable of producing high quality TFTs [2]. Because the mobilities of devices made with ELA crystallized p-Si are much higher than devices made using either solid phase crystallization (SPC) or deposited p-Si, the creation of displays with faster switching speeds and driver circuitry integrated directly on the display substrate is possible. The goal of many researchers optimizing a p-Si laser annealing process, is to maximize the grain size of the ®lm because, in most cases, larger grains lead to better device characteristics [3]. Two methods to create large
* Corresponding author. Tel.: +1-503-690-1168; Fax: +1503-690-1406; E-mail: [email protected]
grains by ELA are application of a single scan (single pass) with a laser energy density which maximizes the average grain size or application of multiple scans (multiple passes) using a lower energy density. For single scans, the creation of very large grains requires a near complete melting of the irradiated area, down to the substrate. However, even with a 96% beam overlap, the resultant p-Si layer typically has a wide distribution of grain sizes, due to the inherent pulse-topulse variations associated with excimer lasers [4]. If the energy density of a particular pulse is high enough to melt the ®lm entirely, the reduction in the number of nucleation sites can lead to the creation of small crystallites through homogenous nucleation of the molten layer after it has become signi®cantly supercooled [5]. Multiple scans avoid this problem by increasing the grain size gradually. In so doing, large grains are formed as grains from previous scans conglomerate. What is unclear though, is how the corresponding TFT performance will compare for a single scan and multiple scan process.
0038-1101/98/$ - see front matter # 1998 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 9 8 ) 0 0 2 4 9 - 4
306
A.M. Marmorstein et al. / Solid-State Electronics 43 (1999) 305±313
In this investigation, we have examined the characteristics of n-channel p-Si TFTs, annealed by a single and multiscan ELA process. Though the use of multiple scans to produce large grains in p-Si material has been previously studied [4, 6], the eect on device performance is not fully understood. TFTs were fabricated using laser-crystallized p-Si at conditions identi®ed and optimized in our previous work [4]. Devices were characterized extensively and it was found that the grain size itself was not the only attribute determining device performance, especially for multiscan ELA. Our materials analysis suggests that the quality of the grains is a sensitive function of the annealing conditions and that, under certain circumstances, advantages derived from larger grains can be eectively overtaken by increasing intragrain defects and interface trapping states, resulting in poorer transistor performance. New results showing the eects of multiple scans on activation energy, threshold voltage and subthreshold swing are also presented.
electron microscopy (TEM). N-channel TFTs, having a top-metal-gate structure, were fabricated using a four mask process. The TFTs were characterized using a Hewlett Packard 4156A semiconductor analyzer. Seventy-®ve 5 5 mm devices were measured for each laser annealing condition, to ensure accurate statistics for the device characteristics. The majority of the measurements consisted of ID±VG data taken at room temperature with VDS = 0.1 V, where the gate voltage was varied from +20 to ÿ20 V. For selected devices, measurements were made at elevated temperatures from 20 to 1008C. By using a linear ®t of a ln(ID) vs. 1/kT plot, where T is the absolute temperature and k is the Boltzmann constant, the source-drain current activation energy was determined. Device characterization was performed both before and after a postfabrication hydrogenation step. Unless otherwise stated, results are for prehydrogenation. 3. Results
2. Experimental Polysilicon TFTs were fabricated on quartz substrates with a 200 nm thick SiO2 barrier layer. The barrier layer serves both to increase the grain size in the p-Si ®lm and to prevent impurity segregation from the substrate [4]. 50 nm of amorphous silicon was deposited on the barrier layer, using plasma enhanced chemical vapor deposition (PECVD), at a deposition rate of 60 nm/min and a temperature of 3908C. To remove excess hydrogen, which could lead to ablation upon crystallization, samples were preheated to 4508C for 3 h in a diusion furnace, under nitrogen ¯ow. The laser annealing took place in an evacuated chamber, at a pressure of 1 mTorr and a temperature of 4008C. Pulses from a XeCl excimer laser (308 nm) operating at 35 Hz were used to crystallize the amorphous silicon. The beam was passed through a homogenizer and focused down to a spot size of 5 6 mm. Samples were scanned with the laser from 1 to 8 times, using a 96% overlap from pulse to pulse. The grain size in the resulting p-Si ®lm was determined by transmission
Table 1 displays the important device parameters, along with the average grain sizes, for samples scanned one time at dierent energy densities. For these samples, there was a steady improvement in all the pertinent characteristics as the average grain size increased with the laser energy density, within the speci®ed range. Characteristics for devices formed with a multiscan process are also shown in Table 1. In contrast to the previous case, the on±o-current ratio, subthreshold swing and leakage current degraded markedly, despite the increase in average grain size. Moreover, the threshold voltage became decidedly negative. Comparing the average mobility of samples annealed at 305 (eight passes) and 335 mJ/cm2 (one pass), despite the larger grain size in the former case, the device performance was poorer. The reasons for these eects were not immediately clear. Through extensive materials analysis, we were able to determine that, even though the grain size in the pSi ®lm was increasing with each scan, artifacts from previous scans remained in the interior of the newly
Table 1. Average device parameters and grain sizes (GS) for p-Si TFTs Number of scans
Energy density (mJ/cm2)
GS (nm)
Mobility (cm2/Vs)
Vth (V)
Leakage current (A)
Log (IOn/IO)
Sub. Swing (V/dec)
1 1 1 2 4 8
275 305 335 305 305 305
90 330 530 390 500 600
95 151 217 179 194 212
2.36 1.16 0.53 0.90 ÿ0.04 ÿ0.8
1.21 10 ÿ 12 8.00 10 ÿ 13 1.90 10 ÿ 13 8.25 10 ÿ 13 3.02 10 ÿ 12 2.46 10 ÿ 11
6.67 7.14 7.96 7.08 6.61 5.72
0.90 0.73 0.65 0.79 1.05 1.68
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formed grains. In a multiscan process, large grains develop as grains from previous scans conglomerate, often without complete elimination of the original grain boundaries. The original grain boundaries can act as intragrain defects and thus hinder device performance. Residual intragrain subboundaries from a sample scanned eight times can be seen by atomic force microscopy (AFM), as shown in Fig. 1. Similar defects can be seen in the TEM image of Fig. 2. A thorough explanation for this phenomenon is presented elsewhere [4].
307
Previous studies of p-Si TFTs fabricated with SPC suggest the dominance of intragrain defects over grain boundary defects with respect to their eect on carrier transport in the channel [7, 8]. A recent work, however, points out that for suciently low intragrain defect density, the carrier mobility can become grain boundary trap limited [9]. Typically, this is the case for ELA p-Si material, where the intragrain defect density tends to be very low, resulting in fast carrier transport within the grains.
Fig. 1. AFM image of ELA p-Si showing large grains conglomerated from smaller grains in a sample scanned eight times at 305 mJ/cm2. Subboundaries and point-like defects are visible throughout the grains. Arrow (a) indicates a primary grain boundary. Arrow (b) points to a point-like defect. Arrow (c) is showing subboundaries formed from partially conglomerated grains. The measured area was 10 10 mm.
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Fig. 2. TEM image of ELA p-Si showing large grains of a sample scanned eight times at 305 mJ/cm2. Defects resulting from grains conglomerated from previous scans are evident throughout the image, as both subboundaries and point-like defects. The point-like defects often form in a regular array, as in the ®gure. Two such defects are indicated by the arrows.
To investigate the mobility variations as a function of the annealing conditions, we used the method proposed by Levinson et al. to evaluate the trap density at the grain boundaries [10]. Based on this formulation, the potential barrier height at the grain boundary is given by Eq. (1) q3 N 2t dch EB , 8 COX VG eSi
1
where EB is the potential barrier height, q is the electronic charge, Nt is the grain boundary trap density, dch is the induced channel thickness (assumed to be 10 nm), eSi is the dielectric constant of Si, COX is the capacitance of the gate insulator, and VG is the applied gate voltage. Levinson et al. assumed a grain boundary mobility of the form shown in Eq. (2) mGB m0 exp ÿEB =kT ,
2
where k is the Boltzmann constant, T is the absolute
temperature and m0 is a pre-factor. Thus the total mobility in the channel, being a function of scattering occurring within the grains and at the grain boundaries, can be expressed as 1=mCH 1=mG 1=mGB ,
3
where mCH is the total mobility, mG is the intragrain mobility and mGB is the mobility at the grain boundary. Based on Levinson's model, the grain boundary trap density (Nt) was calculated from the slope of ln(ID/VG) vs. (1/VG). Furthermore, the intercept of this line was used to calculate the parameter m0 in Eq. (2). A plot of the ®eld eect mobility versus trap density at the grain boundary is shown in Fig. 3. It is evident from the ®gure, that as a general trend, the mobility and trap density were inversely related. Notice, however, the distinction between single-pass and multipass ELA. For the same trap density, ®lms annealed by multipass ELA, with more than four passes, demonstrated a
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309
Fig. 3. Field eect mobility as a function of grain boundary (GB) trap density for devices made from single and multiscan ELA processes. The devices made from single scans were annealed at, from right to left, 275, 305 and 335 mJ/cm2, respectively. The devices made from multiple scans were annealed using 305 mJ/cm2, from right to left, 2, 4 and 8 scans respectively.
lower mobility than ®lms annealed by single pass ELA at a higher energy density. For example, the average mobility of the devices annealed at 335 mJ/cm2 (one pass) was higher than the average mobility of the ®lm annealed at 305 mJ/cm2 (eight passes). This is a very interesting result, in light of the fact that the latter ®lm had a lower grain boundary defect density and a larger average grain size. As we have suggested above, a multipass ELA process increases the defect density within the grains. Since a higher number of defects decreases
the mobility along the length of the grain, and because the grains were becoming larger, it is likely that the transport of carriers became intragrain limited as the ®lm was subjected to more passes. To assess the validity of this hypothesis, we evaluated the magnitude of the grain boundary potential barrier height at the value of the gate voltage, corresponding to the peak in the transconductance for VDS = 0.1 V. These results are shown in Fig. 4, where the TFT mobility is plotted as a function of the barrier
Fig. 4. TFT channel mobility as a function of the potential barrier height at the grain boundary (GB) for devices made from single and multiscan ELA processes. Samples in the intragrain limited regime (black circles) were scanned, from right to left, 2 times, 4 times and 8 times, respectively at 305 mJ/cm2. The samples in the grain boundary limited regime (white circles) were scanned one time at, from right to left, 275 mJ/cm2, 305 mJ/cm2 and 335 mJ/cm2 respectively. Also shown is the transition band separating the regimes where mobility is limited by intragrain or grain boundary defects.
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height. It is evident that even though the grain boundary barrier height was signi®cantly decreased for the case of the multipass process, the TFT mobility was not correspondingly increased. Since lower grain boundary barriers strengthen the in¯uence of the intragrain defects, the conduction was intragrain limited in this case, while for high barrier heights, it was grain boundary limited. Based on our data, a transition band, separating these two regimes was identi®ed in the range of 0.0097±0.0107 eV. This range is close to the value for the potential barrier height reported by other authors, for a similar transition [11]. This previous study concluded, that grain boundaries dominated the carrier transport in the channel when the grain boundary potential barrier height was larger than 0.0124 eV. Using the experimentally measured TFT mobility and the calculated grain boundary mobility from Eq. (2), we performed an order of magnitude calculation of the ratio mG/mGB, using Eq. (3). Fig. 5 plots this ratio as a function of the potential barrier height at the grain boundary. As expected, in the intragrain limited regime, the ratio decreased with decreasing barrier height, con®rming the increasing importance of intragrain defects in the conduction process. An extreme in this regime would be a TFT dominated by intragrain defects, as from SPC p-Si. At the other extreme, it is anticipated that the barrier height will saturate as the size of the associated depletion regions approach the size of the grains. At this point, the carrier density will be greatly reduced and the ®eld eect mobility will be correspondingly low.
Referring back to Table 1, notice that the average value of the subthreshold swing (S) increased by more than a factor of 2 for the samples scanned eight times as compared to the samples scanned once. This behavior was unexpected, because in most cases, S improves as the grain size increases. In general, S is de®ned as in Eq. (4) S ln 10
dVG : d ln ID
Eq. (4) can be rewritten as Eq. (5) [12] kT CD Cit ln 10 1 S , q COX
4
5
where Cit = qDit, Dit is the interface trap density, and CD is the depletion layer capacitance. From this relation, it can be inferred that an increase in Dit for the samples scanned multiple times, may have served to increase S, and as we will show, other evidence supports this claim. Often times, approximate values for Dit are derived directly from the subthreshold slope [12±14]. One such method involves looking at DS. In so doing, it is assumed that the depletion layer capacitance is approximately the same for two samples, one of which has a low interface trap density. If this is true, Dit can be solved for as in (6) Dit
COX q DS: ln 10 kT q
6
Fig. 5. Ratio of intragrain mobility (mG) to the grain boundary mobility (mGB) as a function of the potential barrier height at the grain boundary (GB). White circles represent samples scanned one time at, from right to left, 275, 305 and 335 mJ/cm2, respectively. Black circles represent samples scanned, from right to left, two times, four times and eight times respectively at 305 mJ/cm2. Also shown is the transition band separating the regimes where mobility is limited by intragrain or grain boundary defects.
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311
Fig. 6. Relationship between grain boundary (GB) trap density and threshold voltage for ELA p-Si TFTs made from a single and multiscan process. Black circles represent samples scanned, from right to left, two times, four times and eight times, respectively at 305 mJ/cm2. White circles represent samples scanned one time at, from right to left, 275, 305 and 335 mJ/cm2 respectively.
To apply this equation, we used the average S (S = 0.567 V/dec.) for the wafer scanned one time at 305 mJ/cm2, after hydrogen passivation was performed, as our reference sample with a low level of interface traps. From this, we determined that Dit gradually increased from 5.86 1011/cm2 eV after one scan to 4.00 1012/cm2 eV after eight scans. The relationship between the grain boundary trap density and threshold voltage (Vth) is shown in Fig. 6. As a general trend, and in agreement with previous studies, the threshold voltage decreased as the trap density decreased [15]. Notice, however, that the threshold voltage for multiscans became increasingly negative at a higher rate in relation to the grain boundary trap density than for single scans. In addition, the samples scanned eight times had an average Vth well below 0 V. These eects can be explained if it is assumed that a majority of the interface traps, as described above, are donorlike in nature (positive when unoccupied and neutral when ®lled with an electron), resulting in a net positive layer of interfacial charge, the magnitude of which is a function of the gate voltage. It is also important to note that Vth increased following hydrogenation of the wafer scanned eight times, for devices with negative threshold values. After measuring 15 TFTs where the average Vth was equal to ÿ2.16 V before hydrogenation, it rose to ÿ1.52 V after. In most cases, because hydrogen reduces the number of dangling bonds, the threshold voltage decreases for n-type devices following hydrogenation [16]. However, in the case of donorlike interfacial traps, a reduction in their number would increase Vth.
By making ID±VG measurements at various temperatures, the source-drain current activation energy of each annealing condition, as a function of gate voltage was also determined, and is shown in Fig. 7. The steady decrease in the activation energy with each scan suggests that the Fermi level is moving progressively closer to the conduction band edge. This can be accounted for by either a growing layer of positive interfacial charge or accumulation of n-type dopant in the channel. The dopant could only come from the source and drain regions, but series resistance measurements have con®rmed that this is not the case. It is also possible that incorporated oxygen is acting as a thermal donor, and as the oxygen level increases with each scan, the eect is magni®ed. However, this same drop in activation energy is not witnessed for TFTs laser annealed in air, thus disarming this theory. This leaves interfacial charge due to the presence of traps as the likely culprit. The charge would have the eect of drawing electrons to the surface of the channel, shifting the Fermi level in the bandgap towards the conduction band, and thus lowering the activation energy. Interfacial traps may also be responsible for the increase in leakage current, which occurred for samples scanned multiple times, as shown in Table 1. It is widely believed trap assisted thermionic ®eld emission in the high electric ®eld region near the drain contact is responsible for the anomalously high o-current in p-Si TFTs, for low drain-source voltages [17]. Interface traps introduce allowable energy levels in the bandgap at the p-Si/SiO2 interface, which serve to increase leakage current.
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Fig. 7. Source-drain current activation energy as a function of gate voltage for ELA p-Si TFTs scanned one, two, four and eight times at 305 mJ/cm2.
4. Conclusion Through this investigation, we were able to determine the eects of multiple scans on laser annealed pSi TFTs. Comparison to devices made from single scans revealed that the subthreshold slope and leakage current were aected adversely by multiple scans. In addition, the increase in mobility in relation to grain size was not as profound as for single scans. The changes which occurred within the devices could be explained by an increase in the intragrain defect density and an increase in the magnitude of the p-Si/SiO2 interfacial trap density. This investigation also revealed the subtle interplay between the eect of grain boundary and intragrain defects on mobility. Under certain conditions, maximizing the grain size may not lead to enhanced device performance, if its accompanied by an increase in intragranular defects. Even for ELA, where the intragrain defect density is typically low, carrier mobility may still be signi®cantly aected by scattering within the grain itself. A regime exists, determined by the grain boundary barrier height, separating under what conditions intragrain or grain boundary defects dominate the conduction process. If the grain boundary barrier height is low, intragrain mobility, as controlled by intragrain defects, will play an enhanced role. If the barrier height is high, the grain boundaries will dominate the transport of carriers.
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