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Electrical activation and defects in silicon-implanted and rapidly thermal-annealed gallium arsenide
Nuclear Instruments North-Holland
and Methods
in Physics Research
B59/60
Electrical activation and defects in silicon-implanted thermal-annealed gallium arsenide L. Palmetshofer
1081
(1991) 1081-1085
and rapidly
and J. Kastner
Institut fir E.upenmentalphvslk,
Johannes-Kepler-Unloersitiit,
A-4040 Linr, Austrra
K. Liibke lnslitut ftir Mikroelektronzk,
Johannes-Kepler-UniL~ersitiit,
A-4040 Lin:, Austria
The electrical activation and carrier concentration profiles in high-dose Si-implanted (120 keV, 1~10’~ cm-‘) GaAs layers are reported. The highest activation efficiency observed is 44% both for SiO, and for SiO,N., encapsulation during rapid thermal annealing. For SiO,N, capping the carrier concentration profile is within the theoretical implantation profile, for Si02 capping the carrier concentration profiles are diffusion broadened. Defect studies by deep-level transient spectroscopy revealed the midgap level EL2 as a dominant electron trap after implantation and annealing. The EL2 concentration in as-grown homogeneously Si-doped GaAs layers is very low. but increases strongly during annealing. The increase of the EL2 concentration depends on the cap layer, being much stronger for SiO, encapsulation than for SiO,N., capping. The implantation-induced trap concentration can be annealed out to about a value as arising from the capping and annealing procedure at that temperature.
1. Introduction
2. Experimental
Silicon ion implantation and rapid thermal annealing (RTA) are widely used in the fabrication of n-channel GaAs devices. The characteristics and performance of such devices depend strongly on the carrier concentration profiles and on residual defects resulting from ion implantation. The properties of Si-implanted GaAs layers are influenced by various parameters; the implantation dose and energy, the annealing temperata.ire and time, the encapsulation, and the GaAs substrate are the most important parameters [l-2]. Many experiments on Si-implanted GaAs have been carried out (refs. [1.2] and citations therein), resulting in a better understanding of implantation doping of GaAs. However, relatively few papers are dealing with defect investigations after Si implantation and appropriate annealing [3]. In this article we report on the influence of defects on the activation efficiency in Si-implanted and rapidly thermal-annealed GaAs. In the first part the electrical activation of high-dose Si implants as a function of the annealing temperature and carrier concentration profiles are reported. In the second part the investigation of electrically active defects is presented. The evolution of defects due to the implantation and annealing process is discussed. The conditions for lowest defect concentrations are compared with those for highest activation efficiencies.
Undoped layers (1 urn thick) of GaAs were grown by metal organic chemical vapour deposition (MOCVD) on undoped semi-insulating GaAs wafers. Trimethylgalhum and arsine in hydrogen were used as source materials [4]. Ion implantation was performed at room temperature with an energy of 120 keV and a dose of 1 X 1014 cmp2. Usually the isotope 2sSi was used: control implantations with 29Si produced identical results. As annealing encapsulants. 100 nm thick layers of SiO,, Si?N,, or SiO,N, were deposited at low temperatures (about 350°C). SiO, films were grown by the pyrolytic reaction of SiH, and 0,. Si3N, and SiO,N.,. (O/N ratio = 0.3) films were deposited by plasma-enhanced chemical vapour deposition of SiH,, N, and N,O. Rapid thermal annealing was performed at temperatures between 800 and 1100” C, with a commercial-halogenlamp-heated system under a Nz atmosphere. The annealing time was varied between 2 and 20 s. For comparison. conventional furnace annealing was done at 850°C for 5 min in a H, atmosphere. Electrical properties were determined by conductivity and Hall effect measurements on samples with Van der Pauw geometry. Carrier concentration profiles were measured by the differential Hall technique, using anodic oxidation for controlled layer removal [5]. Defects were studied by deep-level transient spectroscopy (DLTS) on Schottky diodes prepared after implantation
0168-583X/91/$03.50
~c’1991 - Elsevier Science Publishers
B.V. (North-Holland)
VIII. SEMICONDUCTORS
L. Palmetshofer ei al. / Electrical activation and defects in %-implanted GaAs
1082
and annealing. The implantation dose (5 X lo’* cm- ’ ) was chosen so that the resulting diode parameter would allow DLTS analysis of the defect distribution. DLTS spectra were recorded at temperatures between 77 and 400 K. Short duration filling pulses were used in order to avoid distorting effects of minority carrier emission [3]. For comparison, DLTS measurements were also performed on homogeneously Si-doped (10” cm ’ ) GaAs layers.
Table 1 Results of Hall effect measurements for 120 keV. 1 x 10” cm-- ’ Si implants in GaAs under various annealing conditions. r,: annealing temperature; tA: annealing time; amax: maximnm electron concentration Cap layer ;a SiOz
SiO,N,
3. Results and discussion
?C]
Activ. PI
n mai [lOi’ cm-‘] 1.4 1.5
3 10 300
980 940 850
37 44 42
3 10
1020 1000
36 44
1.4 2.2
3.1. Electrical activation of Si implants in GaAs The electrical activation of Si implanted with a lOi cm-’ dose at 120 keV in GaAs is shown in fig. 1 as a function of the annealing temperature. The activation increases at first with increasing annealing temperature, reaches a maximum and falls again at higher temperatures. The position of the maximum depends on the annealing time and on the encapsulating layer. At short annealing times (3 s, fig. la), higher temperatures are necessary for highest activation than at longer annealing times (10 s, fig. lb). SiO,N,. encapsulation requires higher annealing temperatures than SiO, encapsulation.
1
I 1000 Annealing
temperature
1°C 1
Fig. 1. Electrical activation as a function of the annealing temperature for Si-implanted (120 keV, 1~10’~ cm-*) GaAs with SiO, (0) and SiO,N, (0) encapsulating layers. Annealing time: 3 (a) and 10 s (b).
The annealing curves for Si,N, capped samples are similar to those of SiO.,N.,. capped samples. only the activation is inferior to SiO,N,. encapsulation. This is consistent with results reported in the literature [6]. Therefore, Si,N, encapsulation is not treated in the following. The highest activation efficiency has been found to be 44% both for SiO, and for SiO,N,. encapsulation at annealing times of about 10 s. For comparison. the highest activation efficiency obtained with conventional furnace annealing (85O”C, 5 min) was 42%. The results are summarized in table 1. Although the activation efficiency arrives at the same value of 44% both for SiO, and for SiO,N,. encapsulation under appropriate annealing conditions. the carrier concentration profiles differ considerably, as shown in fig. 2. The carrier concentration profile is within the theoretical implantation profile (calculated with the TRIM code) only for SiO,N,. encapsulated samples. Profiles obtained on SiO, encapsulated samples are always diffusion broadened, even for annealing times as short as 2-3 s. Consequently, the peak electron concentration is higher for SiO_,N,. capped samples than for SiO, encapsulation. The values are given in table 1. The peak electron concentration of 2.2 x 10” cm-j obtained with SiO,N.,. encapsulation is on the practical limit achievable by high dose implantations [l]. It should be noted, however, that for other GaAs substrates higher values have been reported [2.6]. The most striking result shown in fig. 2 is the broadening of the profiles. This broadening occurs only for samples encapsulated with SiO, and only after high-dose implantations when the carrier concentration reaches the 10’” cme3 range. For low-dose implantations with carrier concentrations at 10” crnm3 or below. no significant broadening occurs as has been checked by C-V measurements. Obviously. a high concentration of Ga vacancies as caused by the outdiffusion of Ga through the SiO, cap and a certain doping level are necessary for the fast Si diffusion process. A diffusion model based on the diffusion of neutral Si&Si& pairs has been proposed by Greiner and Gibbons [7]. In more recent
1083
L. Pui~etshofer et nl. / Ekctrical actiontion and defects in S-implanted &As
-TRIM
120keV Si',5~10'~cd
Temperature (KI Fig. 3. DLTS spectra of S&implanted (120 keV, 5 X lOI cm-‘) GaAs encapsulated with SiO, during annealing at 940°C for 10 s and encapsulated with SiO,N, during annealing at 1000 o C for 10 s.
0
01
0.2
0.3
04
Depth i,uml
Fig. 2. Carrier concentration and mobility profiles of Si-implanted (120 keV, I x lOI cme2) GaAs with SiO, (circles) and SiO,N,. (squares) encapsulating layers. Annealing parameters: (0) 940°C. 3 s; (0) 940°C, 10s; (0) 1000°C. 10 s. The theoretical implantation profile obtained by the TRIM code is shown for comparison.
lOI cmm3 for SiO,YN,, encapsulation. After partial annealing at 800°C the EL2 concentration has about the same value for both cases. The EL2 concentration of unimplant~ homogeneously Si-doped (1 x 101’ cmm3) samples is very low (about 3-4 X lOI cm-3), as shown by the points designated with n.a. on the abscissa of figs. 4 and 5. Therefore, it is evident, that the deep traps are, in the first instance, implantation induced.
papers it is proposed that the concentration-dependent diffusivity is a Fermi level effect [8,9]. 3.2. Dejects in pi-implanted
- 1LOkeV Si'~SxlO'* cm2 ---Sidoped, not implanted
&As
,o”
SiO2 encapsulation
DLTS spectra of Si-implanted GaAs after annealing are shown in fig. 3. Spectra obtained on SiO, encapsulated samples show only one large peak. The corresponding electron trap is the prominent midgap level EL2, located at EC - 0.80 eV. Spectra from SiO,N, encapsulated samples show two peaks. The larger peak corresponds to the electron trap EL2, the smaller is an electron trap at EC - 0.34 eV, which is most probably EL6 The intensity of both peaks is small compared to the large EL2 peak in SiO, encapsulated samples. The trap concentration in the vicinity of the implantation maximum was calculated taking into account the nonuniform doping level and interface corrections [lo]. The results are shown in figs. 4 and 5 for SiO, and SiO,N_, encapsulated samples, respectively. The trap concentration for implanted samples (full lines) decreases with increasing annealing temperature down to a ~nimum value and increases again at higher temperatures. The minimum value of the EL2 con~ntrat~on is about 2 X lOI6 cm- 3 for SiO, encapsulation and below
z
,' ,' ,'
tA =1&i “ “ ,' ,' ,' ,j' ,' ,d I' ,' 8' ,,'
n.a.
.* 700 Annealing
800
900
temperature
1000 I’C
1
Fig. 4. EL2 concentration of Si-implanted (120 keV, 5x10” cm-*) GaAs (full line) and of homogen~usly Si-doped (10” cm-‘) GaAs (broken line) as a function of the annealing temperature for 10 s RTA with SiOz encapsulation. VLII. SEMICONDUCTORS
1084
Table 2 OEL2 'JEL6 - SI+ 5~10'~cni' -_-notImplanted
Results of DLTS measurements for 120 keV. 5 x 10” cm-’ Si implants in GaAs under various annealing conditions. r,: annealing temperature: t,: annealing time: N,,, and NFrh: concentration of the designated defect
‘"
Cap layer ;:
$OxNy encapsulation tn=1os
na.
800
900
1000
1100
Annealing temperature ("Cl
Fig. 5. Concentration of the traps EL2 and EL6 of Si-implanted (120 keV. 5 ~10” cm-‘) GaAs (full lines) and of homogeneously S&doped (10”cm-‘) GaAs (broken lines) as a function of the annealing temperature for 10 s RTA with SiO,N, encapsuiatlon.
However, the annealing procedure introduces also deep traps. as can be seen by the broken lines in figs. 4 and 5. The results. obtained on homogeneously Si-doped samples show a strong increase in the trap concentration with increasing annealing temperature. The increase is much stronger for SiOZ encapsulated samples. Similar high values for the capping and annealing-induced EL2 ~ncentration have been reported by Katayama et al. [ll]. At high annealing temperatures the trap concentrations of implanted and unimplanted samples have comparable values. The minimum of the trap concentration for implanted samples is a result of the decreasing implantation-induced trap concentration and the increasing annealing-procedure-induced trap concentration with increasing temperature. In SiO,N, capped samples the annealing procedure introduces fewer traps than in SiO1 capped samples allowing a more efficient annealing of implantation-induced defects. The result is a much lower minimum trap concentration. The temperature for minimum trap concentration is about the same, or slightly higher. at which the maximum electrical activation occurs (figs. lb, 4 and 5). However, a general correlation of optimum activation with minimum defect concentration cannot be inferred from this result. The trap concentration of SiO_,N,, capped samples is more than an order of magnitude
&Y]
SiO,
10 300
940 X50
SiO,N v
10 300
1020 850
NE,,
NFL,
[cm j]
[cm-‘]
2 5
-
XlO’h x10’4
9 XlO’j 2.5 x 10’4
1.4x10’4 4 x10’
lower than for SiO, encapsulation, although the electrical activation has about the same value. Moreover, the trap concentration after conventional furnace annealing (85O’C. 5 min) is both for SiO, and for SiO,,N,. encapsulation much lower than after RTA. The values are given in table 2. The electrical activation, on the other hand, is almost as high for furnace annealing as for RTA (table 1). The main reason for the lower trap concentration after furnace annealing lies in the lower annealing temperature. The minimum trap concentration obtainable after annealing is most likely to be given approximately by the dotted lines in figs. 4 and 5. It is strongly dependent on the temperature and on the cap layer. SiO,,N,,. encapsulation is superiour to SiO, encapsulation in obtaining low defect concentrations. The parallel annealing curves for the traps EL2 and EL6 (fig. 5) indicate some relation between EL2 and EL6. as has been proposed recently [12]. In contrast to other investigations [3.13-151 no further defects with concentrations wet1 above the detection limit have been found in our samples. However. all the other studies were performed on different GaAs substrates.
Acknowledgements The authors are grateful for technical assistance from Mr. C. Diskus, Ms. U. Stiigmiiller and Mr. K.H. Ablinger. Dr. G. Kaufel of the Fraunhofer Institut fiir Angewandte Festknrperforschung in Freiburg kindly performed the Si,N, and SiO,N,. capping. This work has been supported by the Fonds zur Fiirderung der wissenschaftlichen Forschung, Austria.
References [l] S.J. Pearton. Solid State Phenomena l/2 (1988) 247, [2] S.S. Gill, ibid., p. 281. [3] D.W.E. Allsopp, ibid.. p. 211. [4] T.F. Kuech. Mater. Sci. Rep. 2 (1987) 1. [5] H. Mi.iller. F.H. Eisen and J.W. Mayer, J. Electrochem. Sot. 122 (1975) 651.
L. Falmets~ofer et ai. / Electrical activation and defects in Si-implanted GaAs [6] M. Kuzuhara, T. Nozaki and H. Kohzu, J. Appl. Phys. 58 (1975) 1204. [7] M.E. Greiner and J.F. Gibbons, J. Appl. Phys. 57 (1985) 5181. [8] D.G. Deppe, N. Holonyak and J.E. Baker, Appl. Phys. Lett. 52 (1988) 129. [9] S. Yu. U.M. Gosele and T.Y. Tan, J. Appl. Phys. 66 (1989) 2952. [IO] J.H. Zhao, J.C. Lee, Z.Q. Fang, T.E. Schlesinger and A.G. Mimes. J. Appl. Phys. 61 (1987) 1063.
[II]
1085
M. Katayama, Y. Tokuda, N. Ando, A. Kitigawa, A. Usami, Y. Inoue and T. Wada, Mater. Res. Sot. Symp. Proc. 146 (1989) 431. [12] H.Y. Cho. E.K. Kim and S.-K. Min. J. Appl. Phys. 66 (1989) 3038. [13] D. Allsopp. Semicond. Sci. Technol. 2 (1987) 129. 1141 M. Kuzuhara and T. Nozaki, J. Appl. Phys. 59 (1986) 3131. fl5] A. Kitigawa, A. Usami, T. Wada and Y. Tokuda, J. Appl. Phys. 63 (1988) 414.
VIII. SEMtCONDUCTORS
and Methods
in Physics Research
B59/60
Electrical activation and defects in silicon-implanted thermal-annealed gallium arsenide L. Palmetshofer
1081
(1991) 1081-1085
and rapidly
and J. Kastner
Institut fir E.upenmentalphvslk,
Johannes-Kepler-Unloersitiit,
A-4040 Linr, Austrra
K. Liibke lnslitut ftir Mikroelektronzk,
Johannes-Kepler-UniL~ersitiit,
A-4040 Lin:, Austria
The electrical activation and carrier concentration profiles in high-dose Si-implanted (120 keV, 1~10’~ cm-‘) GaAs layers are reported. The highest activation efficiency observed is 44% both for SiO, and for SiO,N., encapsulation during rapid thermal annealing. For SiO,N, capping the carrier concentration profile is within the theoretical implantation profile, for Si02 capping the carrier concentration profiles are diffusion broadened. Defect studies by deep-level transient spectroscopy revealed the midgap level EL2 as a dominant electron trap after implantation and annealing. The EL2 concentration in as-grown homogeneously Si-doped GaAs layers is very low. but increases strongly during annealing. The increase of the EL2 concentration depends on the cap layer, being much stronger for SiO, encapsulation than for SiO,N., capping. The implantation-induced trap concentration can be annealed out to about a value as arising from the capping and annealing procedure at that temperature.
1. Introduction
2. Experimental
Silicon ion implantation and rapid thermal annealing (RTA) are widely used in the fabrication of n-channel GaAs devices. The characteristics and performance of such devices depend strongly on the carrier concentration profiles and on residual defects resulting from ion implantation. The properties of Si-implanted GaAs layers are influenced by various parameters; the implantation dose and energy, the annealing temperata.ire and time, the encapsulation, and the GaAs substrate are the most important parameters [l-2]. Many experiments on Si-implanted GaAs have been carried out (refs. [1.2] and citations therein), resulting in a better understanding of implantation doping of GaAs. However, relatively few papers are dealing with defect investigations after Si implantation and appropriate annealing [3]. In this article we report on the influence of defects on the activation efficiency in Si-implanted and rapidly thermal-annealed GaAs. In the first part the electrical activation of high-dose Si implants as a function of the annealing temperature and carrier concentration profiles are reported. In the second part the investigation of electrically active defects is presented. The evolution of defects due to the implantation and annealing process is discussed. The conditions for lowest defect concentrations are compared with those for highest activation efficiencies.
Undoped layers (1 urn thick) of GaAs were grown by metal organic chemical vapour deposition (MOCVD) on undoped semi-insulating GaAs wafers. Trimethylgalhum and arsine in hydrogen were used as source materials [4]. Ion implantation was performed at room temperature with an energy of 120 keV and a dose of 1 X 1014 cmp2. Usually the isotope 2sSi was used: control implantations with 29Si produced identical results. As annealing encapsulants. 100 nm thick layers of SiO,, Si?N,, or SiO,N, were deposited at low temperatures (about 350°C). SiO, films were grown by the pyrolytic reaction of SiH, and 0,. Si3N, and SiO,N.,. (O/N ratio = 0.3) films were deposited by plasma-enhanced chemical vapour deposition of SiH,, N, and N,O. Rapid thermal annealing was performed at temperatures between 800 and 1100” C, with a commercial-halogenlamp-heated system under a Nz atmosphere. The annealing time was varied between 2 and 20 s. For comparison. conventional furnace annealing was done at 850°C for 5 min in a H, atmosphere. Electrical properties were determined by conductivity and Hall effect measurements on samples with Van der Pauw geometry. Carrier concentration profiles were measured by the differential Hall technique, using anodic oxidation for controlled layer removal [5]. Defects were studied by deep-level transient spectroscopy (DLTS) on Schottky diodes prepared after implantation
0168-583X/91/$03.50
~c’1991 - Elsevier Science Publishers
B.V. (North-Holland)
VIII. SEMICONDUCTORS
L. Palmetshofer ei al. / Electrical activation and defects in %-implanted GaAs
1082
and annealing. The implantation dose (5 X lo’* cm- ’ ) was chosen so that the resulting diode parameter would allow DLTS analysis of the defect distribution. DLTS spectra were recorded at temperatures between 77 and 400 K. Short duration filling pulses were used in order to avoid distorting effects of minority carrier emission [3]. For comparison, DLTS measurements were also performed on homogeneously Si-doped (10” cm ’ ) GaAs layers.
Table 1 Results of Hall effect measurements for 120 keV. 1 x 10” cm-- ’ Si implants in GaAs under various annealing conditions. r,: annealing temperature; tA: annealing time; amax: maximnm electron concentration Cap layer ;a SiOz
SiO,N,
3. Results and discussion
?C]
Activ. PI
n mai [lOi’ cm-‘] 1.4 1.5
3 10 300
980 940 850
37 44 42
3 10
1020 1000
36 44
1.4 2.2
3.1. Electrical activation of Si implants in GaAs The electrical activation of Si implanted with a lOi cm-’ dose at 120 keV in GaAs is shown in fig. 1 as a function of the annealing temperature. The activation increases at first with increasing annealing temperature, reaches a maximum and falls again at higher temperatures. The position of the maximum depends on the annealing time and on the encapsulating layer. At short annealing times (3 s, fig. la), higher temperatures are necessary for highest activation than at longer annealing times (10 s, fig. lb). SiO,N,. encapsulation requires higher annealing temperatures than SiO, encapsulation.
1
I 1000 Annealing
temperature
1°C 1
Fig. 1. Electrical activation as a function of the annealing temperature for Si-implanted (120 keV, 1~10’~ cm-*) GaAs with SiO, (0) and SiO,N, (0) encapsulating layers. Annealing time: 3 (a) and 10 s (b).
The annealing curves for Si,N, capped samples are similar to those of SiO.,N.,. capped samples. only the activation is inferior to SiO,N,. encapsulation. This is consistent with results reported in the literature [6]. Therefore, Si,N, encapsulation is not treated in the following. The highest activation efficiency has been found to be 44% both for SiO, and for SiO,N,. encapsulation at annealing times of about 10 s. For comparison. the highest activation efficiency obtained with conventional furnace annealing (85O”C, 5 min) was 42%. The results are summarized in table 1. Although the activation efficiency arrives at the same value of 44% both for SiO, and for SiO,N,. encapsulation under appropriate annealing conditions. the carrier concentration profiles differ considerably, as shown in fig. 2. The carrier concentration profile is within the theoretical implantation profile (calculated with the TRIM code) only for SiO,N,. encapsulated samples. Profiles obtained on SiO, encapsulated samples are always diffusion broadened, even for annealing times as short as 2-3 s. Consequently, the peak electron concentration is higher for SiO_,N,. capped samples than for SiO, encapsulation. The values are given in table 1. The peak electron concentration of 2.2 x 10” cm-j obtained with SiO,N.,. encapsulation is on the practical limit achievable by high dose implantations [l]. It should be noted, however, that for other GaAs substrates higher values have been reported [2.6]. The most striking result shown in fig. 2 is the broadening of the profiles. This broadening occurs only for samples encapsulated with SiO, and only after high-dose implantations when the carrier concentration reaches the 10’” cme3 range. For low-dose implantations with carrier concentrations at 10” crnm3 or below. no significant broadening occurs as has been checked by C-V measurements. Obviously. a high concentration of Ga vacancies as caused by the outdiffusion of Ga through the SiO, cap and a certain doping level are necessary for the fast Si diffusion process. A diffusion model based on the diffusion of neutral Si&Si& pairs has been proposed by Greiner and Gibbons [7]. In more recent
1083
L. Pui~etshofer et nl. / Ekctrical actiontion and defects in S-implanted &As
-TRIM
120keV Si',5~10'~cd
Temperature (KI Fig. 3. DLTS spectra of S&implanted (120 keV, 5 X lOI cm-‘) GaAs encapsulated with SiO, during annealing at 940°C for 10 s and encapsulated with SiO,N, during annealing at 1000 o C for 10 s.
0
01
0.2
0.3
04
Depth i,uml
Fig. 2. Carrier concentration and mobility profiles of Si-implanted (120 keV, I x lOI cme2) GaAs with SiO, (circles) and SiO,N,. (squares) encapsulating layers. Annealing parameters: (0) 940°C. 3 s; (0) 940°C, 10s; (0) 1000°C. 10 s. The theoretical implantation profile obtained by the TRIM code is shown for comparison.
lOI cmm3 for SiO,YN,, encapsulation. After partial annealing at 800°C the EL2 concentration has about the same value for both cases. The EL2 concentration of unimplant~ homogeneously Si-doped (1 x 101’ cmm3) samples is very low (about 3-4 X lOI cm-3), as shown by the points designated with n.a. on the abscissa of figs. 4 and 5. Therefore, it is evident, that the deep traps are, in the first instance, implantation induced.
papers it is proposed that the concentration-dependent diffusivity is a Fermi level effect [8,9]. 3.2. Dejects in pi-implanted
- 1LOkeV Si'~SxlO'* cm2 ---Sidoped, not implanted
&As
,o”
SiO2 encapsulation
DLTS spectra of Si-implanted GaAs after annealing are shown in fig. 3. Spectra obtained on SiO, encapsulated samples show only one large peak. The corresponding electron trap is the prominent midgap level EL2, located at EC - 0.80 eV. Spectra from SiO,N, encapsulated samples show two peaks. The larger peak corresponds to the electron trap EL2, the smaller is an electron trap at EC - 0.34 eV, which is most probably EL6 The intensity of both peaks is small compared to the large EL2 peak in SiO, encapsulated samples. The trap concentration in the vicinity of the implantation maximum was calculated taking into account the nonuniform doping level and interface corrections [lo]. The results are shown in figs. 4 and 5 for SiO, and SiO,N_, encapsulated samples, respectively. The trap concentration for implanted samples (full lines) decreases with increasing annealing temperature down to a ~nimum value and increases again at higher temperatures. The minimum value of the EL2 con~ntrat~on is about 2 X lOI6 cm- 3 for SiO, encapsulation and below
z
,' ,' ,'
tA =1&i “ “ ,' ,' ,' ,j' ,' ,d I' ,' 8' ,,'
n.a.
.* 700 Annealing
800
900
temperature
1000 I’C
1
Fig. 4. EL2 concentration of Si-implanted (120 keV, 5x10” cm-*) GaAs (full line) and of homogen~usly Si-doped (10” cm-‘) GaAs (broken line) as a function of the annealing temperature for 10 s RTA with SiOz encapsulation. VLII. SEMICONDUCTORS
1084
Table 2 OEL2 'JEL6 - SI+ 5~10'~cni' -_-notImplanted
Results of DLTS measurements for 120 keV. 5 x 10” cm-’ Si implants in GaAs under various annealing conditions. r,: annealing temperature: t,: annealing time: N,,, and NFrh: concentration of the designated defect
‘"
Cap layer ;:
$OxNy encapsulation tn=1os
na.
800
900
1000
1100
Annealing temperature ("Cl
Fig. 5. Concentration of the traps EL2 and EL6 of Si-implanted (120 keV. 5 ~10” cm-‘) GaAs (full lines) and of homogeneously S&doped (10”cm-‘) GaAs (broken lines) as a function of the annealing temperature for 10 s RTA with SiO,N, encapsuiatlon.
However, the annealing procedure introduces also deep traps. as can be seen by the broken lines in figs. 4 and 5. The results. obtained on homogeneously Si-doped samples show a strong increase in the trap concentration with increasing annealing temperature. The increase is much stronger for SiOZ encapsulated samples. Similar high values for the capping and annealing-induced EL2 ~ncentration have been reported by Katayama et al. [ll]. At high annealing temperatures the trap concentrations of implanted and unimplanted samples have comparable values. The minimum of the trap concentration for implanted samples is a result of the decreasing implantation-induced trap concentration and the increasing annealing-procedure-induced trap concentration with increasing temperature. In SiO,N, capped samples the annealing procedure introduces fewer traps than in SiO1 capped samples allowing a more efficient annealing of implantation-induced defects. The result is a much lower minimum trap concentration. The temperature for minimum trap concentration is about the same, or slightly higher. at which the maximum electrical activation occurs (figs. lb, 4 and 5). However, a general correlation of optimum activation with minimum defect concentration cannot be inferred from this result. The trap concentration of SiO_,N,, capped samples is more than an order of magnitude
&Y]
SiO,
10 300
940 X50
SiO,N v
10 300
1020 850
NE,,
NFL,
[cm j]
[cm-‘]
2 5
-
XlO’h x10’4
9 XlO’j 2.5 x 10’4
1.4x10’4 4 x10’
lower than for SiO, encapsulation, although the electrical activation has about the same value. Moreover, the trap concentration after conventional furnace annealing (85O’C. 5 min) is both for SiO, and for SiO,,N,. encapsulation much lower than after RTA. The values are given in table 2. The electrical activation, on the other hand, is almost as high for furnace annealing as for RTA (table 1). The main reason for the lower trap concentration after furnace annealing lies in the lower annealing temperature. The minimum trap concentration obtainable after annealing is most likely to be given approximately by the dotted lines in figs. 4 and 5. It is strongly dependent on the temperature and on the cap layer. SiO,,N,,. encapsulation is superiour to SiO, encapsulation in obtaining low defect concentrations. The parallel annealing curves for the traps EL2 and EL6 (fig. 5) indicate some relation between EL2 and EL6. as has been proposed recently [12]. In contrast to other investigations [3.13-151 no further defects with concentrations wet1 above the detection limit have been found in our samples. However. all the other studies were performed on different GaAs substrates.
Acknowledgements The authors are grateful for technical assistance from Mr. C. Diskus, Ms. U. Stiigmiiller and Mr. K.H. Ablinger. Dr. G. Kaufel of the Fraunhofer Institut fiir Angewandte Festknrperforschung in Freiburg kindly performed the Si,N, and SiO,N,. capping. This work has been supported by the Fonds zur Fiirderung der wissenschaftlichen Forschung, Austria.
References [l] S.J. Pearton. Solid State Phenomena l/2 (1988) 247, [2] S.S. Gill, ibid., p. 281. [3] D.W.E. Allsopp, ibid.. p. 211. [4] T.F. Kuech. Mater. Sci. Rep. 2 (1987) 1. [5] H. Mi.iller. F.H. Eisen and J.W. Mayer, J. Electrochem. Sot. 122 (1975) 651.
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VIII. SEMtCONDUCTORS