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Electrostatic discharges (ESD), latch-up and pad design constraints
ENGm~gEalI~D ELSEVIER
Microelectronic Engineering49 (1999) 83-94 www.elsevier.nl/loeate/mee
ElectroStatic Discharges (ESD), Latch-Up and Pad Design Constraints Pascal SALOME, Corinne RICHIER STMicroelectronics, 850 Rue J e a n Monnet, 38926 Crolles Cedex, France Phone: 33 4 76 92 68 18, Fax: 33 4 76 92 64 44, Email: [email protected] a b s t r a c t : This paper is tailored to beginners in the field of electrostatic discharges. After a brief introduction, the basics of ESD are first reviewed and followed by a description of the standards devoted to the protection of intregrated circuits. Then, the behavior and modeling of elementary devices u n d e r ESD are discussed.
1. I N T R O D U C T I O N Static electricity is defined as an electrical charge caused by an imbalance of electrons on the surface of a material. ElectroStatic Discharge (ESD) is defined as the transfer of a charge between two materials at different electrical potentials, one could be a h u m a n body. ESDs m a y affect the electrical characteristics of a semiconductor device or upset the normal operation of an electronic system leading to equipment malfunction or failure. An example resulting from such a discharge can be seen in figure 1. In this case, the electrostatic discharge led to a strong short circuit due to a large melted silicon filament between sources and drains of a cascoded NMOS device.
figure 1: d a m a g e i n d u c e d by an E S D
Damages due to ESD stresses on integrated circuits can be an oxide rupture, a metal or contact burn-out. It can also be a diffusion damage caused by an excessive heating. ESD became a significant problem in silicon ICs as soon as technology feature sizes were reduced to les t h a n 2~m [1]. An approximate technology roadmap is given in table 1. Table 1: Technology road map
Feat~Size:(~tm) :~ ( n ~ ): 2 1 0.8 0.5 0.35 0.25 0.18 0.15
40 20 15 10 7 5 3.5 2.5
: LDD No Yes Yes Yes Yes Yes Yes Yes
s~icide
No No Yes Yes Yes Yes Yes Yes
Advances in IC technology have made circuits and devices smaller and faster but also have greatly increased their susceptibility to ESD. Furthermore, the introduction of both lightly doped drain (LDD) and salicided diffusions led to a so large decrease in the ESD performances t h a t protecting a device became a veritable challenge. Most of the effort in ESD has been
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved. PII: S0167:9317(99)00431-1
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P. Salom~, C. Richier I Microelectronic Engineering 49 (1999) 83-94
focused on developing protection circuits addressing the LDD and silicide problems and maintaining the ESD protection level, especially with thinning of the gate oxide to less than 7nm. 2. E S D B A S I C S
Controlling ESD begins with understanding how an electrostatic charge occurs. Electrostatic charge may be created on a material in different ways such as by contact and separation of two materials, by induction, ion bombardment or contact with another charged object. In the following, the most common charging methods known as "triboelectric charging" and "charging by induction" are described.
electrons it becomes negatively charged. The polarity and magnitude of the charge are indicated by the positions of the materials in the triboelectric series table which lists materials according to their relative triboelectric charging characteristics [2]. The first material listed in the table takes on a positive charge and the other a negative charge. Materials further apart on the table generate a higher charge than those which are closer (see table 2). Table 2: Electrostatic Triboelectric Series
Most positive
2.1. T r i b o e l e c t r i c C h a r g i n g Triboelectric Charging is refered to describe an electrostatic charge which is created by the contact and separation of two materials, similar or not. This mechanism involves the transfer of electrons between materials. Let us assume two different materials which are electrically neutral. Placed in contact and then separated, electrons are transfered from the surface of one material to the surface of the other (see figure 2). Iaterial A
~
Material
atori
Materials after se?aration
I
~ ~ L I
aterial B[ +lq[
~3ainse l e c . ~ _ _ ~ ]
Polyster
Most negative
Materials in contact
sses eltec.I
figure 2: triboelectric charging When a material losses electrons it becomes positively charged while gaining
Air Human skin Glass Mica Human hair Nylon Aluminum Wood Copper Silver Gold Orlon Polyurethan Vinyl Silicon Teflon Silicon rubber
The process of triboeleetrie charging is really a more complex mechanism than described here above. The amount of charge is affected by the area of contact, the speed of separation, the Relative Humidity (RH) and many other factors. But once the charge is created, an electrostatic discharge will follow which may induce damages within the chip. The level of charge is measured in coulombs but, we commonly speak of electrostatic potential expressed as voltage (Q=C*U). The first most common example of triboelectric charging is a man walking across the floor. He generates static electricity as shoe soles contact and separate from the floor
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P. SalomJ, C. Richier / Microelectronic Engineering 49 (1999) 83-94
surface. Table 3 gives examples of such a generation [3-4]. The second most common example is an electronic device sliding into or out of a tube which generates a charge as metal leads make multiple contacts and separations with the container. Table 3: Static Voltage as a Function of Humidity
walking across vinyl floor
12kV
0.25kV
walking across carpet
35kV
1.5kV
removing DIPs from plastic tubes
20 kV
5kV
Once created, the lifetime of the charge depends on the electrical characteristics of the materials. Insulators do not allow the flow of electrons and the charge may remain in place for a very long time. Conductive materials allow electrons to flow easily across their surface. As long as the conductor is isolated from other conductors or ground, the charge will remain. However if the conductor is grounded the charge will easily go to ground or if the conductor contacts another conductor, the charge will flow between the two conductors. 2.2. C h a r g i n g b y i n d u c t i o n Charging by induction is the process whereby an uncharged conductor becomes charged when grounded in presence of an electrostatic field. This process can be described in the following way [5]. If a charged object (CO) is brought near an insulated device, it sets up a field in its vicinity which induces a movement of charge into the device remaining globally neutral (see figure 3a). If CO is charged negatively, the potential at A into the device tends to be more negative than at B. Since the potential at every point of the device must be the same, a movement of electrons takes place from A to B. This results in a separation of charges such that positive charges will be at end A and negative charges will be at end B.
If the device is momentarily grounded while within the electrostatic field, a transfer of charge from the device occurs as seen in figure 3b. Therefore, a first electrostatic discharge happens. A net positive charge will be retained when the ground connection is broken as in figure 3c. Cancelling the electrical field by removing CO allows the charge to spread evenly over the device as in figure 3d. If the ground connection is established once again, electrons will flow back to the device bringing it to its neutral condition. This will lead to the occuring of a new ESD but in the opposite polarity. (a)
(b) device
BI-:- :HA
device
BI ~_-~electrons (d)
(c) device
81
device
BI+ ++÷+IA
figure 3a,3b,3c,3d: process of charging by induction As for triboelectric charging, many factors impact on the amount of charge induced into the device such as the relative humidity, the strength of the field and the device's coupling to that field. ESD caused by induction is probably the most insidious ESD event. All surfaces can be charged by charge sharing, i.e. being touched by a charged person or source. Thus, all those surfaces have the potential for sourcing a field that can cause inductive ESD. The parameters controlling the magnitude of the ESD current pulse are the charge on the source, the capacitance of the source to ground and the capacitance of the device to
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P. SalomJ, C. Richier / Microelectronic Engineering 49 (I999) 83-94
the source leading to m a n y unknown values and to a very hazardous phenomenon [6]. 3. E S D S T A N D A R D S In integrated circuit manufacturing and handling environment, there are three principal sources of ESD. The first and most common to date is the one due to h u m a n handling. It has been shown previously that a person can accumulate charges through a triboelectric mechanism. Therefore an electrostatic discharge may effectively happen if this person touches a grounded circuit. The charge exchange which takes place during such an event will be from the person to the device. To simulate this event a first standard was introduced known as H u m a n Body Model (HBM). The second source of ESD takes place in automated test and handling systems. The equipment can accumulate static charge due to improper grounding, which is then transmitted through the IC when it is picked up for placement in the test socket. This discharge is a shorter duration current pulse of higher magnitude compared to an HBM event and, therefore, a second standard was proposed to simulate this event known as Machine Model (MM). The third possible source of ESD is the IC itself which m a y be charged during transport or because of contact with a highly charged surface or when placed in a field. The charge will remain until the IC comes into contact with a grounded surface. Such an event is very different from both H B M and MM due to the nature of the discharge which comes from the device itself and not from an external source. Thus, a third model is used to simulate this kind of ESD known as Charged Device Model (CDM). In this part, these three ESD models are discussed in detail including the methods used to test the sensitivity of ICs and the choice of an appropriate failure criterion.
3.1. H u m a n B o d y M o d e l ( H B M )
HBM discharge occurs in a very short duration, typically of the order of 100ns, with current ranging from 1A to 10A. H B M can be modeled by the LCR circuit shown in figure 4 [7]. It consists of a charged capacitor which is discharged with a series resistance. Whereas different values were proposed for the capacitor and the resistance [8-10], 100pf and 1500f~ are now accepted in any standards [1113].
/
~
DUT ]
R
'
,
'
'
i i i
C
i
Ct
, i i
i ¢
figure 4: ItBM circuit associated to its parasitic components. Cs, stray capacitance; Ct, test board capacitance; L, parasitic inductance which determines the rise time. The discharge waveform of an H B M tester through a 0f~ load is given in figure 5. HBM current waveform 1.2 .< i
1
0.8 0.6
r,1) ea
0.4 0.2 0
I
0
I
I
I
I
5e-08 ]c-O?].5c-OT2c-07Z5e-07]e-07 Time-[s]
VESDf2000VoIts
figure 5: HBM current waveform for an initial voltage capacitance of 2k V. The HBM current pulse can be described by the following equation [14].
P. Salom~, C. Richier / Microelectronic Engineering 49 (1999) 83-94 l(t) = VESDx(1-exp(-R" t))"
(1)
The general test procedure is defined by the MIL-STD-883C method 3015.7 [13], which specifies the calibration of the tester, the number of samples to be tested and also the pin combination. The selection of pin combination is a difficult issue for ICs with large pin count (>64). Each pin is stressed with the substrate pin grounded and stressed once again with the supply pin grounded, all other pins remain floating. Pin to pin combination is also required and consists in stressing each pin against every other pin which is unfeasible for large ICs. Usually the worst-case conditions for the pin to pin combination is only evaluated, namely the pins furthest apart from each other and the pins adjacent to the stressed pin [4]. Another approach, which reduces the severity of the stress and the testing time, is to pulse one pin with all the other non-supply pins grounded. According to the MIL-STD requirements, the stress is performed with three positive followed by three negative pulses spaced of 1 second for a cooling period. However the number of pulses is decreased to one in the JEDEC standard [12] and let to the choice of the user in the EOS/ESD standard [11]. Usually three pulses are prefered to ensure that no cumulative degradations are involved. A recent study showed that in order to reduce the testing time for large pin count devices, the cooling period can be reduced without any thermal non-equilibrium concern [15]. For qualification purposes, devices are stressed at the required pass voltage with new devices for each stress condition. The international specification distinguishes three classes, withstanding HBM voltage is lower than 2kV in which the device is defined as very ESD sensitive, withstanding HBM voltage is higher than 4kV in which the device is defined as ESD insensitive. When passing voltage ranging from 2kV to 4kV, the device is classified as ESD susceptible.
87
3.2. M a c h i n e Model (MM) The equivalent circuit for the Machine Model test is the same as for the HBM one. However, MM consists of a capacitor of 200pF and a series resistor specified at 0f2 [16]. In pratical cases, this series resistor has a finite value. Series inductance is an important parameter which should be defined in any cases (see figure 6). Usually this value ranges from 0.5~H to 2.5~H, but both values are known to induce the same failure modes [17]. The Philips specification requires that L=2.5~H and R=25~ The MM is the standard ESD test method in Japan leading to its general usage by IC manufacturers. Because of the low series resistance, the effect of parasitic circuit are easily detected and it is easier to ensure reproducibility between testers. This feature led to the development of this method in Japan. The MM current pulse can be described by the following equation [14] and is illustrated in figure 6 for different values of the parasitic inductance: .
t
(2)
~LdL.CJ M M current waveform 6 --
"
"
4
" MM(x,b.5p,~) " MM(x,2.51aH) .........
0
-2 -4 -6
0
1e-07
Time-[s]
2e-07
3e-07
4e-07
VESD=400Volts
figure 6: MM current waveform The magnitude of the current is a function of VESD . C ~ showing the dependence of L. The oscillating part is defined by the sinusoidal term in which L and C determine
P. Salomd, C. Richier / Microelectronic Engineering 49 (1999) 83-94
88
the frequency. The damping is described by the resistance and the inductance. If the device resistance does not meet the condition, RL < 2 ~ R, then the damping term dominates and the current waveform becomes that of the HBM. HBM and MM have different forms but failure modes are usually similar and only differ in the severity of the damage.
3.3. C h a r g e d D e v i c e Model (CDM) The concept of CDM is completely different from that of HBM or MM. The discharge comes from the device itself. Therefore the parasitic elements (shown in figure 7) are parasitic resistance and inductance of the ICs. These very low values result in very fast pulses with a short duration that is about lns and high current levels of several amperes.
L
°[ figure 7: CDM equivalent circuit. Because of a very fast transient, the CDM introduces different failure modes from previous test methods, and damages are often revealed in gate oxides of the internal circuitry [18-19]. A standard is currently under development [20]. Draft standard distinguishes between several concepts which are used today in the tester. The charging method can be direct or field induced. In a direct charging method, the charge is applied through a switch and a resistor directly to one of the pins of the device. Charges may spread differently in the
device when a field induced charging method is used [21]. Here the entire package is charged by induction in the presence of an electric field. The field of CDM testing distinguishes two types of testers based on the device positioning: socketed and non-socketed testers. In a socketed tester, devices are inserted in a socket which adds parasitics to the device. Due to these parasitics, the socketed CDM test may significantly differ from the CDM event taking place in a lonely device. However it is also closer to the CDM event which is experienced on a board [22]. In a non socketed CDM test system, devices are placed on a field plate in the dead-bug position. In this category, a second subpartitioning of CDM testers is based on the discharge mode. The discharge can either be initiated by approaching a grounded probe (non-contact mode) or by relay switching (contact mode). Since the CDM test is the hardest available test method being close to real life, an increased demand for this method may be expected. Clearly, the device and the package impedance will have an impact on the CDM waveform [23]. This may explain why the correlation between different types of testers seems to be problematic and why it is so difficult to define a standard which will be approved by everyone [24].
3.4. C h o o s i n g a Failure Criterion Failure criteria are used to determine if the ICs failed during the ESD qualification process. The nature of ESD damage can result in large differences during the measurement of the post-stress leakage curves [25]. However, variations in the severity of the damage can result in a small increase in the leakage current either at the stressed pin or between other pins, especially power supply pins. Therefore, the selection of the failure criterion used during ESD qualification process may significantly impact on the given ESD failure threshold. The best solution is that the stressed device should be subjected to a full functional test after each ESD stress
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P. Salom~, C. Richier / Microelectronic Engineering 49 (1999) 83-94
but this is often not feasible. ESD testers can only perform simple leakage measurement of the stressed pin. For test time issue, the failure criterion is usually defined as a maximum input or output leakage current at a given bias voltage which could be the DC power supply value. As any change of the initial I-V characteristic is considered as a failure, it is also possible to select a percentage change in leakage current (10% to 50% are often reported). As a conclusion, one must be careful when comparing ESD results obtained with different failure criteria, and with the choice of the failure criterion itself [26]. It is highly recommended that any change in leakage current is monitored and noticed as the onset of failure.
than the I-V curve can be sliced in four main regions which are illustrated in figure 9. Both regions 1 and 2 are governed by the standard NMOS operating mode. Region 3 corresponds to the avalanche breakdown region while region 4 is the bipolar or "snapback" region.
Source
Gate
Drain
_
4. BEHAVIOR OF ELEMENTARY DEVICES U N D E R ESD ESD is a fast transient event leading to a high current level, usually in the range of several amperes. This results that all semiconductor devices, MOS transistors, diodes and resistances, will behave differently during ESD with such high current densities compared to usual operation covered by the standard models. In this part, the high current behavior of MOS transistors, Silicon Controlled Recitifers (SCRs), diode and diffused resistances are discussed. 4.1. MOS Transistors Beside the typical operating conduction, namely linear and saturation region, in which the MOS is designed to operate in usual applications, during an ESD event the transistor is required to conduct much more current and operates in regions which are governed by impact ionization, parasitic device behavior and thermal effects. Figure 8 shows a cross-section of an NMOS transistor indicating the parasitic elements which are involved during high current operating mode. The phenomena associated with the high current effect have been deeply studied analytically and numerically [27]. It results
_
•
_
figure 8: cross.section of an NMOS including parasitic elements
:;:;:~,~.
Vg,=2(Vd} VQ=3{VO) vg=J~J~:
0~6 OO4
Region4 0.~0.0~
~_._--~-..-~-~ ___._ ' ~ . , .
Region3
-0,00 -0,01
=
2
I
4
G
~
I
8
q
P
I0
12 V
figure 9: I - V c u r v e o f a n N M O S f o r different gate voltage The avalanche generation of carriers in the high field region near the drain results in hole current into the substrate. This substrate conduction, which is modelized by a n-cell in figure 8, leads to raise the local substrate
9O
P. SalomJ, C. Richier I Microelectronic Engineering 49 (1999) 8 3 - 9 4
potential near the source and eventually induces the source-substrate junction to become forward-biased. Therefore, electrons are injected from the source into the substrate and collected by the drain. A parasitic NPN bipolar conduction is initiated with the drain acting as the collector, the source as the emitter and the substrate as the base. As the bipolar turns on, an additional current source is provided for the multiplication process. Therefore, less impact ionization are required to sustain the bipolar in the on-state leading to reduce the drain voltage down to a value called Vsp. This phenomenon is often refered to a snapback phenomenon (Vsb is the snapback voltage). To increase the robustness of such a device against ESD, it is important to minimize the power which is dissipated during the conduction and thus to reduce the snapback voltage [28]. A theoretical analysis of the structure given in figure 8 leads to the following analytical expression of the holding voltage depending mainly on two parameters 13and
~
=
exp-L (L is the gate length).
¢r VsB = VBRKLLI
E >0 ~o
"6 -v
14 13 12 11 10 9 8 7 6 5
l+
L2+
2)~ j
observed that the higher the gain, the higher the difference between the breakdown voltage (VBRK) and the minimum holding voltage. The effects of qs, corresponding to the characteristic length of the transmission line modelized by the x-cell in figure 8, are reported in figure 11. We can observe that the thinner the epitaxial (qJ decreases), the faster VSB (holding voltage) will tend to the breakdown voltage.
~o r~
I
2
I
VBRK-'I3
"~=2.9 --~-
'
8 7
i
I
I
2
I
I
I
4 6 8 Gate Length [um]
10
12
figure 11: Effect of substrate coefficient on holding voltage (3)
)
~" 13=0.5
I
•
V=0.5
1o
VBRK = 13
.//~Z " ~
14 13 12 11
~=I t~
I
4 6 8 Gate Length [urn]
>O ~0 .=_ "-6
I
10
12
figure 10: Effect of transistor gain on the holding voltage 13is the gain of the NPN transistor in the high-injection level mode. Its impact on the holding voltage is given in figure 10. It is
8 7.5 7 6.5 6 5.5 ~ . ¢ / 5 ~J 7 4.5 4
...... 2 7.0,1.3,0.65 0.251amCMOS, EPI 2.5g ¢, 0.25p.m CMOS, EPI 4g + 0.251Ltm CMOS, Bulk • I
I
I
I
I
1
2
3
4
5
Gate Length [urn]
figure 12: Impact of substrate on the holding voltage for different substrates. Vbk, b and y are given for simulations
6
91
P. SalomJ, C. Rich&r / Microelectronic Engineering 49 (1999) 83-94
Experimental investigations on 0.25~m CMOS process compared to simulation results are reported in figure 12 for different epitaxial substrates and confirm these previous results. The same behavior can be expected in PMOS transistors except that the bipolar transistor is a PNP transistor. PNP transistors have lower gain than NPN transistors and therefore snapback phenomenon is less important and more difficult to optimize. It has often been reported that PMOS transistors are more sensitive to ESD than NMOS transistors [29]. Another device called FMOS (Field MOS) includes a snapback behavior. This device is formed by two diffusion areas separated by a field oxide as LOCOS [30] As a conclusion, to optimize the ESD robustness of snapback devices, both process and design are important parameters to consider [31-32].
forward-biased diodes. Therefore, SCR has a low power dissipation which is very useful in the design of robust ESD protection circuits. However in nowadays technologies this device is difficult to trigger and becomes less and less popular in deep sub-micron technologies.
Vss
Pad
Rsub P a dR~ nwel figure 13: cross-section of a SCR device
4.2. Silicon C o n t r o l l e d Rectifiers (SCRs) SCR is a low impedance element which consists of PNPN device. It is usually formed by parasitic NPN and PNP devices and can be found in both semiconductor technologies namely CMOS and BICMOS. The triggering of SCR connected between power supply and ground pins is often reported as Latch-Up phenomenon which is another reliability concern in ICs. However, due to its low impedance and to its very low holding voltage, this element can be useful to design a robust ESD protections [33]. A cross-section of a CMOS SCR is observed in figure 13 indicating the parasitic elements. SCRs are defined by the feature that the base area of the NPN transistor is also the collector area for the PNP device. During a high current event, the voltage rises until the SCR is triggered by carriers injected into the base of the PNP or the NPN. Depending on Rnwell, Rsub and the gains of the two bipolar transistors, the NPN or the PNP turns on first. This results in a drastic decrease in the holding voltage. The SCR holding voltage may be as low as 1.2 volt which corresponds to the voltage of two
4.3. D i o d e s In the early years of ESD protection, diodes were often used as protection element in their reverse-biased mode. The protection operates when the applied voltage exceeds the diode's breakdown voltage. However, the protective properties of diodes are limited due to the higher dissipated power, during ESD transient, than in a MOS transistor operating in a snapback mode. Moreover, the series resistance is usually high leading to a too much high holding voltage and, thus, to a protection element not efficient enough. Today, diodes are still often used as protection element but in the forward direction acting as a current director toward a more robust ESD clamp [34] or in a stacked configuration acting as a triggering element for a big ESD clamp [35]. In order that diodes provide an adequate protection capability their dynamic resistances should be optimized. Heating in the forward-biased diode takes place in the P and N regions adjacent to the junction. It is relatively low because of the small electric field in these regions. The ESD failure mechanism in diodes
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P. Salomd, C. Richier / Microelectronic Engineering 49 (1999) 83-94
can be described by the phenomenon of second breakdown [28]. 4.4. D i f f u s e d R e s i s t a n c e s The diffused resistance is an often used element in ESD protection circuit network [36]. They are mainly used to decouple primary and secondary stage of protection devices included in input or output circuit. Taking advantage of velocity saturation phenomenon for the high current operating mode, these resistances can be designed to have a low impedence at standard operating current and being indeed much more resistive at high current level as during ESD events [36]. In nowadays technologies, a snapback phenomenon may even be found in well resistances. This parasitic bipolar conduction included in well resistance may be explained as follow. As the current saturates, the electric field builds up at the reverse biased N+/N junction. When the field is high enough, impact ionization mechanism occurs leading to hole generation in an N type well resistance. With such a generation a certain area of the Nwell may become neutral and a NPN bipolar is formed. Therefore, a snapback phenomenon is observed. However, the parasitic bipolar included in well resistance is not robust enough to sustain ESD current [37]. As a conclusion some design rules should be followed in order that such diffused resistances do not become the bottleneck of the protection circuit [38]. 5. CONCLUSION During this introduction on electrostatic discharge, the basics of ESD have been first discussed. From the two main charging processes, i.e. triboelectric charging and field induced charging, it appears that all materials can be charged. Once created, these charges result in electrostatic discharges which can induce failures in the components. In the second part, the principles of the Human Body Model, Machine Model and Charged Device Model have been reviewed. The usual ESD test procedures have also been
outlined. Although the best characterization method for optimizing the ESD protection element is using a square pulse current generated with a transmission line, the often used Transmission Line Method (TLP [39]) has not, however, been developed as this is not yet a standard. The choice of failure criteria is also important and should ideally be set at the specification limits of the device under test. In a third part, the operations of elementary devices under high current conditions have been outlined. Optimizing the snapback phenomenon is a key point to design efficient protection circuits but becomes more and more difficult in deeply submicronic technologies with thinner and thinner gate oxides. In this case the marging between Vsp and the oxide breakdown voltage gets smaller and it becomes difficult to protect devices using standard snapback mechanism. The concept of ESD protection circuit designs and some typical ESD protection circuit elements will be discussed later in a second issue. It can be concluded that ESD protection will remain an important issue in the future. The main challenges will be to provide ESD protection circuits for advanced semiconductor chips [40]. REFERENCES 1. DWVVURY, C., AMERASEKERA, A. Review paper : ESD issues for advanced CMOS technologies. Micro. Reliab. Journal, 1996, vol 36, n°7-8, p907-924. 2. FOWLER, S.L. Triboelectricity and surface do not correlate. EOS/ ESD Symposium, Anaheim, California, September 27-29, 1988, p103-112. 3. R. Y. MOSS, Caution Electrostatic Discharge at Work, IEEE Trans. Comp. Hyb. and Man., CHMT-5, p512-515, 1982. 4. AMERASEKERA, A., DUVVURY, C. ESD in silicon integrated circuit. New-York, John Wiley and sons, 1995, 208p. 5. CHEMELLI, R.G., LINGER, B.A., BOSSARD, P.R. ESD by Static Induction.
P. Salom~, C. Richier I Microelectronic Engineering 49 (1999) 83-94
EOS/ESD Symposium, Las Vegas, Nevada, September 27-29, 1983, p 29-36. 6. AVERY, L.R. Charged device model testing ; trying to duplicate reality. EOS/ESD Symposium, Orlando, Floride, September 29October 1, 1987, p 88-92. 7. VERHAEGE, K., ROUSSEL, P.J., GROESENEKEN, G., et al. Analysis of HBM ESD testers and specifications using a 4th order lumped element model. Proc. of ESREF Symposium, Bordeaux, France, September 27-29, 1993, p 385-393. 8. HYATT,H.M. Critical considerations for ESD testing. EOS/ESD Symposium, Philadelphia, Pennsylvania, October 2-4, 1984, p 104-111. 9. SPEAKMAN, T.S. A model for failure of bipolar Silicon integrated circuits subjected to electrostatic discharge. IEEE International Reliab. Phys. Symp., 1974, p 60-69. 10. MADZY, T.M., PRICE, L.A. Module electrostatic discharge simulator. EOS/ESD Symposium, Denver, Colorado, September 2427, 1979, p 36-40. 11. STANDARD EOS/ESD-S5.1. Human Body Model (HBM) - Component Level. New York, EOS/ESD Association, 1991.13 p. 12. EIAJ-Standard. Testing method 20 : electrostatic destructive test, electrostatic discharge, ESD. 1988. 29p. IC-121-1988. 13. STANDARD MIL-STD 883C notice 8 method 3015.7. Electrostatic Discharge Sensitivity classification. 22 March 1989. pp1811-1816. 14. ROOZENDAAL, L., AMERASEKERA, A., BOS, P., et al. Standard ESD testing of integrated circuits. EOS/ESD Symposium, Orlando, Florida, September 11-13, 1990, p 119-130. 15. VERHAEGE, K., ROBINSON-HAHN, D., RUSS, C., et al. Justifications for reducing HBM and MM ESD qualification test time. Micro. Reliab. Journal, 1996, vol 36, n°ll-12, p 1715-1718. 16. DRAFT STANDARD EOS/ESD-S5.2. Machine Model (MM) - Component Level. New York, EOS/ESD Association, 1992. 10 p.
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17. LUCHIES, J.M. Electrostatic discharge in integrated circuits; testing and protection. PhD thesis : Universiteit Twente Enschede, Pays Bas, 1995. 137 p. ISBN : 90-9008517-3 18. REINER, J.C. A physical model for the creation of latent gate oxide defects by very fast electrostatic discharges. European Symp. on Reliab. of Electron device Failure phy. and anal., Glasgow, Scotland, October 4-7, 1994, p 467-472. 19. REINER, J.C. Latent gate oxide defects caused by CDM-ESD. EOS/ESD Symposium, Phoenix, Arizona, September 11-14, 1995, p 311-321. 20. DRAFT STANDARD EOS/ESD-S5.3. Charged Device Model (CDM) -Component testing. New York, EOS/ESD Association, 1993.13 p. 21. RENNINGER, R.G., JONG, M.C., LIN, D.L., et al. A Field Induced Charged Device Model Simulator. EOS/ESD Symposium, New Orleans, Louisiana, September 26-28, 1989, p 59-71. 22. OLNEY, A. A combined socketed and non-socketed CDM test approach for eliminating real-world CDM failures. EOS/ ESD Symposium, Orlando, Florida, September 10-12, 1996, p 62-75. 23. BRODBECK, T., KAGERER, A. Influence of the device package on the results of CDM tests-Consequences for tester characterization and test procedure. EOS/ ESD Symposium, Reno, Nevada, October 6-8, 1998, p 320-327. 24. CHAINE, M., VERHAEGE, K., AVERY, L., et al.Investigation into Socketed CDM (SCDM) tester parasitics. EOS/ESD Symposium, Reno, Nevada, October 6-8, 1998, p 301-310. 25. SALOME, P., LEROUX, C., MARIOLLE, D., et al. An attempt to explain thermally induced soft failures during low level ESD stresses : study of the differences between soft and hard NMOS failures. EOS/ ESD Symposium, Santa Clara, California, September 23-25, 1997, p 337-345. 26. NOTERMANS, G., DE JONG, P., KUPER, F. Pitfalls when correlating TLP, HBM, and MM testing. EOS/ESD
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P. Salom~, C. Richier I Microelectronic Engineering 49 (1999) 83-94
Symposium, Reno, Nevada, October 6-8, 1998, p 170-176. 27. AMERASEKERA, A., RAMASWAMY, S., CHANG, M., et al. Modeling MOS snapback and parasitic bipolar action for circuit-level E SD and high current simulations. IEEE International Reliab. Phys. Symp., Dallas, Texas, March 25-28, 1996, p 318-326. 28. LIN, D.L. Thermal breakdown of VLSI by ESD pulses. IEEE International Reliab. Phys. Symp., New Orleans, Louisiana, April 3-5, 1990, p 281-287. 29. AUR, S., CHATTERJEE, A. On the robustness of LDD nMOS transistors subjected to measurement of drain breakdown voltage. Solid State Electronics, 1990, vol 33, n°8, p 1043-1048. 30. DUVVURY, C., McPHEE, R.A., ROUNTREE, R.N., et al. Thick oxide device ESD performance under process variations. EOS/ESD Symposium, Las Vegas, Nevada, September 23-25, 1986, p 173-181. 31. AMERASEKERA, A., DUVVURY, C. The impact of technology scaling on ESD robustness and protection circuit design. EOS/ESD Symposium, Las Vegas, Nevada, September 27-29, 1994, p 237-245. 32. DUVVURY, C., ROUNTREE, R.N., BAGLEE, D.A., et al. ESD design considerations for ULSI. EOS/ESD Symposium, Minneapolis, Minnesota, September 10-12, 1985, p 45-48. 33. AVERY,L.R. Using SCR's as transient protection structures in integrated circuits. EOS/ESD Symposium, Las Vegas, Nevada, September 27-29, 1983, p 177-183. 34. CROFT, J.D. Transient supply clamp with a variable RC time constant. EOS/ESD Symposium, Orlando, Florida, September 1012, 1996, p 276-279. 35. MALONEY, T.J., PARAT, K., CLARK, N.K., et al. Protection of High voltage power and programming pins. EOS/ESD Symposium, Santa Clara, California, September 23-25, 1997, p 246-254. 36 KRIEGER, G., NILES, P. Diffused resistors characteristics at high current density levels-Analysis and application. IEEE
Trans. on Electron Devices, 1989, vol ED-36, n°2, p 416-423. 37. NOTERMANS,G. On the use of N-well resistors for uniform triggering of ESD protection elements. EOS/ESD Symposium, Santa Clara, California, September 23-25, 1997, p 221-229. 38. AMERASEKERA, A., CHANG, M.C., SEITCHICK, J.A., et al. Self heating effects in basic semiconductor structures. IEEE Trans. on Electron Devices, 1993, vol 40, n°10, p 1836-1844. 39. MALONEY, T.J., KHURANA, N. Transmission line pulsing techniques for circuit modeling of ESD phenomena. EOS/ ESD Symposium, Minneapolis, Minnesota, September 10-12, 1985, p 49-54. 40. VOLDMAN,S.H. The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation and scaling. IEEE Bip. Circ. Tech. Meeting, Minneapolis, Minnesota, September 27-29, 1998, p 19-30.
Microelectronic Engineering49 (1999) 83-94 www.elsevier.nl/loeate/mee
ElectroStatic Discharges (ESD), Latch-Up and Pad Design Constraints Pascal SALOME, Corinne RICHIER STMicroelectronics, 850 Rue J e a n Monnet, 38926 Crolles Cedex, France Phone: 33 4 76 92 68 18, Fax: 33 4 76 92 64 44, Email: [email protected] a b s t r a c t : This paper is tailored to beginners in the field of electrostatic discharges. After a brief introduction, the basics of ESD are first reviewed and followed by a description of the standards devoted to the protection of intregrated circuits. Then, the behavior and modeling of elementary devices u n d e r ESD are discussed.
1. I N T R O D U C T I O N Static electricity is defined as an electrical charge caused by an imbalance of electrons on the surface of a material. ElectroStatic Discharge (ESD) is defined as the transfer of a charge between two materials at different electrical potentials, one could be a h u m a n body. ESDs m a y affect the electrical characteristics of a semiconductor device or upset the normal operation of an electronic system leading to equipment malfunction or failure. An example resulting from such a discharge can be seen in figure 1. In this case, the electrostatic discharge led to a strong short circuit due to a large melted silicon filament between sources and drains of a cascoded NMOS device.
figure 1: d a m a g e i n d u c e d by an E S D
Damages due to ESD stresses on integrated circuits can be an oxide rupture, a metal or contact burn-out. It can also be a diffusion damage caused by an excessive heating. ESD became a significant problem in silicon ICs as soon as technology feature sizes were reduced to les t h a n 2~m [1]. An approximate technology roadmap is given in table 1. Table 1: Technology road map
Feat~Size:(~tm) :~ ( n ~ ): 2 1 0.8 0.5 0.35 0.25 0.18 0.15
40 20 15 10 7 5 3.5 2.5
: LDD No Yes Yes Yes Yes Yes Yes Yes
s~icide
No No Yes Yes Yes Yes Yes Yes
Advances in IC technology have made circuits and devices smaller and faster but also have greatly increased their susceptibility to ESD. Furthermore, the introduction of both lightly doped drain (LDD) and salicided diffusions led to a so large decrease in the ESD performances t h a t protecting a device became a veritable challenge. Most of the effort in ESD has been
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved. PII: S0167:9317(99)00431-1
84
P. Salom~, C. Richier I Microelectronic Engineering 49 (1999) 83-94
focused on developing protection circuits addressing the LDD and silicide problems and maintaining the ESD protection level, especially with thinning of the gate oxide to less than 7nm. 2. E S D B A S I C S
Controlling ESD begins with understanding how an electrostatic charge occurs. Electrostatic charge may be created on a material in different ways such as by contact and separation of two materials, by induction, ion bombardment or contact with another charged object. In the following, the most common charging methods known as "triboelectric charging" and "charging by induction" are described.
electrons it becomes negatively charged. The polarity and magnitude of the charge are indicated by the positions of the materials in the triboelectric series table which lists materials according to their relative triboelectric charging characteristics [2]. The first material listed in the table takes on a positive charge and the other a negative charge. Materials further apart on the table generate a higher charge than those which are closer (see table 2). Table 2: Electrostatic Triboelectric Series
Most positive
2.1. T r i b o e l e c t r i c C h a r g i n g Triboelectric Charging is refered to describe an electrostatic charge which is created by the contact and separation of two materials, similar or not. This mechanism involves the transfer of electrons between materials. Let us assume two different materials which are electrically neutral. Placed in contact and then separated, electrons are transfered from the surface of one material to the surface of the other (see figure 2). Iaterial A
~
Material
atori
Materials after se?aration
I
~ ~ L I
aterial B[ +lq[
~3ainse l e c . ~ _ _ ~ ]
Polyster
Most negative
Materials in contact
sses eltec.I
figure 2: triboelectric charging When a material losses electrons it becomes positively charged while gaining
Air Human skin Glass Mica Human hair Nylon Aluminum Wood Copper Silver Gold Orlon Polyurethan Vinyl Silicon Teflon Silicon rubber
The process of triboeleetrie charging is really a more complex mechanism than described here above. The amount of charge is affected by the area of contact, the speed of separation, the Relative Humidity (RH) and many other factors. But once the charge is created, an electrostatic discharge will follow which may induce damages within the chip. The level of charge is measured in coulombs but, we commonly speak of electrostatic potential expressed as voltage (Q=C*U). The first most common example of triboelectric charging is a man walking across the floor. He generates static electricity as shoe soles contact and separate from the floor
85
P. SalomJ, C. Richier / Microelectronic Engineering 49 (1999) 83-94
surface. Table 3 gives examples of such a generation [3-4]. The second most common example is an electronic device sliding into or out of a tube which generates a charge as metal leads make multiple contacts and separations with the container. Table 3: Static Voltage as a Function of Humidity
walking across vinyl floor
12kV
0.25kV
walking across carpet
35kV
1.5kV
removing DIPs from plastic tubes
20 kV
5kV
Once created, the lifetime of the charge depends on the electrical characteristics of the materials. Insulators do not allow the flow of electrons and the charge may remain in place for a very long time. Conductive materials allow electrons to flow easily across their surface. As long as the conductor is isolated from other conductors or ground, the charge will remain. However if the conductor is grounded the charge will easily go to ground or if the conductor contacts another conductor, the charge will flow between the two conductors. 2.2. C h a r g i n g b y i n d u c t i o n Charging by induction is the process whereby an uncharged conductor becomes charged when grounded in presence of an electrostatic field. This process can be described in the following way [5]. If a charged object (CO) is brought near an insulated device, it sets up a field in its vicinity which induces a movement of charge into the device remaining globally neutral (see figure 3a). If CO is charged negatively, the potential at A into the device tends to be more negative than at B. Since the potential at every point of the device must be the same, a movement of electrons takes place from A to B. This results in a separation of charges such that positive charges will be at end A and negative charges will be at end B.
If the device is momentarily grounded while within the electrostatic field, a transfer of charge from the device occurs as seen in figure 3b. Therefore, a first electrostatic discharge happens. A net positive charge will be retained when the ground connection is broken as in figure 3c. Cancelling the electrical field by removing CO allows the charge to spread evenly over the device as in figure 3d. If the ground connection is established once again, electrons will flow back to the device bringing it to its neutral condition. This will lead to the occuring of a new ESD but in the opposite polarity. (a)
(b) device
BI-:- :HA
device
BI ~_-~electrons (d)
(c) device
81
device
BI+ ++÷+IA
figure 3a,3b,3c,3d: process of charging by induction As for triboelectric charging, many factors impact on the amount of charge induced into the device such as the relative humidity, the strength of the field and the device's coupling to that field. ESD caused by induction is probably the most insidious ESD event. All surfaces can be charged by charge sharing, i.e. being touched by a charged person or source. Thus, all those surfaces have the potential for sourcing a field that can cause inductive ESD. The parameters controlling the magnitude of the ESD current pulse are the charge on the source, the capacitance of the source to ground and the capacitance of the device to
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P. SalomJ, C. Richier / Microelectronic Engineering 49 (I999) 83-94
the source leading to m a n y unknown values and to a very hazardous phenomenon [6]. 3. E S D S T A N D A R D S In integrated circuit manufacturing and handling environment, there are three principal sources of ESD. The first and most common to date is the one due to h u m a n handling. It has been shown previously that a person can accumulate charges through a triboelectric mechanism. Therefore an electrostatic discharge may effectively happen if this person touches a grounded circuit. The charge exchange which takes place during such an event will be from the person to the device. To simulate this event a first standard was introduced known as H u m a n Body Model (HBM). The second source of ESD takes place in automated test and handling systems. The equipment can accumulate static charge due to improper grounding, which is then transmitted through the IC when it is picked up for placement in the test socket. This discharge is a shorter duration current pulse of higher magnitude compared to an HBM event and, therefore, a second standard was proposed to simulate this event known as Machine Model (MM). The third possible source of ESD is the IC itself which m a y be charged during transport or because of contact with a highly charged surface or when placed in a field. The charge will remain until the IC comes into contact with a grounded surface. Such an event is very different from both H B M and MM due to the nature of the discharge which comes from the device itself and not from an external source. Thus, a third model is used to simulate this kind of ESD known as Charged Device Model (CDM). In this part, these three ESD models are discussed in detail including the methods used to test the sensitivity of ICs and the choice of an appropriate failure criterion.
3.1. H u m a n B o d y M o d e l ( H B M )
HBM discharge occurs in a very short duration, typically of the order of 100ns, with current ranging from 1A to 10A. H B M can be modeled by the LCR circuit shown in figure 4 [7]. It consists of a charged capacitor which is discharged with a series resistance. Whereas different values were proposed for the capacitor and the resistance [8-10], 100pf and 1500f~ are now accepted in any standards [1113].
/
~
DUT ]
R
'
,
'
'
i i i
C
i
Ct
, i i
i ¢
figure 4: ItBM circuit associated to its parasitic components. Cs, stray capacitance; Ct, test board capacitance; L, parasitic inductance which determines the rise time. The discharge waveform of an H B M tester through a 0f~ load is given in figure 5. HBM current waveform 1.2 .< i
1
0.8 0.6
r,1) ea
0.4 0.2 0
I
0
I
I
I
I
5e-08 ]c-O?].5c-OT2c-07Z5e-07]e-07 Time-[s]
VESDf2000VoIts
figure 5: HBM current waveform for an initial voltage capacitance of 2k V. The HBM current pulse can be described by the following equation [14].
P. Salom~, C. Richier / Microelectronic Engineering 49 (1999) 83-94 l(t) = VESDx(1-exp(-R" t))"
(1)
The general test procedure is defined by the MIL-STD-883C method 3015.7 [13], which specifies the calibration of the tester, the number of samples to be tested and also the pin combination. The selection of pin combination is a difficult issue for ICs with large pin count (>64). Each pin is stressed with the substrate pin grounded and stressed once again with the supply pin grounded, all other pins remain floating. Pin to pin combination is also required and consists in stressing each pin against every other pin which is unfeasible for large ICs. Usually the worst-case conditions for the pin to pin combination is only evaluated, namely the pins furthest apart from each other and the pins adjacent to the stressed pin [4]. Another approach, which reduces the severity of the stress and the testing time, is to pulse one pin with all the other non-supply pins grounded. According to the MIL-STD requirements, the stress is performed with three positive followed by three negative pulses spaced of 1 second for a cooling period. However the number of pulses is decreased to one in the JEDEC standard [12] and let to the choice of the user in the EOS/ESD standard [11]. Usually three pulses are prefered to ensure that no cumulative degradations are involved. A recent study showed that in order to reduce the testing time for large pin count devices, the cooling period can be reduced without any thermal non-equilibrium concern [15]. For qualification purposes, devices are stressed at the required pass voltage with new devices for each stress condition. The international specification distinguishes three classes, withstanding HBM voltage is lower than 2kV in which the device is defined as very ESD sensitive, withstanding HBM voltage is higher than 4kV in which the device is defined as ESD insensitive. When passing voltage ranging from 2kV to 4kV, the device is classified as ESD susceptible.
87
3.2. M a c h i n e Model (MM) The equivalent circuit for the Machine Model test is the same as for the HBM one. However, MM consists of a capacitor of 200pF and a series resistor specified at 0f2 [16]. In pratical cases, this series resistor has a finite value. Series inductance is an important parameter which should be defined in any cases (see figure 6). Usually this value ranges from 0.5~H to 2.5~H, but both values are known to induce the same failure modes [17]. The Philips specification requires that L=2.5~H and R=25~ The MM is the standard ESD test method in Japan leading to its general usage by IC manufacturers. Because of the low series resistance, the effect of parasitic circuit are easily detected and it is easier to ensure reproducibility between testers. This feature led to the development of this method in Japan. The MM current pulse can be described by the following equation [14] and is illustrated in figure 6 for different values of the parasitic inductance: .
t
(2)
~LdL.CJ M M current waveform 6 --
"
"
4
" MM(x,b.5p,~) " MM(x,2.51aH) .........
0
-2 -4 -6
0
1e-07
Time-[s]
2e-07
3e-07
4e-07
VESD=400Volts
figure 6: MM current waveform The magnitude of the current is a function of VESD . C ~ showing the dependence of L. The oscillating part is defined by the sinusoidal term in which L and C determine
P. Salomd, C. Richier / Microelectronic Engineering 49 (1999) 83-94
88
the frequency. The damping is described by the resistance and the inductance. If the device resistance does not meet the condition, RL < 2 ~ R, then the damping term dominates and the current waveform becomes that of the HBM. HBM and MM have different forms but failure modes are usually similar and only differ in the severity of the damage.
3.3. C h a r g e d D e v i c e Model (CDM) The concept of CDM is completely different from that of HBM or MM. The discharge comes from the device itself. Therefore the parasitic elements (shown in figure 7) are parasitic resistance and inductance of the ICs. These very low values result in very fast pulses with a short duration that is about lns and high current levels of several amperes.
L
°[ figure 7: CDM equivalent circuit. Because of a very fast transient, the CDM introduces different failure modes from previous test methods, and damages are often revealed in gate oxides of the internal circuitry [18-19]. A standard is currently under development [20]. Draft standard distinguishes between several concepts which are used today in the tester. The charging method can be direct or field induced. In a direct charging method, the charge is applied through a switch and a resistor directly to one of the pins of the device. Charges may spread differently in the
device when a field induced charging method is used [21]. Here the entire package is charged by induction in the presence of an electric field. The field of CDM testing distinguishes two types of testers based on the device positioning: socketed and non-socketed testers. In a socketed tester, devices are inserted in a socket which adds parasitics to the device. Due to these parasitics, the socketed CDM test may significantly differ from the CDM event taking place in a lonely device. However it is also closer to the CDM event which is experienced on a board [22]. In a non socketed CDM test system, devices are placed on a field plate in the dead-bug position. In this category, a second subpartitioning of CDM testers is based on the discharge mode. The discharge can either be initiated by approaching a grounded probe (non-contact mode) or by relay switching (contact mode). Since the CDM test is the hardest available test method being close to real life, an increased demand for this method may be expected. Clearly, the device and the package impedance will have an impact on the CDM waveform [23]. This may explain why the correlation between different types of testers seems to be problematic and why it is so difficult to define a standard which will be approved by everyone [24].
3.4. C h o o s i n g a Failure Criterion Failure criteria are used to determine if the ICs failed during the ESD qualification process. The nature of ESD damage can result in large differences during the measurement of the post-stress leakage curves [25]. However, variations in the severity of the damage can result in a small increase in the leakage current either at the stressed pin or between other pins, especially power supply pins. Therefore, the selection of the failure criterion used during ESD qualification process may significantly impact on the given ESD failure threshold. The best solution is that the stressed device should be subjected to a full functional test after each ESD stress
89
P. Salom~, C. Richier / Microelectronic Engineering 49 (1999) 83-94
but this is often not feasible. ESD testers can only perform simple leakage measurement of the stressed pin. For test time issue, the failure criterion is usually defined as a maximum input or output leakage current at a given bias voltage which could be the DC power supply value. As any change of the initial I-V characteristic is considered as a failure, it is also possible to select a percentage change in leakage current (10% to 50% are often reported). As a conclusion, one must be careful when comparing ESD results obtained with different failure criteria, and with the choice of the failure criterion itself [26]. It is highly recommended that any change in leakage current is monitored and noticed as the onset of failure.
than the I-V curve can be sliced in four main regions which are illustrated in figure 9. Both regions 1 and 2 are governed by the standard NMOS operating mode. Region 3 corresponds to the avalanche breakdown region while region 4 is the bipolar or "snapback" region.
Source
Gate
Drain
_
4. BEHAVIOR OF ELEMENTARY DEVICES U N D E R ESD ESD is a fast transient event leading to a high current level, usually in the range of several amperes. This results that all semiconductor devices, MOS transistors, diodes and resistances, will behave differently during ESD with such high current densities compared to usual operation covered by the standard models. In this part, the high current behavior of MOS transistors, Silicon Controlled Recitifers (SCRs), diode and diffused resistances are discussed. 4.1. MOS Transistors Beside the typical operating conduction, namely linear and saturation region, in which the MOS is designed to operate in usual applications, during an ESD event the transistor is required to conduct much more current and operates in regions which are governed by impact ionization, parasitic device behavior and thermal effects. Figure 8 shows a cross-section of an NMOS transistor indicating the parasitic elements which are involved during high current operating mode. The phenomena associated with the high current effect have been deeply studied analytically and numerically [27]. It results
_
•
_
figure 8: cross.section of an NMOS including parasitic elements
:;:;:~,~.
Vg,=2(Vd} VQ=3{VO) vg=J~J~:
0~6 OO4
Region4 0.~0.0~
~_._--~-..-~-~ ___._ ' ~ . , .
Region3
-0,00 -0,01
=
2
I
4
G
~
I
8
q
P
I0
12 V
figure 9: I - V c u r v e o f a n N M O S f o r different gate voltage The avalanche generation of carriers in the high field region near the drain results in hole current into the substrate. This substrate conduction, which is modelized by a n-cell in figure 8, leads to raise the local substrate
9O
P. SalomJ, C. Richier I Microelectronic Engineering 49 (1999) 8 3 - 9 4
potential near the source and eventually induces the source-substrate junction to become forward-biased. Therefore, electrons are injected from the source into the substrate and collected by the drain. A parasitic NPN bipolar conduction is initiated with the drain acting as the collector, the source as the emitter and the substrate as the base. As the bipolar turns on, an additional current source is provided for the multiplication process. Therefore, less impact ionization are required to sustain the bipolar in the on-state leading to reduce the drain voltage down to a value called Vsp. This phenomenon is often refered to a snapback phenomenon (Vsb is the snapback voltage). To increase the robustness of such a device against ESD, it is important to minimize the power which is dissipated during the conduction and thus to reduce the snapback voltage [28]. A theoretical analysis of the structure given in figure 8 leads to the following analytical expression of the holding voltage depending mainly on two parameters 13and
~
=
exp-L (L is the gate length).
¢r VsB = VBRKLLI
E >0 ~o
"6 -v
14 13 12 11 10 9 8 7 6 5
l+
L2+
2)~ j
observed that the higher the gain, the higher the difference between the breakdown voltage (VBRK) and the minimum holding voltage. The effects of qs, corresponding to the characteristic length of the transmission line modelized by the x-cell in figure 8, are reported in figure 11. We can observe that the thinner the epitaxial (qJ decreases), the faster VSB (holding voltage) will tend to the breakdown voltage.
~o r~
I
2
I
VBRK-'I3
"~=2.9 --~-
'
8 7
i
I
I
2
I
I
I
4 6 8 Gate Length [um]
10
12
figure 11: Effect of substrate coefficient on holding voltage (3)
)
~" 13=0.5
I
•
V=0.5
1o
VBRK = 13
.//~Z " ~
14 13 12 11
~=I t~
I
4 6 8 Gate Length [urn]
>O ~0 .=_ "-6
I
10
12
figure 10: Effect of transistor gain on the holding voltage 13is the gain of the NPN transistor in the high-injection level mode. Its impact on the holding voltage is given in figure 10. It is
8 7.5 7 6.5 6 5.5 ~ . ¢ / 5 ~J 7 4.5 4
...... 2 7.0,1.3,0.65 0.251amCMOS, EPI 2.5g ¢, 0.25p.m CMOS, EPI 4g + 0.251Ltm CMOS, Bulk • I
I
I
I
I
1
2
3
4
5
Gate Length [urn]
figure 12: Impact of substrate on the holding voltage for different substrates. Vbk, b and y are given for simulations
6
91
P. SalomJ, C. Rich&r / Microelectronic Engineering 49 (1999) 83-94
Experimental investigations on 0.25~m CMOS process compared to simulation results are reported in figure 12 for different epitaxial substrates and confirm these previous results. The same behavior can be expected in PMOS transistors except that the bipolar transistor is a PNP transistor. PNP transistors have lower gain than NPN transistors and therefore snapback phenomenon is less important and more difficult to optimize. It has often been reported that PMOS transistors are more sensitive to ESD than NMOS transistors [29]. Another device called FMOS (Field MOS) includes a snapback behavior. This device is formed by two diffusion areas separated by a field oxide as LOCOS [30] As a conclusion, to optimize the ESD robustness of snapback devices, both process and design are important parameters to consider [31-32].
forward-biased diodes. Therefore, SCR has a low power dissipation which is very useful in the design of robust ESD protection circuits. However in nowadays technologies this device is difficult to trigger and becomes less and less popular in deep sub-micron technologies.
Vss
Pad
Rsub P a dR~ nwel figure 13: cross-section of a SCR device
4.2. Silicon C o n t r o l l e d Rectifiers (SCRs) SCR is a low impedance element which consists of PNPN device. It is usually formed by parasitic NPN and PNP devices and can be found in both semiconductor technologies namely CMOS and BICMOS. The triggering of SCR connected between power supply and ground pins is often reported as Latch-Up phenomenon which is another reliability concern in ICs. However, due to its low impedance and to its very low holding voltage, this element can be useful to design a robust ESD protections [33]. A cross-section of a CMOS SCR is observed in figure 13 indicating the parasitic elements. SCRs are defined by the feature that the base area of the NPN transistor is also the collector area for the PNP device. During a high current event, the voltage rises until the SCR is triggered by carriers injected into the base of the PNP or the NPN. Depending on Rnwell, Rsub and the gains of the two bipolar transistors, the NPN or the PNP turns on first. This results in a drastic decrease in the holding voltage. The SCR holding voltage may be as low as 1.2 volt which corresponds to the voltage of two
4.3. D i o d e s In the early years of ESD protection, diodes were often used as protection element in their reverse-biased mode. The protection operates when the applied voltage exceeds the diode's breakdown voltage. However, the protective properties of diodes are limited due to the higher dissipated power, during ESD transient, than in a MOS transistor operating in a snapback mode. Moreover, the series resistance is usually high leading to a too much high holding voltage and, thus, to a protection element not efficient enough. Today, diodes are still often used as protection element but in the forward direction acting as a current director toward a more robust ESD clamp [34] or in a stacked configuration acting as a triggering element for a big ESD clamp [35]. In order that diodes provide an adequate protection capability their dynamic resistances should be optimized. Heating in the forward-biased diode takes place in the P and N regions adjacent to the junction. It is relatively low because of the small electric field in these regions. The ESD failure mechanism in diodes
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can be described by the phenomenon of second breakdown [28]. 4.4. D i f f u s e d R e s i s t a n c e s The diffused resistance is an often used element in ESD protection circuit network [36]. They are mainly used to decouple primary and secondary stage of protection devices included in input or output circuit. Taking advantage of velocity saturation phenomenon for the high current operating mode, these resistances can be designed to have a low impedence at standard operating current and being indeed much more resistive at high current level as during ESD events [36]. In nowadays technologies, a snapback phenomenon may even be found in well resistances. This parasitic bipolar conduction included in well resistance may be explained as follow. As the current saturates, the electric field builds up at the reverse biased N+/N junction. When the field is high enough, impact ionization mechanism occurs leading to hole generation in an N type well resistance. With such a generation a certain area of the Nwell may become neutral and a NPN bipolar is formed. Therefore, a snapback phenomenon is observed. However, the parasitic bipolar included in well resistance is not robust enough to sustain ESD current [37]. As a conclusion some design rules should be followed in order that such diffused resistances do not become the bottleneck of the protection circuit [38]. 5. CONCLUSION During this introduction on electrostatic discharge, the basics of ESD have been first discussed. From the two main charging processes, i.e. triboelectric charging and field induced charging, it appears that all materials can be charged. Once created, these charges result in electrostatic discharges which can induce failures in the components. In the second part, the principles of the Human Body Model, Machine Model and Charged Device Model have been reviewed. The usual ESD test procedures have also been
outlined. Although the best characterization method for optimizing the ESD protection element is using a square pulse current generated with a transmission line, the often used Transmission Line Method (TLP [39]) has not, however, been developed as this is not yet a standard. The choice of failure criteria is also important and should ideally be set at the specification limits of the device under test. In a third part, the operations of elementary devices under high current conditions have been outlined. Optimizing the snapback phenomenon is a key point to design efficient protection circuits but becomes more and more difficult in deeply submicronic technologies with thinner and thinner gate oxides. In this case the marging between Vsp and the oxide breakdown voltage gets smaller and it becomes difficult to protect devices using standard snapback mechanism. The concept of ESD protection circuit designs and some typical ESD protection circuit elements will be discussed later in a second issue. It can be concluded that ESD protection will remain an important issue in the future. The main challenges will be to provide ESD protection circuits for advanced semiconductor chips [40]. REFERENCES 1. DWVVURY, C., AMERASEKERA, A. Review paper : ESD issues for advanced CMOS technologies. Micro. Reliab. Journal, 1996, vol 36, n°7-8, p907-924. 2. FOWLER, S.L. Triboelectricity and surface do not correlate. EOS/ ESD Symposium, Anaheim, California, September 27-29, 1988, p103-112. 3. R. Y. MOSS, Caution Electrostatic Discharge at Work, IEEE Trans. Comp. Hyb. and Man., CHMT-5, p512-515, 1982. 4. AMERASEKERA, A., DUVVURY, C. ESD in silicon integrated circuit. New-York, John Wiley and sons, 1995, 208p. 5. CHEMELLI, R.G., LINGER, B.A., BOSSARD, P.R. ESD by Static Induction.
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